DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3 and 8-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 13 and 9-10 of U.S. Patent No. 11,854,904. The claims of the application correspond to claims of the patent as follows:
Instant application
Patent No. 11,854,904
Difference
Claim 1
A device comprising:
a first semiconductor strip and a second semiconductor strip;
an n-type Fin-Field Effect Transistor (FinFET) comprising:
an n-type source/drain region comprising:
a first layer comprising a first portion and
a second portion overlapping the first semiconductor strip and the second semiconductor strip, respectively, and
a first middle portion joined to the first portion and the second portion, with a first void being under and exposed to the first layer; and
a second layer over and contacting the first layer and comprising a concave top surface, wherein the second layer is separated from the first void by the first layer;
a third semiconductor strip and a fourth semiconductor strip; and
a p-type FinFET comprising:
a p-type source/drain region comprising:
a third layer comprising a third portion and
a fourth portion overlapping the third semiconductor strip and the fourth semiconductor strip, respectively,
wherein the third portion and the fourth portion are spaced apart from each other, with a second void being formed under and exposed to the third layer; and
a fourth layer over the third layer,
wherein a bottom surface of the fourth layer is exposed to the second void, and the fourth layer comprises a convex top surface.
Claim 1
A method comprising:
forming
an n-type Fin-Field Effect Transistor (FinFET) comprising:
forming a first gate stack on a first semiconductor fin and a second semiconductor fin;
etching first portions of the first semiconductor fin and the second semiconductor fin to form a first recess and a second recess, respectively; and
performing first epitaxy processes to form
an n-type source/drain region comprising:
a first layer comprising a first portion grown from the first recess and
a second portion grown from the second recess, and
a first middle portion joined to the first portion and the second portion, with a first void being formed under and exposed to the first layer; and
a second layer over and contacting the first layer and comprising a concave top surface, wherein the second layer is separated from the first void by the first layer, and wherein the concave top surface is viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack;
forming a p-type FinFET comprising:
forming a second gate stack on a third semiconductor fin and a fourth semiconductor fin;
etching second portions of the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; and
performing second epitaxy processes to form
a p-type source/drain region comprising:
a third layer comprising a third portion grown from the third recess and
a fourth portion grown from the fourth recess,
wherein the third portion and the fourth portion are spaced apart from each other, with a second void being formed under and exposed to the third layer; and
a fourth layer over and contacting the third layer, wherein a bottom surface of the fourth layer is exposed to the second void, and the fourth layer comprises a convex top surface.
Method vs device made
Claim 1 defines 1st and 2nd strips
Same
Same
1st layer of instant application overlaps strips, 1st layer of patent grown from and implicitly overlaps recesses
Same
Application defines 3rd and 4th strips
Same
Same
3rd layer of application overlaps 3rd and 4th strips, 3rd layer of patent grown from and implicitly overlaps recesses
Same
Similar
Same
Claim 3
The device of claim 1, wherein the fourth layer comprises:
an additional p-type layer, and a p-type capping layer over and contacting the additional p-type layer, wherein the additional p-type layer and the p-type capping layer have different compositions.
Claim 13
The method of claim 11, wherein the second capping layer and the second epitaxy layer comprise silicon germanium boron, and the second capping layer has a lower germanium atomic percentage than the second epitaxy layer.
Additional p-type layer of application substantially equal to second epitaxy layer of patent.
Claim 8
8. The device of claim 1, wherein the n-type source/drain region comprises:
a first outer portion on a first outer side of the first semiconductor strip; and
a first inner portion between the first semiconductor strip and the second semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are immediately neighboring each other, and wherein the first outer portion is narrow than a half of the first inner portion.
Claim 9
9. The method of claim 1, wherein the n-type source/drain region comprises:
a first outer portion on a first outer side of the first semiconductor fin; and
a first inner portion between the first semiconductor fin and the second semiconductor fin, wherein the first semiconductor fin and the second semiconductor fin are immediately neighboring each other, wherein the first outer portion is narrow than a half of the first inner portion.
Substantially equal; semiconductor strips of application equivalent to semiconductor fins of patent
Claim 9
9. The device of claim 8, wherein the p-type source/drain region comprises:
a second outer portion on a second outer side of the third semiconductor strip; and
a second inner portion between the third semiconductor strip and the fourth semiconductor strip, wherein the second outer portion is wider than a half of the second inner portion.
Claim 10
10. (Original) The method of claim 9, wherein the p-type source/drain region comprises:
a second outer portion on a second outer side of the second semiconductor fin; and
a second inner portion between the third semiconductor fin and the fourth semiconductor fin, wherein the second outer portion is wider than a half of the second inner portion.
Substantially equal; semiconductor strips of application equivalent to semiconductor fins of patent
Although the claims in the instant application include slightly different terminology, these terms are patentably indistinguishable from corresponding limitations in the patent. For example, the term ‘semiconductor strips’ as used in the instant application are remaining portions of recessed semiconductor fins. Therefore, claims 1, 3 and 8-9 are equivalent in scope to claims 1, 13, and 9-10 of the patent. Claims 2, 4-7 and 10 are rejected by virtue of their dependency on rejected claim 1.
Allowable Subject Matter
Claims 1, 3 and 8-9 would be allowable if rewritten or amended to overcome the double patenting rejection(s) set forth in this Office action.
Claims 2, 4-7 and 10 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitations stating:
“an n-type source/drain region comprising:
a first portion comprising a first concave top surface;
a second portion, with the first portion being between the first gate stack and the [[first]]second portion;
a first contact plug extending extend into the second portion; and
a first silicide layer under the first contact plug, wherein the first silicide layer has a second concave top surface; and
a p-type FinFET comprising:
a second gate stack; and
an p-type source/drain region comprising:
a third portion comprising a convex top surface;
a fourth portion, with the third portion being between the second gate stack and the [[third]]fourth portion;
a second contact plug extending extend into the fourth portion; and
a second silicide layer under the second contact plug, wherein the second silicide layer has a third concave top surface” as recited in claim 11, and
“an n-type source/drain region comprising:
a first portion and a second portion; and
a first middle portion between the first portion and the second portion, wherein the first middle portion has a first concave top surface, wherein the first concave top surface is viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack;
a first contact plug, with the first vertical plane being between the first contact plug and the first gate stack;
a first silicide layer underlying the first contact plug and in the n-type source/drain region, wherein the first silicide layer comprises a second concave top surface;
a second gate stack;
a p-type source/drain region comprising:
a third portion and a fourth portion; and
a second middle portion between the third portion and the fourth portion, wherein the second middle portion has a convex top surface, and wherein the convex top surface is viewed from a second vertical plane that is parallel to a second lengthwise direction of the second gate stack;
a second contact plug, with the second vertical plane being between the second contact plug and the second gate stack; and
a second silicide layer underlying the second contact plug and in the p-type source/drain region, wherein the second silicide layer comprises a third concave top surface” as recited in claim 18.
Kim et al. (US-20190393347-A1, hereinafter ‘Kim1’) teaches a middle n-type source/drain region with a concave surface, but fails to teach a middle portion of a p-type source/drain region with a convex surface.
Kim et al. (US-20200403100-A1, hereinafter ‘Kim2’) teaches a middle p-type source/drain region with a convex surface, but fails to teach a middle portion of an n-type source/drain region with a concave surface.
In light of these limitations in the claims (see Applicant’s fig. 11A & ¶ 0045), the previously applied references do not anticipate or obviate the claimed invention as in the context of the claims.
Response to Arguments
Applicant’s arguments, see pages 9-12, filed 7/16/2026, with respect to the formal objections and prior art rejections, have been fully considered and are persuasive. Accordingly, these objections/rejections have been withdrawn.
Applicant's arguments regarding the double patenting rejections have been fully considered but they are not persuasive.
A complete response to a nonstatutory double patenting (NSDP) rejection is either a reply by applicant showing that the claims subject to the rejection are patentably distinct from the reference claims, or the filing of a terminal disclaimer in accordance with 37 CFR 1.321 in the pending application(s) with a reply to the Office action (see MPEP § 1490 for a discussion of terminal disclaimers). Such a response is required even when the nonstatutory double patenting rejection is provisional.
As filing a terminal disclaimer, or filing a showing that the claims subject to the rejection are patentably distinct from the reference application’s claims, is necessary for further consideration of the rejection of the claims, such a filing should not be held in abeyance. Only compliance with objections or requirements as to form not necessary for further consideration of the claims may be held in abeyance until allowable subject matter is indicated. Replies with an omission should be treated as provided in MPEP § 714.03. Therefore, an application must not be allowed unless the required compliant terminal disclaimer(s) is/are filed and/or the withdrawal of the nonstatutory double patenting rejection(s) is made of record by the examiner. See MPEP § 804.02, subsection VI, for filing terminal disclaimers required to overcome nonstatutory double patenting rejections in applications filed on or after June 8, 1995.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRIAN TURNER whose telephone number is (571)270-5411. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at 571-270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BRIAN TURNER/Examiner, Art Unit 2818
Prosecution Insights