DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the first concave top surface and convex top surface must be shown or the features canceled from the claims. No new matter should be entered.
Figs. 7A-8A show a first concave top surface of element 42NB and convex top surface of element 42PC, but does not show the second, third and/or additional concave top surfaces of respective first and second silicide layers, as recited in claims 4, 7, 11 and 18. Fig. 11A shows second and third concave top surfaces of silicide layers DSN and DSP, but does not show the first concave top surface or the convex top surface as recited in claims 1, 11 and 18.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "42PA" and "42PB" have both been used to designate the first epitaxial layer. Furthermore, the element corresponding to the third epitaxial layer is unlabeled.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 11 and 13 is objected to because of the following informalities: The Examiner suggests the following amendments to correct apparent typographic errors.
Claim 11. “…a first contact plug extending into the second portion…”, and
“…a second contact plug extending into the fourth portion…”
Claim 13 “…a second epitaxy layer
Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 3 and 8-9 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 13 and 9-10 of U.S. Patent No. 11,854,904. The claims of the application correspond to claims of the patent as follows:
Instant application
Patent No. 11,854,904
Difference
Claim 1
A device comprising:
a first semiconductor strip and a second semiconductor strip;
an n-type Fin-Field Effect Transistor (FinFET) comprising:
an n-type source/drain region comprising:
a first layer comprising a first portion and
a second portion overlapping the first semiconductor strip and the second semiconductor strip, respectively, and
a first middle portion joined to the first portion and the second portion, with a first void being under and exposed to the first layer; and
a second layer over and contacting the first layer and comprising a concave top surface, wherein the second layer is separated from the first void by the first layer;
a third semiconductor strip and a fourth semiconductor strip; and
a p-type FinFET comprising:
a p-type source/drain region comprising:
a third layer comprising a third portion and
a fourth portion overlapping the third semiconductor strip and the fourth semiconductor strip, respectively,
wherein the third portion and the fourth portion are spaced apart from each other, with a second void being formed under and exposed to the third layer; and
a fourth layer over the third layer,
wherein a bottom surface of the fourth layer is exposed to the second void, and the fourth layer comprises a convex top surface.
Claim 1
A method comprising:
forming
an n-type Fin-Field Effect Transistor (FinFET) comprising:
forming a first gate stack on a first semiconductor fin and a second semiconductor fin;
etching first portions of the first semiconductor fin and the second semiconductor fin to form a first recess and a second recess, respectively; and
performing first epitaxy processes to form
an n-type source/drain region comprising:
a first layer comprising a first portion grown from the first recess and
a second portion grown from the second recess, and
a first middle portion joined to the first portion and the second portion, with a first void being formed under and exposed to the first layer; and
a second layer over and contacting the first layer and comprising a concave top surface, wherein the second layer is separated from the first void by the first layer, and wherein the concave top surface is viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack;
forming a p-type FinFET comprising:
forming a second gate stack on a third semiconductor fin and a fourth semiconductor fin;
etching second portions of the third semiconductor fin and the fourth semiconductor fin to form a third recess and a fourth recess, respectively; and
performing second epitaxy processes to form
a p-type source/drain region comprising:
a third layer comprising a third portion grown from the third recess and
a fourth portion grown from the fourth recess,
wherein the third portion and the fourth portion are spaced apart from each other, with a second void being formed under and exposed to the third layer; and
a fourth layer over and contacting the third layer, wherein a bottom surface of the fourth layer is exposed to the second void, and the fourth layer comprises a convex top surface.
Method vs device made
Claim 1 defines 1st and 2nd strips
Same
Same
1st layer of instant application overlaps strips, 1st layer of patent grown from and implicitly overlaps recesses
Same
Application defines 3rd and 4th strips
Same
Same
3rd layer of application overlaps 3rd and 4th strips, 3rd layer of patent grown from and implicitly overlaps recesses
Same
Similar
Same
Claim 3
The device of claim 1, wherein the fourth layer comprises:
an additional p-type layer, and a p-type capping layer over and contacting the additional p-type layer, wherein the additional p-type layer and the p-type capping layer have different compositions.
Claim 13
The method of claim 11, wherein the second capping layer and the second epitaxy layer comprise silicon germanium boron, and the second capping layer has a lower germanium atomic percentage than the second epitaxy layer.
Additional p-type layer of application substantially equal to second epitaxy layer of patent.
Claim 8
8. The device of claim 1, wherein the n-type source/drain region comprises:
a first outer portion on a first outer side of the first semiconductor strip; and
a first inner portion between the first semiconductor strip and the second semiconductor strip, wherein the first semiconductor strip and the second semiconductor strip are immediately neighboring each other, and wherein the first outer portion is narrow than a half of the first inner portion.
Claim 9
9. The method of claim 1, wherein the n-type source/drain region comprises:
a first outer portion on a first outer side of the first semiconductor fin; and
a first inner portion between the first semiconductor fin and the second semiconductor fin, wherein the first semiconductor fin and the second semiconductor fin are immediately neighboring each other, wherein the first outer portion is narrow than a half of the first inner portion.
Substantially equal; semiconductor strips of application equivalent to semiconductor fins of patent
Claim 9
9. The device of claim 8, wherein the p-type source/drain region comprises:
a second outer portion on a second outer side of the third semiconductor strip; and
a second inner portion between the third semiconductor strip and the fourth semiconductor strip, wherein the second outer portion is wider than a half of the second inner portion.
Claim 10
10. (Original) The method of claim 9, wherein the p-type source/drain region comprises:
a second outer portion on a second outer side of the second semiconductor fin; and
a second inner portion between the third semiconductor fin and the fourth semiconductor fin, wherein the second outer portion is wider than a half of the second inner portion.
Substantially equal; semiconductor strips of application equivalent to semiconductor fins of patent
Although the claims in the instant application include slightly different terminology, these terms are patentably indistinguishable from corresponding limitations in the patent. For example, the term ‘semiconductor strips’ as used in the instant application are remaining portions of recessed semiconductor fins. Therefore, claims 1, 3 and 8-9 are equivalent in scope to claims 1, 13, and 9-10 of the patent. Claims 2, 4-7 and 10 are rejected by virtue of their dependency on rejected claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 4-7 and 11-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 4 recites “a first silicide layer underlying the contact plug, wherein the first silicide layer has a first additional concave top surface” in lines 7-8, and claim 7 recites “a second silicide layer on the p-type source/drain region, wherein the second silicide layer has a second additional concave top surface” in lines 2-3. These features have support in fig. 11A, which shows silicide layers DSN and DSP with concave top surfaces.
Claims 4 and 7 depend directly or indirectly, on claim 1, which requires the features of “an n-type source/drain region comprising:
…a second layer over and contacting the first layer and comprising a concave top surface” and
“a p-type source/drain region comprising:
…a fourth layer over the third layer, wherein a bottom surface of the fourth layer is exposed to the second void, and the fourth layer comprises a convex top surface” (emphasis added). Therefore, claim 4 requires an n-type source/drain region including both of an epitaxial layer with a concave top surface, and a silicide layer with a concave top surface. Similarly, claim 7 requires a p-type source/drain region including both of an epitaxial layer with a convex top surface, and a silicide layer with a concave top surface.
Fig. 8A and related text discloses an n-type source/drain region 42N, including epitaxial layer 42NC with a concave top surface, and a p-type source/drain region 42P, including epitaxial layer 42PC with a convex top surface. However, fig. 8A does not disclose silicide layers on source/drain regions 42N and 42P. Fig. 11A and related text discloses silicide layer DSN on 42N and silicide layer DSP on 42P with concave top surfaces. However, in order to form the silicide layers, the concave top surface of 42N and the convex top surface of 42PC are removed (fig. 10), such that fig. 11A does not include the concave top surface of epitaxial layer 42NC, or the concave top surface of epitaxial layer 42PC. Accordingly, the application as originally filed does not provide support for the features of claims 4-7.
Claims 11 and 18 contain limitations similar to those of claims 4 and 7, namely an n-type source/drain region comprising a concave top surface, a first silicide layer with a concave top surface on the n-type source/drain region, a p-type source/drain region comprising a convex top surface, and a second silicide layer with concave top surface on the p-type source/drain region. Accordingly, claims 11 and 18 are rejected under 35 USC § 112(a) for the same reasons.
Claims 12-17 and 19-20 depend on claims 11 and 18, and are rejected under 35 USC § 112(a) for implicitly including the unsupported subject matter above.
Claim 11 further recites the limitations “…a second portion, with the first portion being between the first gate stack and the first portion…” and “…a fourth portion, with the third portion being between the second gate stack and the third portion…” (emphasis added).
These limitations are indefinite, as they both include circular dependencies (a first portion between itself and a gate stack, and a third portion between itself and a gate stack).
For the purposes of compact prosecution, the Examiner has interpreted claims 4, 7, 11 and 18 as follows:
4. The device of claim 3, wherein the n-type FinFET further comprises a gate stack, and the p-type capping layer comprises:
a first part having a first lateral distance from the gate stack;
a second part having a second lateral distance from the gate stack, with the second lateral distance being greater than the first lateral distance;
a contact plug penetrating through the second part; and
a first silicide layer underlying the contact plug
7. The device of claim 4 further comprising:
a second silicide layer on the p-type source/drain region
11. A device comprising:
an n-type Fin-Field Effect Transistor (FinFET) comprising:
a first gate stack; and
an n-type source/drain region comprising:
a first portion
a second portion, with the second portion being between the first gate stack and the first portion;
a first contact plug extending into the second portion; and
a first silicide layer under the first contact plug, wherein the first silicide layer has a second concave top surface; and
a p-type FinFET comprising:
a second gate stack; and
an p-type source/drain region comprising:
a third portion
a fourth portion, with the fourth portion being between the second gate stack and the third portion;
a second contact plug extend into the fourth portion; and
a second silicide layer under the second contact plug, wherein the second silicide layer has a third concave top surface.
18. A device comprising:
a first gate stack;
an n-type source/drain region comprising:
a first portion and a second portion; and
a first middle portion between the first portion and the second portion
a first contact plug, with the first vertical plane being between the first contact plug and the first gate stack;
a first silicide layer underlying the first contact plug and in the n-type source/drain region, wherein the first silicide layer comprises a second concave top surface;
a second gate stack;
a p-type source/drain region comprising:
a third portion and a fourth portion; and
a second middle portion between the third portion and the fourth portion
a second contact plug, with the second vertical plane being between the second contact plug and the second gate stack; and
a second silicide layer underlying the second contact plug and in the p-type source/drain region, wherein the second silicide layer comprises a third concave top surface.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11, 13, 16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Kim et al. (PG Pub. No. US 2019/0244963 A1).
Regarding claim 11, Kim teaches a device comprising:
an n-type Fin-Field Effect Transistor (FinFET) (¶ 0195: n-type transistor in region III) comprising:
a first gate stack (¶ 0223: 586 disposed in region III); and
an n-type source/drain region (¶ 0217: 526) comprising:
a first portion (¶ 0217: 506B) comprising a first concave top surface (not given patentable weight- see 112 rejection above);
a second portion (¶ 0217: 506c), with the first portion being between the first gate stack and the first portion (fig. 88: at least a portion of 506c disposed between 506b and 586; see 112 rejection above for claim interpretation);
a first contact plug (¶ 0231: 656) extend into the second portion (fig. 95 among others: 656 extends into 506c); and
a first silicide layer (¶ 0230: 626) under the first contact plug (fig. 95: 626 disposed under 656), wherein the first silicide layer has a second concave top surface (fig. 99: 626 includes a concave top surface); and
a p-type FinFET (¶ 0195: p-type transistor in region II) comprising:
a second gate stack (¶ 0225: 584 disposed in region II); and
an p-type source/drain region (¶ 0209: 524) comprising:
a third portion (¶ 0209: 504b) comprising a convex top surface (not given patentable weight- see 112 rejection above);
a fourth portion (¶ 0209: 504c), with the third portion being between the second gate stack and the third portion (fig. 87: at least a portion of 504c disposed between 504b and 584; see 112 rejection above for claim interpretation);
a second contact plug (¶ 0212: 654) extend into the fourth portion (fig. 95: 654 extends into 504c); and
a second silicide layer (¶ 0230: 624) under the second contact plug (fig. 95: 624 disposed under 654), wherein the second silicide layer has a third concave top surface (fig. 98: 624 includes a concave top surface).
Regarding claim 13, Kim teaches the device of claim 11, wherein the n-type source/drain region comprises:
a first epitaxy layer (¶ 0219: 506b), wherein the first epitaxy layer comprises a first part, a second part, and a middle part joining the first part to the second part (fig. 83: first and second portions of 506b formed on active regions 406, joined by merged portion of 506b), wherein the first part, the second part and the middle part are formed of a same material (¶ 0219 & fig. 83: first, second and third portions of 506b formed by a same SEG process, and therefore implicitly formed of a same material);
a first void overlapped by the middle part (fig. 83: gap below merged portion of 560b), with a bottom surface of the first epitaxy layer being exposed to the first void (fig. 83: merged portion of 506b exposed to gap); and
a second epitaxy layer (¶ 0219: 506c) and contacting the first epitaxy layer (fig. 83: 506c contacts 506b), wherein a top surface of the second epitaxy layer contacts the first silicide layer (fig. 95: top surface of 506c electrically and/or physically contacts 626).
Regarding claim 16, Kim teaches the device of claim 11, wherein the first contact plug penetrates through a first capping layer of the n-type source/drain region (¶ 0219 & fig. 99: 656 penetrates through capping layer 516), and the second contact plug penetrates through a second capping layer of the p-type source/drain region (¶ 0209 & fig. 98: 652 penetrates through capping layer 514).
Regarding claim 18, Kim teaches a device (fig. 100 among others) comprising:
a first gate stack (¶ 0225: gate structure 586 in region III);
an n-type source/drain region (¶¶ 0197, 0219: source/drain structure 526 in n-type region III) comprising:
a first portion and a second portion (figs, 83, 95 among others: portions of 506b disposed on active regions 406); and
a first middle portion between the first portion and the second portion (figs. 83, 95: merged portion of 506b), wherein the first middle portion has a first concave top surface, wherein the first concave top surface is viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack (not given patentable weight; see 112 rejection above);
a first contact plug (¶ 0212: 656), with a first vertical plane being between the first contact plug and the first gate stack (figs. 99-100: in region III, vertical plane between 656 and 586);
a first silicide layer (¶ 0230: 626) underlying the first contact plug and in the n-type source/drain region (figs. 95-99: 626 underlies 656 in 526), wherein the first silicide layer comprises a second concave top surface (fig. 99: 626 includes a concave top surface);
a second gate stack (¶ 0225: gate structure 584 in region II);
a p-type source/drain region (¶ 0209: source/drain structure 524 in p-type region II) comprising:
a third portion and a fourth portion (¶ 0209 & fig. 95: left and right portions of 504b); and
a second middle portion between the third portion and the fourth portion (¶ 0209 & fig. 95: middle portion of 504c), wherein the second middle portion has a convex top surface, and wherein the convex top surface is viewed from a second vertical plane that is parallel to a second lengthwise direction of the second gate stack (not given patentable weight; see 112 rejection above);
a second contact plug (¶ 0212: 654), with the second vertical plane being between the second contact plug and the second gate stack (fig. 95: vertical plane between 654 and 584); and
a second silicide layer (¶ 0230: 624) underlying the second contact plug and in the p-type source/drain region (fig. 95: 624 disposed under 654 and in 624), wherein the second silicide layer comprises a third concave top surface (fig. 98” 624 has concave top surface).
Regarding claim 19, Kim teaches the device of claim 18, wherein the first silicide layer penetrates through a first capping layer of the n-type source/drain region (fig. 95: 656 penetrates through layer 516), and the second silicide layer penetrates through a second capping layer of the p-type source/drain region (fig. 95: 654 penetrates through layer 465).
Regarding claim 20, Kim teaches the device of claim 18, wherein the first silicide layer and the second silicide layer are in contact with a first middle layer of the n-type source/drain region and a second middle layer of the p-type source/drain region, respectively (figs. 95-99: 656 and 654 in at least electrical contact with respective middle layer portions of 526 and 524), and the first middle layer and the second middle layer are in contact with the first capping layer and the second capping layer, respectively (figs. 95-99: middle layer portions of 526 and 524 are in contact with 516 and 465).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 11 above, and further in view of Park et al. (PG Pub. No. US 2016/0351570 A1).
Regarding claim 12, Kim teaches the device of claim 11, comprising an n-type source/drain region (526) and a p-type source/drain region (524).
Kim does not teach the device further comprising:
a contact etch stop layer on the n-type source/drain region and the p-type source/drain region, wherein the contact etch stop layer comprises a vertical portion contacting the third portion of the p-type source/drain region to form a vertical interface.
Park teaches a device (¶ 0032: 100) including a contact etch stop layer (¶¶ 0033-0034: 154 & 254) on an n-type source/drain region (¶ 0033-0034 & fig. 2A: portion 154 formed on source/drain 110 in n-type region I) and the p-type source/drain region (fig. 2B: portion 254 formed on source/drain 210 in p-type region II), wherein the contact etch stop layer comprises a vertical portion contacting a third portion of the p-type source/drain region to form a vertical interface (fig. 2B, 7A, 8B and/or 9B: 254 comprises portion extending vertically and contacting a third portion of 210).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the device of Kim with a contact etch stop layer, as a means to protect the n-type and p-type source/drain regions during subsequent manufacturing processes, such as contact formation (654/656 of Kim, C1/C2 of Park).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 11 above, and further in view of Choi et al. (PG Pub. No. US 2020/0020773 A1).
Regarding claim 14, Kim teaches the device of claim 13, wherein the p-type source/drain region comprises:
a third epitaxy layer (¶ 0209: 504b) comprising a third part and a fourth part (fig. 83: 504b comprises portions disposed on active regions 404);
a fourth epitaxy layer (¶ 0209: 504c) over the third epitaxy layer and connecting the third part to the fourth part (fig. 83: 504c disposed over portions of 504b and connects portions of 504b); and
a second void (fig. 83: gap disposed under 504b), wherein bottom surfaces of the third epitaxy layer, the third part, and the fourth part are exposed to the second void (fig. 83: bottom of 504b, including third and fourth parts, exposed to gap under 504b).
Kim does not teach the fourth part separated from the third part.
Choi teaches a device (figs. 18-19 among others) including a p-type source/drain region (¶ 0025: SD1) comprising third and fourth parts of a third epitaxial layer (¶ 0038: SP2) and a fourth epitaxy layer (¶ 0038: SP3) over the third epitaxy layer and connecting the third part to the fourth part (fig. 19B: SP3 disposed over and connects portions of SP2), wherein the fourth part is separated from the third part (fig. 19B: portions of SP2 physically separate).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the third epitaxial layer of Kim with the separation of Choi, as a means to optimize the composition of the fourth epitaxy layer relative to the third epitaxy layer (Choi, ¶ 0043), reducing resistance of the source/drain pattern to help improve electrical characteristics of the semiconductor device (Choi, ¶ 0119).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 11 above, and further in view of Lee et al. (PG Pub. No. US 2019/0131434 A1).
Regarding claim 15, Kim teaches the device of claim 11, wherein the first concave top surface (not given patentable weight; see 112 rejection above) and the second concave top surface are viewed from a first vertical plane that is parallel to a first lengthwise direction of the first gate stack (fig. 100: top surface of 626 includes a concave shape in a vertical plane parallel to lengthwise direction of 586), and the convex top surface (not given patentable weight; see 112 rejection above) and the third concave top surface are viewed from a second vertical plane (fig. 98: vertical plane extending in the 1st direction).
Kim does not teach wherein the second vertical plane that is parallel to a second lengthwise direction of the second gate stack.
Lee teaches a device (¶ 0011: 100) including a silicide layer (¶ 0062: 82) under a contact plug (¶ 0042: 102) extending into a source/drain region (¶ 0010 & fig. 15B: 102/82 extend into source/drain region 80), wherein the silicide layer comprises a concave top surface as viewed from a vertical plane that is parallel to a second direction of a gate stack (¶ 0054 & figs. 12-15B: 82 includes a concave top surface as viewed from a vertical plane extending a lengthwise direction of gate stack 97).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the third concave top surface of Kim in the direction of Lee, as a means to increase surface area between the source/drain region and the contact plug, providing lower source/drain contact resistance, improved production yield and better device performance.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 16 above, and further in view of Li et al. (PG Pub. No. US 2017/0194495 A1) and Li et al. (PG Pub. No. US 2019/0097006 A1, hereinafter referenced as ‘Li-006’).
Regarding claim 17, Kim teaches the device of claim 16, comprising first and second capping layers (516, 514). Kim further teaches capping layers comprise epitaxial semiconductor material (¶ 0149).
Kim does not teach wherein the first capping layer comprises SiGeP, and the second capping layer comprises SiGeB.
Li teaches a device (¶ 0027: 300) including a first capping layer comprising SiGeP (¶ 0034: cap layer 317 of NFET structure 303 includes SiGe with implanted phosphorous ions).
Li-006 teaches a device (¶ 0064) including a second capping layer comprising SiGeB (¶ 0035: boron doped silicon germanium layer 220-3).
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to configure the first capping layer of Kim with SiGeP, as a means to prevent ions in the source/drain portions from segregating to the top surface of the silicon substrate after sequent thermal and cleaning processes (Li, ¶ 0035). Furthermore, it would have been obvious to said artisan to configure the second capping layer of Kim with SiGeB, as a means to optimize carrier concentration in the second source/drain region, minimizing resistance of the source/drain structure.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. In the instant case, the materials of Li and Li-006 are suitable for providing the capping layers of Kim, and are therefore a matter of obvious design choice.
Allowable Subject Matter
Claims 1-3 and 8-9 would be allowable if rewritten or amended to overcome the double patenting rejection(s) set forth in this Office action.
Claims 4-7 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
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/BRIAN TURNER/Examiner, Art Unit 2818
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