Prosecution Insights
Last updated: October 01, 2026
Application No. 18/363,554

FINFET DEVICE AND METHOD

Non-Final OA §102§103§112
Filed
Aug 01, 2023
Priority
Jan 15, 2021 — divisional of 17/150,044
Examiner
WILCZEWSKI, MARY A
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
712 granted / 839 resolved
+16.9% vs TC avg
Moderate +10% lift
Without
With
+10.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
38 currently pending
Career history
870
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
44.5%
+4.5% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
21.7%
-18.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 839 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION This Office action is in response to the Request for Continued Examination (RCE) filed 07 August 2026. Claims 1-20 are pending in the application. This application is a divisional of application Serial No. 17/150,044, filed on 15 January 2021, still pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 14 July 2026 has been entered. Claim Rejections - 35 USC § 112 In light of Applicant’s amendment and remarks, the rejections of claim 18 under 35 U.S.C. 112(a) and 35 U.S.C. 112(b) have been withdrawn. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-5 and 10 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Lee et al., US 2019/0043959, of record. With respect to claim 1, Lee et al. disclose a device, shown in Fig. 21, comprising: a fin FA (see paragraphs [0023]-[0028]) extending from a semiconductor substrate 110, see Fig. 21; a gate stack 122 (see paragraphs [0029]-[0032]) over the fin FA, see Fig. 21; a spacer 124 on a sidewall of the gate stack 122, see Fig. 21; a source/drain region 114 in the fin FA adjacent the spacer 124, see Fig. 21; an inter-layer dielectric layer (ILD) 126 extending over the gate stack 122, the spacer 124, and the source/drain region 114 (see paragraph [0033]), see Fig. 21; a contact plug 140 extending through the ILD 126 and contacting the source/drain region 114 (see paragraphs [0039], [0040], and [0062]), see Fig. 21; a dielectric layer 136/138 comprising a first portion 138 on a top surface of the ILD 126 (see Figs. 20 and 21) and a second portion 136 extending between the ILD 126 and the contact plug 140, shown in Figs. 20 and 21), wherein the first portion 138 and the second portion 138 are discontinuous, as shown in Fig. 21, wherein a top surface of the second portion 136 is closer to the substrate 110 than the top surface of the ILD 126, as shown in Fig. 21, wherein a bottom surface of the dielectric layer 138 that is closest to the semiconductor substrate 110 is farther from the semiconductor substrate 110 than a top surface of the gate stack 122; and an air gap 130R2 (see Fig. 19) between the spacer 124 and the contact plug 140, wherein the second portion 136 of the dielectric layer 136/138 seals the top of the air gap 130R2, as shown in Fig. 21, see paragraphs [0117]-[0122]. With respect to claim 2, the device of Lee et al. further comprises a conductive material 174 extending on the ILD 126, the second portion 136, and the contact plug 140, see Fig. 7. With respect to claim 3, in the device of Lee et al., the conductive material 174 is separated from the air gap 134D (in Fig. 7, see paragraph [0069]) by the second portion 136, as shown in Fig. 7. With respect to claim 4, the first portion 138 is separated from the second portion 138 by the conductive material 174, since the first portion 138 and the second portion 136 are discontinuous along the sidewall of the first portion 138, as shown in Fig. 7. With respect to claim 5, in the device of Lee et al., the dielectric layer 136/138 comprises silicon nitride, see paragraphs [0117] and [0121]. With respect to claim 10, in the device of Lee et al., a bottom surface of the second portion 136 is farther from the substrate 110 than a bottom surface of the ILD 126, as shown in Fig. 21. Claims 16-20 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Cheng et al., US 2019/0334011, of record. With respect to claim 16, Cheng et al. disclose a device, shown in Fig. 9, comprising: a contact structure 701 on an epitaxial source/drain region 103A/103B (see paragraphs [0028] and [0043]), see Figs. 6-7; a first air gap 200 (air gap disposed on the right side of contact structure 701) over the epitaxial source/drain region 103A/103B and adjacent the contact structure 701, as shown in Fig. 9, wherein the contact structure 701 extends along a first side of the first air gap 200; a first spacer 150 (see Fig. 6) extending along a second side of the first air gap 200; first dielectric layer 190 above the first spacer 150, wherein the first dielectric layer 190 extends along the second side of the first air gap 200 (air gap disposed on the right side of contact structure 701), wherein the first dielectric layer is a first dielectric material, see paragraph [0045]; and a region of a second dielectric material 1022 (see Figs. 1 and 9) extending over the first air gap 200 from the first dielectric layer 190 to the contact structure 701, as shown in Fig. 9, wherein the second dielectric material 1022 (Paragraph [0030]: “The dielectric material spacers 1022 can include or be formed of silicon boron carbon nitride (SiBCN).”) is different from the first dielectric material (SiO2, see paragraph [0045]). With respect to claim 17, as shown in Fig. 9 of Cheng et al., the first air gap 200 (air gap disposed on the right side of contact structure 701) is adjacent a first side of the contact structure 701 and further comprising a second air gap 200 (air gap disposed on the left side of contact structure 701) adjacent a second side of the contact structure 701, as shown in Fig. 9. With respect to claim 18, the device of Cheng et al. further comprises a second dielectric layer 1022 over the first dielectric layer 190 (the second dielectric layer 1022 extends over the bottom surface of the first dielectric layer 190, as shown in Fig. 9), wherein the second dielectric layer 1022 comprises the second dielectric material 1022 (Paragraph [0030]: “The dielectric material spacers 1022 can include or be formed of silicon boron carbon nitride (SiBCN).”). With respect to claim 19, in the device of Cheng et al., the contact structure 701 has a width near the bottom of the contact structure 701 that is smaller than a width near the top of the contact structure 701. Since the contact structure 701 has an inverse T-shaped cross-sections 702, as shown in Fig. 7, the portions of 702 under air gap spacer regions 703 have a width that is smaller than the width of the top cross section 701, as shown in annotated Fig. 9 below. PNG media_image1.png 709 715 media_image1.png Greyscale With respect to claim 20, in the device of Cheng et al., the contact structure 701 comprises a spacer layer 150 on a sidewall of a conductive material 170, see Figs. 6 and 7 and paragraphs [0038]-[0043]. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11, 12, 14, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0043959, in view of Cheng et al., US 2019/0334011, both of record. With respect to claim 11, Lee et al. disclose a device, shown in Fig. 4, comprising: a gate structure 122 (see paragraphs [0029]-[0032]) over a semiconductor fin FA (see paragraphs [0023]-[0028]), see Fig. 4; a source/drain region 114 in the semiconductor fin FA, wherein the source/drain region 114 comprises a semiconductor material (see paragraphs [0036]-[0038]), see Fig. 4; a first spacer layer 124 over a sidewall of the gate structure 122, see Fig. 4; a source/drain contact 142 on a top surface of the source/drain region 114, as shown in Fig. 4; a second spacer layer 144 over a sidewall of the source/drain contact 142, as shown in Fig. 4; a first dielectric layer 132A on a sidewall of the second spacer layer 144, wherein the first dielectric layer 132A extends over air gap 134A (see paragraph [0059]), wherein the air gap 134A exposes a bottom surface of the first dielectric layer 132A, a sidewall of the first spacer layer 124, a sidewall of the second spacer layer 144, and the semiconductor material of the source/drain region 114 at a top surface of the semiconductor material of the source/drain region 114, as shown in Fig. 4. Although Lee et al. disclose source/drain regions 114, Lee et al. lack anticipation only of the source/drain regions being epitaxial source/drain regions. In the same field of endeavor, Cheng et al. disclose an epitaxial source/drain region 103A/103B in the semiconductor fin 101 (see paragraph [0029]), wherein the epitaxial source/drain region 103A/103B comprises a semiconductor material, see paragraphs [0031] and [0057], see Fig. 1. In light of the teaching of Cheng et al., it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that source/drain regions 114 could be epitaxially grown over the S/D portions of the fin FA in the known device of Lee et al. to increase the S/D volume and provide a larger surface for forming the necessary conductive contacts on the source/drain regions. With respect to claim 12, the device of Lee et al. further comprises a conductive material 146 physically contacting top surfaces of the first dielectric layer 132A, the second spacer layer 144, and the source/drain contact 142, as shown in Fig. 4. With respect to claim 14, in the device of Lee et al., the first dielectric layer 132A is higher than the first spacer layer 124, as shown in Fig. 4. With respect to claim 15, the device of Lee et al. further comprises a second dielectric layer 126 over the first spacer layer 124, wherein the first dielectric layer 132A physically contacts a sidewall of the second dielectric layer 126, as shown in Fig. 4. Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al., US 2019/0043959, as applied to claim 1 above. With respect to claim 6, although Lee et al. disclose the top surface of the second portion is below the top surface of ILD 126, as shown in Fig. 2, Lee et al. lack anticipation of the top surface of the second portion is in the range between 0 nm and 15 nm below the top surface of the ILD 126. However, it has been well established that . "where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Hence, requiring in claim 6 that the top surface of the second portion is in the range between 0 nm and 15 nm below the top surface of the ILD 126 would have been obvious to the skilled artisan and clearly ascertainable through routine experimentation, since Lee et al. teach that general conditions of the claim, that is, that the top surface of the second portion is below the top surface of ILD 126, as shown in Fig. 2. The distance the top surface of the second portion is below the top surface of the ILD 126 does not patentably distinguish Applicant’s claimed device from the known device of Lee et al. With respect to claims 7-9 as to the vertical thickness and width of the second portion (dependent claims 7 and 8, respectively), and the vertical thickness of the first portion (dependent claim 9), Lee et al. do not disclose these claimed vertical thicknesses and width. However, it is clear from Fig. 2 of Lee et al. that the second portion, shown above in annotated Fig. 2, has a vertical thickness and a width and that the first portion, also shown in annotated Fig. 2 above, has a vertical thickness. Although Lee et al. do not disclose the claimed range of vertical thicknesses and width, it has been well established that "where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) Hence, the claimed vertical thickness and width of the second portion and the vertical thickness of the first portion would have been obvious to the skilled artisan and clearly ascertainable through routine experimentation, and, accordingly, do not patentably distinguish Applicant’s claimed device from the known device of Lee et al. Allowable Subject Matter Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 13, Lee et al. fails to teach or suggest that a bottom surface of the conductive material 146 is lower than a top surface of the second spacer layer 144, as shown in Fig. 27B of the instant application. As shown in Fig. 4 of Lee et al., the bottom surface of the conductive material 146 is coplanar with a top surface of the second spacer layer 144. Response to Arguments Applicant's arguments filed 14 July 2026 have been fully considered but they are not persuasive. Independent claim 1 has been amended to require “the first portion and the second portion are discontinuous”. Lee et al. clearly show in Fig. 21, a dielectric layer 136/138 comprising a first portion 138 on a top surface of the ILD 126 (see Figs. 20 and 21) and a second portion 136 extending between the ILD 126 and the contact plug 140, shown in Figs. 20 and 21), wherein the first portion 138 and the second portion 138 are discontinuous. Therefore, amended claim 1 fails to patentably distinguish Applicant’s claimed device from the prior art device of Lee et al. shown in Fig. 21. Independent claim 11 has been amended to require “the air gap exposes a bottom surface of the first dielectric layer, a sidewall surface of the first spacer layer, a sidewall surface of the second spacer layer, and the semiconductor material of the epitaxial source/drain region at a top surface of the semiconductor material of the epitaxial source/drain region”. The air gap 134A of Lee et al. exposes a bottom surface of the first dielectric layer 132A, a sidewall of the first spacer layer 124, a sidewall of the second spacer layer 144, and the semiconductor material of the source/drain region 114 at a top surface of the semiconductor material of the source/drain region 114, as shown in Fig. 4 of Lee et al. Lee et al. only lack a teaching that the source/drain regions 114 are epitaxial source/drain regions. However, it is well known in the art to form epitaxial source/drain regions in a FinFET in order to increase S/D volume and provide a larger surface for forming the necessary conductive contacts on the source/drain regions. Therefore, Applicant’s claimed device is unpatentable over Lee et al., US 2019/0043959, in view of Cheng et al., US 2019/0334011, as applied above in the rejection of claims 11, 12, 14, and 15. With respect to claim 16, independent claim 16 has been amended to require “a region of a second dielectric material extending over the first air gap from the first dielectric layer to the contact structure, wherein the second dielectric material is different from the first dielectric material”. Cheng et al. teach a region of a second dielectric material 1022 (see Figs. 1 and 9) extending over the first air gap 200 from the first dielectric layer 190 to the contact structure 701, as shown in Fig. 9, wherein the second dielectric material 1022 (Paragraph [0030]: “The dielectric material spacers 1022 can include or be formed of silicon boron carbon nitride (SiBCN).”) is different from the first dielectric material (SiO2, see paragraph [0045]). Therefore, amended claim 16 fails to patentably distinguish Applicant’s claimed device from the prior art device of Cheng. shown in Fig. 9. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARY A WILCZEWSKI whose telephone number is (571)272-1849. The examiner can normally be reached M-TH 7:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. MARY A. WILCZEWSKI Primary Examiner Art Unit 2898 /MARY A WILCZEWSKI/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Aug 01, 2023
Application Filed
Nov 13, 2025
Non-Final Rejection mailed — §102, §103, §112
Feb 11, 2026
Response Filed
May 14, 2026
Final Rejection mailed — §102, §103, §112
Jul 14, 2026
Response after Non-Final Action
Aug 07, 2026
Request for Continued Examination
Aug 11, 2026
Response after Non-Final Action
Sep 08, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
95%
With Interview (+10.2%)
2y 7m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 839 resolved cases by this examiner. Grant probability derived from career allowance rate.

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