Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 18-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 18 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pan et al. [US PGPUB 20220093471] (hereinafter Pan).
Regarding claim 18, Pan teaches a semiconductor device, comprising:
a substrate (101, Para 21);
a dielectric wall (structure 704/902/904 of feature 906, Para 39, Fig. 9/20) on the substrate (Fig. 20);
a plurality of first semiconductor channels (106, Para 26) on a first side of the dielectric wall (left side, Fig. 20);
a plurality of second semiconductor channels (106, Para 26) on a second side of the dielectric wall (right side, Fig. 20);
a dielectric liner (702, Para 39) spacing the first semiconductor channels from the first side of the dielectric wall and spacing the second semiconductor channels from the second side of the dielectric wall (Fig. 20), wherein a top end of the dielectric liner is substantially level with a topmost one of the first semiconductor channels (Fig. 20), and the top end of the dielectric liner is lower than a top surface of the dielectric wall (Fig. 20);
a first gate structure (1906, Para 42) wrapping around the first semiconductor channels (Fig. 20); and
a second gate structure (1906, Para 42) wrapping around second semiconductor channels (Fig. 20).
Allowable Subject Matter
Claims 1-17 are allowed.
Claims 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 1-9 are allowed because all prior arts on record on record either singularly or in combination fail to anticipate or render obvious a method of manufacturing a semiconductor device, comprising:
depositing a dielectric liner over the first and second fin;
forming a dielectric wall between the first and second fins and over the dielectric liner;
recessing a top surface of the dielectric structure and a top end of the dielectric liner;
depositing a protection layer over the first and second fins, wherein the protection layer covers the recessed top end of the dielectric liner;
(as claimed in claim 1), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Claims 10-17 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a semiconductor device, comprising: a method for manufacturing a semiconductor device, comprising:
recessing a top surface of the dielectric structure and a top end of the dielectric liner;
depositing a protection layer over the first fin, wherein the protection layer covers the recessed top end of the dielectric liner; and
after depositing the protection layer, etching back the dielectric structure (as claimed in claim 10), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ISMAIL A MUSE/Primary Examiner, Art Unit 2812