DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 15 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2019/0115300, of record) in view of Kuo et al. (CN 114759017, of record).
Regarding claim 1, Yu et al. discloses, as shown in Figures 9-10, a semiconductor package structure comprising:
a first redistribution structure (114), having a first side and a second side opposite to the first side;
a SoC structure (104A, [0013]) on the first side of the first redistribution structure;
a memory structure (104B, HBM, [0013]) adjacent to the SoC structure and on the first side of the first redistribution structure;
a first electronic component (118) on the second side of the first redistribution structure and electrically connected to at least one of the SoC structure or the memory structure; and
a first encapsulation layer (130) encapsulating the first electronic component, wherein the first electronic component comprises a semiconductor capacitor structure and some active devices [0025].
Yu et al. does not disclose the first electronic component comprises a semiconductor capacitor die and a power management die vertically stacked with the semiconductor capacitor die, and wherein a plurality of first through silicon vias (TSVs) are positioned at least in one of the power management die or the semiconductor capacitor die. However, Kuo et al. discloses a semiconductor package structure having the first electronic component comprises a semiconductor capacitor die (610,620) and a power management die (306) vertically stacked with the semiconductor capacitor die, and wherein a plurality of first TSVs (308) are positioned at least in one of the power management die or the semiconductor capacitor die. Note Figure 6 of Kuo et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the first electronic component of Yu et al. comprising a semiconductor capacitor die and a power management die vertically stacked with the semiconductor capacitor die, and wherein a plurality of first TSVs are positioned at least in one of the power management die or the semiconductor capacitor die, such as taught by Kuo et al. in order to further reduce the length of the interconnection and to improve the speed of the device.
Regarding claim 15, Yu et al. discloses, as shown in Figures 9-10, a semiconductor package structure comprising:
a first redistribution structure (114), having a first side and a second side opposite to the first side;
a SoC structure (104A, [0013]) on the first side of the first redistribution structure;
a memory structure (104B, HBM, [0013]) adjacent to the SoC structure and on the first side of the first redistribution structure; and
a first electronic component (118) on the second side of the first redistribution structure and electrically connected to the memory structure,
wherein the first electronic component comprises an active device [0025].
Yu et al. does not disclose the first electronic component also comprises a semiconductor capacitor die vertically stacked with the active device, wherein the active device is a power management die, and wherein a plurality of first through silicon vias (TSVs) are positioned at least in one of the power management die or the semiconductor capacitor die. However, Kuo et al. discloses a semiconductor package structure having the first electronic component comprises an active device and a semiconductor capacitor die vertically stacked with the active device wherein the active device is a power management die, and wherein a plurality of first TSVs are positioned at least in one of the power management die or the semiconductor capacitor die. Note Figure 6 of Kuo et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the first electronic component of Yu et al. comprising an active device and a semiconductor capacitor die vertically stacked with the active device wherein the active device is a power management die, and wherein a plurality of first TSVs are positioned at least in one of the power management die or the semiconductor capacitor die, such as taught by Kuo et al. in order to further reduce the length of the interconnection and to improve the speed of the device.
Regarding claim 19, Yu et al. and Kuo et al. disclose further comprising a second redistribution structure (302) supporting the first electronic component and electrically connected to the first redistribution structure (324) by the through silicon via (TSV, 308,314). Note Figures 3 and 6 of Kuo et al.
Regarding claim 23, Yu et al. and Kuo et al. disclose (1) the semiconductor capacitor die comprises the plurality of TSVs penetrating the semiconductor capacitor die from one side of the semiconductor capacitor die to a metallization structure of the semiconductor capacitor die, or (2) the power management die comprises the plurality of TSVs penetrating the power management die from one side of the power management die to a metallization structure of the power management die. Figure 6 of Kuo et al.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2019/0115300, of record) in view of Kuo et al. (CN 114759017, of record) and further in view of Hsu et al. (US 2020/0395338, of record).
Regarding claim 24, Yu et al. and Kuo et al. do not disclose a sidewall of the power management die and a sidewall of the semiconductor capacitor die in the firs electronic component are almost vertically aligned, but not exactly aligned. However, Hsu et al. discloses a device having a sidewall of two dies are vertically aligned. Note Figures 1D, 1G, 3C-3D and [0028] of Hsu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the connection of Yu et al. and Kuo et al. having sidewall vertically aligned, such as taught by Hsu et al. in order to have the desired configuration.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2019/0115300, of record) in view of Kuo et al. (CN 114759017, of record) and further in view of Hsu et al. (US 2020/0395338).
Regarding claim 17, Yu et al. and Kuo et al. disclose the claimed invention including the semiconductor package structure as explained in the above rejection. Yu et al. and Kuo et al. do not disclose the connection through a hybrid bonding layer. However, Hsu et al. discloses a connection (between dies 100 and 200) through a hybrid bonding layer. Note Figures 1D, 1G, 3C-3D and [0028] of Hsu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the connection of Yu et al. and Kuo et al. through a hybrid bonding layer, such as taught by Hsu et al. in order to shorten the interconnection length and improve the performance of the device.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2019/0115300, of record) in view of Kuo et al. (CN 114759017, of record) and further in view of Lin et al. (US 2016/0343695).
Yu et al. and Kuo et al. disclose the claimed invention including the semiconductor package structure as explained in the above rejection. Yu et al. and Kuo et al. further disclose a second redistribution structure coupled to the first electronic component, wherein the second redistribution structure is disposed on a side of the first electronic component facing away from the first redistribution structure. Yu et al. and Kuo et al. do not disclose a second electronic component on the second side of the first redistribution layer and the second redistribution structure electrically also coupled to the second electronic component. However, Lin et al. discloses a second electronic component (110B) on the second side of the first redistribution layer, and a second redistribution structure (200) electrically coupled to the first electronic component and the second electronic component, wherein the second redistribution structure is disposed on a side of the first electronic component facing away from the first redistribution structure. Note Figures 3E-5 of Lin et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to integrate the structure of Yu et al. and Kuo et al. comprising a second electronic component on the second side of the first redistribution layer, and a second redistribution structure electrically coupled to the first electronic component and the second electronic component, such as taught by Lin et al. in order to perform the desired function.
Regarding claim 25, Yu et al., Kuo et al., and Lin et al. disclose the plurality of TSVs (126) in the semiconductor capacitor die (118) are in contact with the second redistribution structure. (Figures of Yu et al.)
Regarding claim 27, Yu et al., Kuo et al., and Lin et al. disclose the plurality of TSVs in the power management die penetrate the power management die from one side in proximity to the second redistribution structure to the metallization structure of the power management die.
Regarding claim 28, Yu et al., Kuo et al., and Lin et al. disclose the structure further comprising a fourth electronic component (620) on the second side of the first redistribution structure, wherein the bottom surface of the fourth electronic component is level with the first electronic component (in the upside down position, 610 and 620 are level), and wherein the fourth electronic component is free from having a TSV. Figure 6 of Kuo et al.
Regarding claim 29, Yu et al., Kuo et al., and Lin et al. disclose a portion of the first electronic component and a portion of the fourth electronic component are at least under a projective coverage of the SoC structure and the memory structure (combination of Figures).
Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US 2019/0115300, of record) in view of Kuo et al. (CN 114759017, of record), Lin et al. (US 2016/0343695) and further in view of Hsu et al. (US 2020/0395338).
Regarding claim 17, Yu et al., Kuo et al., and Lin et al. disclose the claimed invention including the semiconductor package structure as explained in the above rejection. Yu et al., Kuo et al., and Lin et al.do not disclose the connection through a hybrid bonding layer. However, Hsu et al. discloses a connection (between dies 100 and 200) through a hybrid bonding layer. Note Figures 1D, 1G, 3C-3D and [0028] of Hsu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the connection of Yu et al., Kuo et al., and Lin et al. through a hybrid bonding layer, such as taught by Hsu et al. in order to shorten the interconnection length and improve the performance of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HUNG K VU whose telephone number is (571)272-1666. The examiner can normally be reached Monday - Friday: 7am - 5pm.
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/HUNG K VU/ Primary Examiner, Art Unit 2897
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