DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention of Embodiment 7 of Figure 13, Claims 1, 3-5, 7, 9 and 15-22 in the reply filed on 12/16/2025 is acknowledged.
Claims 2, 6, 8, 10-12, and claim 20, however, does not belong the elected Embodiment 7 of Figure 13, are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/16/2025.
Information Disclosure Statement
The information disclosure statement filed 04/02/2024, 01/17/2025, 01/17/2025, and 02/27/2025 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 7 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. (US 2019/0115300).
Regarding claim 1, Yu et al. discloses, as shown in Figures 9-10, a semiconductor package structure comprising:
a first redistribution structure (114), having a first side and a second side opposite to the first side;
a SoC structure (104A, [0013]) on the first side of the first redistribution structure;
a memory structure (104B, HBM, [0013]) adjacent to the SoC structure and on the first side of the first redistribution structure;
a first electronic component (118) on the second side of the first redistribution structure and electrically connected to at least one of the SoC structure or the memory structure; and
a first encapsulation layer (130) encapsulating the first electronic component, wherein the first electronic component comprises a semiconductor capacitor structure or a voltage converter [0025].
Regarding claim 15, Yu et al. discloses, as shown in Figures 9-10, a semiconductor package structure comprising:
a first redistribution structure (114), having a first side and a second side opposite to the first side;
a SoC structure (104A, [0013]) on the first side of the first redistribution structure;
a memory structure (104B, HBM, [0013]) adjacent to the SoC structure and on the first side of the first redistribution structure; and
a first electronic component (118) on the second side of the first redistribution structure and electrically connected to the memory structure,
wherein the first electronic component comprises an active device [0025].
Claim(s) 1, 3, 7 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2016/0343695).
Regarding claim 1, Lin et al. discloses, as shown in Figures 3E-5, a semiconductor package structure comprising:
a first redistribution structure (130B), having a first side and a second side opposite to the first side;
a SoC structure (110A, [0058]) on the first side of the first redistribution structure;
a memory structure (110A) adjacent to the SoC structure and on the first side of the first redistribution structure ([0025], Figures 4-5);
a first electronic component (110B) on the second side of the first redistribution structure and electrically connected to at least one of the SoC structure or the memory structure; and
a first encapsulation layer (120B) encapsulating the first electronic component, wherein the first electronic component comprises a semiconductor capacitor structure or a voltage converter [0037].
Regarding claim 3, Lin et al. discloses the structure further comprising:
a second electronic component (110B) on the second side of the first redistribution layer; and
a second redistribution structure (200) electrically coupled to the first electronic component and the second electronic component, wherein the second redistribution structure is disposed on a side of the first electronic component facing away from the first redistribution structure.
Regarding claim 7, Lin et al. discloses a thickness of the first electronic component and a thickness of the second electronic component are substantially identical ([0040], Figures 2B, 3E, 4).
Regarding claim 15, Lin et al. discloses, as shown in Figures 3E-5, a semiconductor package structure comprising:
a first redistribution structure (130B), having a first side and a second side opposite to the first side;
a SoC structure (110A, [0058]) on the first side of the first redistribution structure;
a memory structure (110A) adjacent to the SoC structure and on the first side of the first redistribution structure ([0025], Figures 4-5); and
a first electronic component (100B) on the second side of the first redistribution structure and electrically connected to the memory structure,
wherein the first electronic component comprises an active device [0037].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2016/0343695) in view of Yu et al. (US 2018/0226349).
Regarding claim 4, Lin et al. discloses the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al. does not disclose at least one of the first electronic component or the second electronic component comprises a plurality of through silicon vias (TSVs) electrically connecting the first redistribution structure and the second redistribution structure. However, Yu et al. discloses a semiconductor package structure comprising at least one of the first electronic component or the second electronic component (118) comprises a plurality of through silicon vias (TSVs) (126) electrically connecting a first redistribution structure (114) and a second redistribution structure (132). Note Figures 9-10 of Yu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form at least one of the first electronic component or the second electronic component of Lin et al. having a plurality of through silicon vias (TSVs) electrically connecting the first redistribution structure and the second redistribution structure, such as taught by Yu et al. in order to further reduce the length of the interconnection and improve the speed.
Regarding claim 5, Lin et al. and Yu et al. discloses the first encapsulation layer (130) comprises molding underfill (MUF) (Figures 9-10).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2016/0343695, hereafter Lin et al.’695) in view of Lin et al. (US 2016/0260693, hereafter Lin et al.’693).
Lin et al.’695 discloses the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al.’695 does not disclose the SoC structure is vertically stacked to the memory structure. However, Lin et al.’693 discloses a SoC structure (500b) is vertically stacked to a memory structure. Note Figure 2 and [0035] of Lin et al.’693. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the SoC structure of Lin et al.’695 being stacked to the memory structure, such as taught by Ln et al.’693 in order to further reduce the overall footprint.
Claim(s) 16 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2016/0343695) in view of Azrai et al. (US 2005/0213280).
Regarding claim 16, Lin et al. discloses the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al. does not disclose the first electronic component comprises a power management unit and a semiconductor capacitor structure integrated with the power management unit. However, Azrai et al. discloses the first electronic component comprises a power management unit (76) and a semiconductor capacitor structure (Cf, 306,464) integrated with the power management unit. Note Figures 2, 7-8, 35-46, and [0155] –[0159] of Azai et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form at least one of the first electronic component of Lin et al. comprising a power management unit and a semiconductor capacitor structure integrated with the power management unit, such as taught by Azrai et al. in order to perform the desired function.
Regarding claim 21, Lin et al. discloses the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al. does not disclose the voltage converter comprises an active device. However, Azrai et al. discloses the first electronic component being a voltage converter comprises an active device (transistor P1-P5). Note Figures 2, 7-8, 35-46, and [0155] –[0159] of Azai et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the voltage converter of Lin et al. comprising an active device, such as taught by Azrai et al. in order to perform the desired function.
Regarding claim 22, Lin et al. discloses the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al. does not disclose the voltage converter comprises a power management unit and a second semiconductor capacitor structure. However, Azrai et al. discloses the first electronic component being a voltage converter comprises a power management unit (76) and a second semiconductor capacitor structure (Cf, 306,464). Note Figures 2, 7-8, 35-46, and [0155] –[0159] of Azai et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the voltage converter of Lin et al. comprising a power management unit and a second semiconductor capacitor structure, such as taught by Azrai et al. in order to perform the desired function.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2016/0343695) in view of Azrai et al. (US 2005/0213280) and further in view of Hsu et al. (US 2020/0395338).
Lin et al. discloses the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al. does not disclose the first electronic component comprises a power management die and a silicon capacitor die electrically connected to the power management die. However, Azrai et al. discloses the first electronic component comprises a power management unit (76) and a second semiconductor capacitor structure (Cf, 306,464) electrically connected to the power management die. Note Figures 2, 7-8, 35-46, and [0155] –[0159] of Azai et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the first electronic component of Lin et al. comprising a power management die and a silicon capacitor die electrically connected to the power management die, such as taught by Azrai et al. in order to perform the desired function.
Lin et al. and Azrai et al. do not disclose the connection through a hybrid bonding layer. However, Hsu et al. discloses a connection through a hybrid bonding layer. Note Figures 1D, 1G, 3C-3D and [0028] of Hsu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form the connection of Lin et al. and Azrai et al. through a hybrid bonding layer, such as taught by Hsu et al. in order to shorten the interconnection length and improve the performance of the device.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 2016/0343695) in view of Azrai et al. (US 2005/0213280) and further in view of Yu et al. (US 2018/0226349).
Regarding claim 18, Lin et al. and Azrai et al. disclose the claimed invention including the semiconductor package structure as explained in the above rejection. Lin et al. and Azrai et al. do not disclose at least one of the first electronic component or the second electronic component comprises a plurality of through silicon vias (TSVs) electrically connecting the first redistribution structure and the second redistribution structure. However, Yu et al. discloses a semiconductor package structure comprising at least one of the first electronic component or the second electronic component (118) comprises a plurality of through silicon vias (TSVs) (126) electrically connecting a first redistribution structure (114) and a second redistribution structure (132). Note Figures 9-10 of Yu et al. Therefore, it would have been obvious to one of ordinary skills in the art at the time the invention was made to form at least one of the first electronic component or the second electronic component of Lin et al. and Azrai et al. having a plurality of through silicon vias (TSVs) electrically connecting the first redistribution structure and the second redistribution structure, such as taught by Yu et al. in order to further reduce the length of the interconnection and improve the speed.
Regarding claim 19, Lin et al., Azrai et al. and Yu et al. disclose further comprising a second redistribution structure (132) supporting the first electronic component and electrically connected to the first redistribution structure (114) by the through silicon via (TSV, 126). Note Figures 9-10 of Yu et al.
Conclusion
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/HUNG K VU/ Primary Examiner, Art Unit 2897