DETAILED ACTION
This Office Action is in response to the Election and Amendment filed on May 5, 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species A, claims 1-7 and new claims 21 and 22 in the reply filed on May 5, 2026 is acknowledged. The traversal is on the ground(s) that the amendments to independent claims now include some of the features of claim and therefore are no longer obvious variants of each other. This is not found persuasive because despite the amendments, claims 8 and 15 still recite different features not disclosed in species A. For instance, species B disclose forming connection structures passing through the periphery of the of the active array and the bit line array, wherein the connection structures are sandwiched in between the memory cells and the dummy memory cells. Species C discloses the method comprising a plurality of bit line vias located on the first bit line conductive layer and on the third bit line conductive layer are overlapped with one another along the second direction and non-overlapped with the plurality of bit line vias located on the second bit line conductive layer. These elements are distinct features not found in species A. The requirement is still deemed proper and is therefore made FINAL.
Claims 3 and 8-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7 and 22 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lai et al. (US Pub. 2021/0343730 A1).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
In re claim 1, Lai et al. discloses (3A-1 - 3R-3) a method, comprising: providing a substrate; forming a CMOS (complementary metal-oxide semiconductor) circuitry [0020] over the substrate; forming a first dielectric film (326) over the substrate on the CMOS circuitry, and patterning the first dielectric film using a first mask [0056]; forming bit line conductive layers (328M) in first openings defined by the first mask; forming a second dielectric film (326M) over the first dielectric film, and patterning the second dielectric film using a second mask [0056]; forming bit line vias (332) in second openings defined by the second mask , wherein the bit line vias have a staggered arrangement [0086] forming a memory array on the second dielectric film and electrically connected to the bit line vias; forming a third dielectric film (375) on the memory array, and patterning the third dielectric film using a third mask (384); and forming source line vias [0107] in third openings defined by the third mask, wherein the source line vias have a staggered arrangement [0086] and are electrically connected to the memory array.
In re claim 2, Lai et al. discloses (3R-1) forming a fourth dielectric film (375) over the third dielectric film, and patterning the fourth dielectric film using a fourth mask (391); an forming source line conducive layers (372) in fourth openings defined by the fourth mask.
In re claim 4, Lai et al. discloses ([0086]) wherein the bit line vias are non- overlapped with the source line vias.
In re claim 5, Lai et al. discloses (3A-1 - 3R-3) wherein forming the memory array comprises: forming a word line stack (fig. 3C; 334) on the second dielectric film, wherein the word line stack has a first side surface and a second side surface opposite to the first side surface; and forming source/drain regions on the first side surface and the second side surface, wherein the source/drain regions on the first side surface are staggered from the source/drain regions on the second side surface [0086].
In re claim 6, Lai et al. discloses (figs. 3E-1, 3E-2) forming channel material layers (346) on the first side surface and the second side surface prior to forming the source/drain regions; forming dielectric materials (figs. 3F-1, 3F-3) on the channel material layers, and patterning the dielectric materials to form dielectric pillars (fig. 3J-3; 348); and wherein the source/drain regions are formed on two sides of the dielectric pillars.
In re claim 7, Lai et al. discloses (3A-1 - 3R-3) forming the CMOS circuitry
further comprises: forming an interconnect structure (fig. 3A-1; 328)) on the substrate prior to forming the first dielectric film, wherein the bit line conductive layers, the bit line vias and the source line vias are electrically connected to the interconnect structure.
In re claim 22, Lai et al. discloses (3A-1 - 3R-3), wherein forming the memory array further comprises forming a plurality of conductive pillars having a staggered arrangement and a plurality of isolation pillars having a staggered arrangement [0086].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Fukuo (US 10,734,400 B1), Shimizu (US 9,876,031 B1), Parekh (US Pub. 2021/0398897 A1), and Zhu (CN-109314116-B) also disclose various elements of the claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm.
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/MATTHEW E WARREN/Primary Examiner, Art Unit 2817
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