Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of the Claims
Applicant’s election of Group I, claims 1-10 in the reply filed on August 02nd, 2025 is acknowledged. The traversal is on the ground(s) that “the search and examination of Groups I-III are inseparable and cannot impose a serious burden on the examiner”. This is not found persuasive. The restriction for examination purposes as indicated in the restriction /election requirement, mailed on 09/23/2025, is proper because all these inventions listed in this action are independent or distinct for the reasons given and there would be a serious search and examination burden if restriction were not required because one or more of the following reasons apply:
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
Accordingly, the requirement is still deemed proper and is therefore made FINAL. Non-elected invention of Groups II-III, claims 11-20, have been withdrawn from consideration. Claims 1-20 are pending.
Action on merits of Group I, claims 1-10 as follows.
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on August 02nd, 2023 and March 28th, 2024 have been considered by the examiner.
Drawings
The drawings filed on 08/02/2023 are acceptable.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kao (US 2019/0285953, hereinafter as Kao ‘953) in view of Li (CN 107219660, hereinafter as Li ‘660).
Regarding Claim 1, Kao ‘953 teaches a display device (Fig. 2, (100); [0024]), comprising:
a display area (AR; [0024]) comprising:
a plurality of pixels (OLEDs; [0024] and [0030]); and
a data line (DL; [0024]) and a gate line (SL; [0024]) that are electrically connected to the plurality of pixels;
a non-display area (PR; [0024]) disposed adjacent to the display area (AR);
a plurality of pads (PA; [0025]) disposed on a side of the non-display area (PR);
a gate control line that is electrically connected to at least one of the plurality of pads and that supplies a gate control signal (see Fig. 2);
a driving voltage line (BA; [0026]) that is electrically connected to at least one of the plurality of pads and that supplies a driving voltage (e.g. common voltage; [0026]);
an antistatic circuit (120; [0025]);
a scan driver (IGD; [0024]) that generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line (see para. [0026]); and
a shielding layer (130; [0025]) integral to the driving voltage line to overlap the top of the antistatic circuit (see Fig. 3B).
Thus, Kao ‘953 is shown to teach all the features of the claim with the exception of explicitly the limitations: “an antistatic circuit electrically connected to the gate control line”.
Li ‘660 teaches an antistatic circuit (Fig. 3, (70); [0063]) electrically connected to the gate control line (Figs. 2 and 3, (211); [0063]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kao ‘953 by having an antistatic circuit electrically connected to the gate control line for the purpose of protecting the signal connection line from damage by static charge (see para. [0063]) as suggested by Li ‘660.
Examiner notes that Claim 1 contains functional limitation “generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line” (emphasis added). According to MPEP 2173(05) g. " the use of functional language in a claim may fail “to provide a clear-cut indication of the scope of the subject matter embraced by the claim” and thus be indefinite. In re Swinehart, 439 F.2d 210, 213 (CCPA 1971). For example, when claims merely recite a description of a problem to be solved or a function or result achieved by the invention, the boundaries of the claim scope may be unclear. Halliburton Energy Servs., Inc. v. M-I LLC, 514 F.3d 1244, 1255 (Fed. Cir. 2008)”. In the instant case, “generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line” is nothing else than the result achieved by the invention.
The applicant’s claim 1 does not distinguish over Kao ‘953 reference regardless of the functions allegedly performed by the claimed device, because only the device per se is relevant, not the recited function of the scan driver in order to generate a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line. In reference to the claim language referring to the function of the scan driver, intended use and other types of functional language (such as generates a gate signal based on a gate control signal received from the gate control line and that supplies the gate signal to the gate line) must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
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Fig. 3B (Kao ‘953)
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Fig. 3 (Li ‘660)
Regarding Claim 2, Kao ‘953 teaches the antistatic circuit (120) comprises a transistor (T1/T2; [0025]) comprising an oxide-based semiconductor region (e.g. metal oxide (SM), see Fig. 4, para. [0025]).
Regarding Claim 3, Kao ‘953 teaches the shielding layer (130) includes a plurality of holes (Fig. 5, (SP2); [0030]) that do not overlap a semiconductor region of the transistor.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Kao ‘953 and Li ‘660 as applied to claim 1 above, and further on view of Park (KR 2016/0070257, hereinafter as Park ‘257).
Regarding Claim 4, Kao ‘953 and Li ‘660 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a low potential line that is electrically connected to at least one of the plurality of pads and that supplies a low potential voltage, wherein the shielding layer is integral to the low potential line to overlap the top of the antistatic circuit”.
Park ‘257 teaches a low potential line (Fig. 5, (GND); [0043]) that is electrically connected to at least one of the plurality of pads (GNP; see Fig. 5) and that supplies a low potential voltage, wherein the shielding layer (SHD; [0047]) is integral to the low potential line (GND; see para. [0050]) to overlap the top of the antistatic circuit (ESD; [0053]-[0054]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kao ‘953 and Li ‘660 by having a low potential line that is electrically connected to at least one of the plurality of pads and that supplies a low potential voltage, wherein the shielding layer is integral to the low potential line to overlap the top of the antistatic circuit for the purpose of preventing the square element from being damaged by a relatively large amount of static electricity generated during the deposition process of organic materials or a metal frame aligned in close proximity to the substrate during the manufacturing process (see para. [0053]) as suggested by Park ‘257.
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Fig. 5 (Park ‘257)
Regarding Claim 5, Park ‘257 teaches a gate high voltage line that is electrically connected to at least one of the plurality of pads and that supplies a gate high voltage (see Fig. 5, (VDD)); a first gate low voltage line (GND) that is electrically connected to at least one of the plurality of pads and that supplies a first gate low voltage; a second gate low voltage line that is electrically connected to at least one of the plurality of pads (see Fig. 3).
Kao ‘953, Li ‘660 and Park ‘257 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a second gate low voltage lower than the first gate low voltage”.
However, it has been held to be within the general skill of a worker in the art to select a second gate low voltage lower than the first gate low voltage on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. A person of ordinary skills in the art is motivated to select a second gate low voltage lower than the first gate low voltage in order to improve the performance of the display device.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kao ‘953, Li ‘660 and Park ‘257 as applied to claim 5 above, and further on view of Arai (US 2007/0201175, hereinafter as Arai ‘175).
Regarding Claim 6, Li ‘660 teaches a first transistor (T1) electrically connected between the gate high voltage line (VGH) and the gate control line (211); a second transistor electrically connected between the gate control line (211) and the first gate low voltage line (VGL) (see Fig. 5).
Kao ‘953, Li ‘660 and Park ‘257 are shown to teach all the features of the claim with the exception of explicitly the limitations: “a first resistance line electrically connected between a gate electrode of the first transistor and the gate control line; and a second resistance line electrically connected between a gate electrode of the second transistor and the first gate low voltage line”.
Arai ‘175 teaches a first resistance line (Fig. 1, (17); [0059]) electrically connected between a gate electrode of the first transistor (10; [0059]) and the gate control line (1; [0052]); and a second resistance line (18; [0058]) electrically connected between a gate electrode of the second transistor (11; [0058]) and the first gate low voltage line (2; [0052]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kao ‘953, Li ‘660 and Park ‘257 by having a first resistance line electrically connected between a gate electrode of the first transistor and the gate control line; and a second resistance line electrically connected between a gate electrode of the second transistor and the first gate low voltage line in order to obtain the surge test standard satisfied even though the semiconductor fabrication process (design rules) is further scaled down (see para. [0043]) as suggested by Arai ‘175.
Regarding Claim 7, Kao ‘953 teaches a first bias electrode (G1) electrically connected to the second gate low voltage line to overlap the semiconductor region (SM) of the first transistor (see Fig. 4), and the second transistor comprises a second bias electrode electrically connected to the second gate low voltage line to overlap the semiconductor region of the second transistor (see Figs. 3A and 4; [0025]).
Regarding Claim 8, Park ‘257 teaches the shielding layer (SHD) overlaps a portion of each of the gate high voltage line (VDD), and the first and second gate low voltage lines (GNDh), and the plurality of holes of the shielding layer (SHD) overlap another portion of each of the gate high voltage line, and the first and second gate low voltage lines (see Figs. 5 and 6).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kao ‘953 and Li ‘660 as applied to claim 1 above, and further on view of Kim (US 2020/0393937, hereinafter as Kim ‘937).
Regarding Claim 9, Kao ‘953 teaches a DC electrode (DL) that is electrically connected to at least one of the plurality of pads (PA) and that supplies a DC voltage (see Fig. 2).
Thus, Kao ‘953 and Li ‘660are shown to teach all the features of the claim with the exception of explicitly the limitations: “a test signal line that is electrically connected to at least one of the plurality of pads and that supplies a test gate signal; and a test transistor that supplies the DC voltage based on the test gate signal to the data lines, wherein the DC electrode overlaps the semiconductor region of the test transistor”.
Kim ‘937 teaches a test signal line (Fig. 6, (368); [0093]) that is electrically connected to at least one of the plurality of pads (PADA; [0054]) and that supplies a test gate signal; and a test transistor (TT; [0091]) that supplies the DC voltage based on the test gate signal to the data lines (DL; [0093]), wherein the DC electrode overlaps the semiconductor region (320; [0092]) of the test transistor (see Fig. 7).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify Kao ‘953 and Li ‘660 by having a test signal line that is electrically connected to at least one of the plurality of pads and that supplies a test gate signal; and a test transistor that supplies the DC voltage based on the test gate signal to the data lines, wherein the DC electrode overlaps the semiconductor region of the test transistor for the purpose of checking whether the pixels in the display area DA are defective (see para. [0093]) as suggested by Kim ‘937.
Regarding Claim 10, Kim ‘937 teaches the test transistor comprises: a drain electrode (362; [0094]) overlapping the DC electrode (DL; [0094]) and electrically connected to the DC electrode (DL); a gate electrode (341; [0094]) receiving a test gate signal and overlapping a semiconductor region (320) of the test transistor; and a source electrode (361; [0092]) electrically connected to the data line (see Fig. 6; [0093]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following patents are cited to further show the state of the art with respect to semiconductor devices:
Kim et al. (US 2021/0083037 A1)
Lee et al. (US 2022/0037299 A1)
Yamazaki (US 2014/0175436 A1)
For applicant’s benefit portions of the cited reference(s) have been cited to aid in the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DZUNG T TRAN whose telephone number is (571) 270-3911. The examiner can normally be reached on M-F 8 AM-5PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DZUNG TRAN/
Primary Examiner, Art Unit 2893