Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/20/2023, 7/28/2025 and 11/03/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7, 10-16 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Hamamura et al. US 2013/0234163 in view of Yamamoto US 2002/0153579 and Kim US 2020/0020780.
Re claim 1, Hamamura teaches an electronic device (fig6) comprising:
a semiconductor body of Silicon Carbide (1 and 2, fig6, [35]), having a first (top surface of 1-2 facing gate 7, fig6, [35]) and a second face (bottom surface of 1-2 facing drain 10, fig6, [35]), opposite to each other along a first direction;
an electrical terminal (7 and 6, fig6, [35, 36]) at the first face, including a conductive layer (7, fig6, [35]) and an electrical insulation region (6, fig6, [36]), the electrical insulation region extending between the semiconductor body (1,2, fig6, [35]) and the conductive layer (7, fig6, [35]),
wherein said electrical insulation region is a multilayer comprising:
a first insulating layer in contact with the semiconductor body, having a first bandgap value and a first thickness, (6a as SiO2 ~3nm ~8eV, fig6, [36]) configured to be traversed by the tunnel effect, during use, by electric charge carriers coming from the semiconductor body;
a second insulating layer on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness (6d as SiN 0.5* (0.9* (thickness of 6) band gap ~5ev, fig6, [40]), configured to form a potential well for said electric charge carriers; and
a third insulating layer (6b as HfO2 6eV ~10% thickness of 6, fig6, [36, 44]) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values.
Hamamura does not explicitly show a third insulating layer on the second insulating layer, having a third thickness greater than the second thickness.
Yamamoto teaches a thin interfacial SiO2 layer (17 ~0.5-1nm, fig5B, [86, 94]) with an Al2O3/HfO2/ Al2O3 stack (3 as Al2O3 ~0.2-2nm, 4 as HfO2 ~1-5nm, fig5B, [74, 75, 85]).
Kim teaches HK laminate structure of HAHAH ([48]) with thin interfacial SiO2 of about 0.1-0.2 nm (208, fig2D, [69]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Hamamura, Yamamoto and Kim to form an HAHAH stack between two thin interfacial SiO2 layer. The motivation to do so is to reduce leakage current (Kim, [47]; Yamamoto, [62]).
The outcome of the combination teaches a first insulating layer in contact with the semiconductor body, having a first bandgap value and a first thickness, (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6);
a second insulating layer on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness (6d as HfO2 ~1-5nm ~6ev, fig6); and
a third insulating layer (6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values and a third thickness greater than the second thickness.
Regarding the language of “a first insulating layer … configured to be traversed by the tunnel effect, during use, by electric charge carriers coming from the semiconductor body; a second insulating layer … configured to form a potential well for said electric charge carriers;” the Examiner notes this language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). As best can be determined by the Examiner from the specification of the present application, the structure which performs the function is simply the existence of laminated gate dielectric structure, a structure which is clearly present in the device of Hamamura as modified by Yamamoto and Kim. Therefore, it appears the structure of a gate dielectric stack as modified by Yamamoto and Kim is capable of performing the function required by the claim language.
Re claim 2, Hamamura modified above teaches the electronic device according to claim 1, wherein: the first insulating layer has a thickness comprised between 0.5 nm and 1 nm (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6); the second insulating layer has a thickness comprised between 1.5 nm and 2.5 nm (Hamamura, 6d as HfO2 ~1-5nm ~6ev, fig6); and the third insulating layer has a thickness comprised between 10 and 100 nm (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6).
Re claim 3, Hamamura modified above teaches the electronic device according to claim 1, wherein: the first insulating layer is of one from among: SiN, SiO2 (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6), AlN; the second insulating layer is of one from among: HfO2 (Hamamura, 6d as HfO2 ~1-5nm ~6ev, fig6), HfSiOx, ZrO2, ZrSiOx; and the third insulating layer includes two or more alternating layers of an Aluminum Oxide and a Hafnium Oxide (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6).
Re claim 4, Hamamura modified above teaches the electronic device according to claim 3, wherein the third insulating layer includes two or more alternating layers of Al2O3 and HfO2 (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6), or two or more alternating layers of AlSiOx and HfSiOx.
Re claim 5, Hamamura modified above teaches the electronic device according to claim 1, further comprising a channel region (Hamamura, surface of 2 between 6 and 10, fig6, [35]) in said semiconductor body (Hamamura, 1-2, fig6, [35]), configured to accommodate, in use, an electric current, said electrical insulation region extending at said channel region.
Re claim 6, Hamamura modified above teaches the electronic device according to claim 5, having positive charge carriers at said first face defining a positive interface charge, said electrical insulation region being designed in such a way as to have trap states of electrons, which generate a negative charge such as to balance, at least in part, said positive interface charge (Hamamura, fig6).
Re claim 7, Hamamura modified above teaches the electronic device according to claim 1, wherein said electronic device is a MOSFET comprising a source terminal (Hamamura, 9, fig6, [35]) and a drain terminal (Hamamura, 10, fig6, [35]), said electrical terminal being a gate terminal of the MOSFET (Hamamura, 7 and 6, fig6, [35, 36]), the conductive layer being a gate metallization (Hamamura, 7, fig6, [35]), and the electrical insulation region forming, as a whole, a gate dielectric (Hamamura, 6 as HAHAH between thin SiO2 layers, fig6, [36]).
Re claim 10, Hamamura teaches a method of manufacturing an electronic device (fig6) comprising:
providing a semiconductor body of Silicon Carbide (1 and 2, fig6, [35]), having a first (top surface of 1-2 facing gate 7, fig6, [35]) and a second face (bottom surface of 1-2 facing drain 10, fig6, [35]), opposite to each other along a first direction;
forming an electrical terminal (7 and 6, fig6, [35, 36]) at the first face, including forming a conductive layer (7, fig6, [35]) and an electrical insulation region (6, fig6, [36]) between the conductive layer and the semiconductor body, configured to electrically insulate the electrical terminal from the semiconductor body,
wherein the step of forming said electrical insulation region comprises forming a multilayer, including:
forming a first insulating layer (6a as SiO2 ~3nm ~8eV, fig6, [36]) in contact with the semiconductor body, having a first bandgap value and a first thickness,
forming a second insulating layer (6d as SiN 0.5* (0.9* (thickness of 6) band gap ~5ev, fig6, [40]) on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness; and
forming a third insulating layer (6b as HfO2 6eV ~10% thickness of 6, fig6, [36, 44]) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values.
Hamamura does not explicitly show a third insulating layer on the second insulating layer, having a third thickness greater than the second thickness.
Yamamoto teaches a thin interfacial SiO2 layer (17 ~0.5-1nm, fig5B, [86, 94]) with an Al2O3/HfO2/ Al2O3 stack (3 as Al2O3 ~0.2-2nm, 4 as HfO2 ~1-5nm, fig5B, [74, 75, 85]).
Kim teaches HK laminate structure of HAHAH ([48]) with thin interfacial SiO2 of about 0.1-0.2 nm (208, fig2D, [69]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Hamamura, Yamamoto and Kim to form an HAHAH stack between two thin interfacial SiO2 layer. The motivation to do so is to reduce leakage current (Kim, [47]; Yamamoto, [62]).
The outcome of the combination teaches a first insulating layer in contact with the semiconductor body, having a first bandgap value and a first thickness, (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6);
a second insulating layer on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness (6d as HfO2 ~1-5nm ~6ev, fig6); and
a third insulating layer (6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values and a third thickness greater than the second thickness.
Regarding the language of “a first insulating layer … configured to be traversed, by tunnel effect, during use, by electric charge carriers coming from the semiconductor body; a second insulating layer … configured to form a potential well for said electric charge carriers;” the Examiner notes this language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). As best can be determined by the Examiner from the specification of the present application, the structure which performs the function is simply the existence of laminated gate dielectric structure, a structure which is clearly present in the device of Hamamura as modified by Yamamoto and Kim. Therefore, it appears the structure of a gate dielectric stack as modified by Yamamoto and Kim is capable of performing the function required by the claim language.
Re claim 11, Hamamura modified above teaches the method according to claim 10, wherein: the first insulating layer has a thickness comprised between 0.5 nm and 1 nm (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6); the second insulating layer has a thickness comprised between 1.5 nm and 2.5 nm (Hamamura, 6d as HfO2 ~1-5nm ~6ev, fig6); and the third insulating layer has a thickness comprised between 10 and 100 nm (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6).
Re claim 12, Hamamura modified above teaches the method according to claim 10, wherein: the first insulating layer is of one from among: SiN, SiO2 (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6), AlN; the second insulating layer is of one from among: HfO2 (Hamamura, 6d as HfO2 ~1-5nm ~6ev, fig6), HfSiOx, ZrO2, ZrSiOx; and the third insulating layer includes two or more alternating layers of an Aluminum Oxide and a Hafnium Oxide (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6).
Re claim 13, Hamamura modified above teaches the method according to claim 12, wherein the third insulating layer includes two or more alternating layers of Al2O3 and HfO2 (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6), or two or more alternating layers of AlSiOx and HfSiOx.
Re claim 14, Hamamura modified above teaches the method according to claim 10, wherein forming the second and the third insulating layers comprises performing respective depositions by ALD technique (Yamamoto, [72, 75]).
Re claim 15, Hamamura modified above teaches the method according to claim 10, further comprising a channel region (Hamamura, surface of 2 between 6 and 10, fig6, [35]) in said semiconductor body (Hamamura, 1 and 2, fig6, [35]), configured to accommodate, in use, an electric current, said electrical insulation region (Hamamura, 6, fig6, [36]) being formed at said channel region.
Re claim 16, Hamamura modified above teaches the method according to claim 10, wherein said electronic device is a MOSFET (Hamamura, fig6), the manufacturing comprising forming a source terminal (Hamamura, 9, fig6, [35]) and a drain terminal (Hamamura, 10, fig6, [35]) of the MOSFET, said electrical terminal being a gate terminal of the MOSFET (Hamamura, 7 and 6, fig6, [35, 36]), the conductive layer being a gate metallization (Hamamura, 7, fig6, [35]), and the electrical insulation region forming, as a whole, a gate dielectric (Hamamura, 6 as HAHAH between thin SiO2 layers, fig6, [36]).
Re claim 18, Hamamura teaches a device (fig6), comprising:
a Silicon Carbide body (1 and 2, fig6, [35]);
an electrical terminal (7 and 6, fig6, [35, 36]) on the body, including: a first tunneling insulating layer (6a as SiO2 ~3nm ~8eV, fig6, [36]) in contact with the body, having a first bandgap value and a first thickness;
a second insulating layer (6d as SiN 0.5* (0.9* (thickness of 6) band gap ~5ev, fig6, [40]) on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness; and
a third insulating layer (6b as HfO2 6eV ~10% thickness of 6, fig6, [36, 44]) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values.
Hamamura does not explicitly show a third insulating layer on the second insulating layer, having a third thickness greater than the second thickness.
Yamamoto teaches a thin interfacial SiO2 layer (17 ~0.5-1nm, fig5B, [86, 94]) with an Al2O3/HfO2/ Al2O3 stack (3 as Al2O3 ~0.2-2nm, 4 as HfO2 ~1-5nm, fig5B, [74, 75, 85]).
Kim teaches HK laminate structure of HAHAH ([48]) with thin interfacial SiO2 of about 0.1-0.2 nm (208, fig2D, [69]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Hamamura, Yamamoto and Kim to form an HAHAH stack between two thin interfacial SiO2 layer. The motivation to do so is to reduce leakage current (Kim, [47]; Yamamoto, [62]).
The outcome of the combination teaches a first insulating layer in contact with the semiconductor body, having a first bandgap value and a first thickness, (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6);
a second insulating layer on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness (6d as HfO2 ~1-5nm ~6ev, fig6); and
a third insulating layer (6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values and a third thickness greater than the second thickness.
Re claim 19, Hamamura modified above teaches the device of claim 18 wherein the first insulating layer is of one from among: SiN, SiO2 (Hamamura, 6a as SiO2 ~0.5-1nm ~8eV, fig6), AlN; the second insulating layer is of one from among: HfO2 (Hamamura, 6d as HfO2 ~1-5nm ~6ev, fig6), HfSiOx, ZrO2, ZrSiOx; and the third insulating layer includes two or more alternating layers of an Aluminum Oxide and a Hafnium Oxide (Hamamura, 6b-6e replaced by AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV, fig6).
Claim(s) 1, 8-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Oka et al. US 2016/0163792 in view of Yamamoto US 2002/0153579 and Kim US 2020/0020780.
Re claim 1, Oka teaches an electronic device (fig7) comprising:
a semiconductor body of Silicon Carbide (210, 212, fig7, [187]), having a first (top surface of 212, fig7) and a second face (bottom surface of 210, fig7), opposite to each other along a first direction;
an electrical terminal (230, 260 and 250, fig7, [104, 108]) at the first face, including a conductive layer (260 and 250, fig7, [108]) and an electrical insulation region (230, fig7, [104]), the electrical insulation region extending between the semiconductor body (210, 212, fig7, [187]) and the conductive layer (260 and 250, fig7, [108]),
Oka does not explicitly show the detail of the electrical insulation region.
Yamamoto teaches a thin interfacial SiO2 layer (17 ~0.5-1nm, fig5B, [86, 94]) with an Al2O3/HfO2/ Al2O3 stack (3 as Al2O3 ~0.2-2nm, 4 as HfO2 ~1-5nm, fig5B, [74, 75, 85]).
Kim teaches HK laminate structure of HAHAH ([48]) with thin interfacial SiO2 of about 0.1-0.2 nm (208, fig2D, [69]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Oka, Yamamoto and Kim to form an HAHAH stack between two thin interfacial SiO2 layer as 230. The motivation to do so is to reduce leakage current (Kim, [47]; Yamamoto, [62]) and prevent reaction of the metal oxide layer with the substrate (Yamamoto, [102]).
The outcome of the combination teaches a first insulating layer in contact with the semiconductor body, having a first bandgap value and a first thickness, (Oka, thin interfacial SiO2 ~0.5-1nm ~8eV added between 0.0 and 212, fig7);
a second insulating layer on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness (232 as HfO2 ~1-5nm ~6ev, fig7); and
a third insulating layer (AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV as the rest part of 232, fig7) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values and a third thickness greater than the second thickness.
Regarding the language of “a first insulating layer … configured to be traversed by the tunnel effect, during use, by electric charge carriers coming from the semiconductor body; a second insulating layer … configured to form a potential well for said electric charge carriers;” the Examiner notes this language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). As best can be determined by the Examiner from the specification of the present application, the structure which performs the function is simply the existence of laminated dielectric structure of a diode between anode and SiC layer, a structure which is clearly present in the device of Oka as modified by Yamamoto and Kim. Therefore, it appears the structure of a dielectric stack as modified by Yamamoto and Kim is capable of performing the function required by the claim language.
Re claim 8, Oka modified above teaches the electronic device according to claim 1, wherein said electronic device is a diode and includes: a cathode terminal (Oka, 270, fig7, [109]) extending at the second face of the semiconductor body; at least one trench (Oka, 228, fig7, [104]) extending from the first face towards the second face, said electrical insulation region (Oka, 230 as HAHAH stack between two thin interfacial SiO2 layer, fig7) extending into said trench; wherein said electrical terminal forms an anode terminal (Oka, 250 and 260, fig7, [108]) of the diode and includes a metal layer having a portion extending into said trench, said electrical insulation region extending between said portion of the anode terminal and the semiconductor body.
Re claim 9, Oka modified above teaches the electronic device according to claim 8, wherein the diode is a Schottky diode comprising at least one metal-semiconductor junction formed by an electrical contact region between the anode terminal and the semiconductor body laterally to said trench (Oka, fig7).
Re claim 10, Oka teaches a method of manufacturing an electronic device (fig7) comprising:
providing a semiconductor body of Silicon Carbide (210, 212, fig7, [187]), having a first (top surface of 212, fig7) and a second face (bottom surface of 210, fig7), opposite to each other along a first direction;
forming an electrical terminal (230, 260 and 250, fig7, [104, 108]) at the first face, including forming a conductive layer(260 and 250, fig7, [108]) and an electrical insulation region (230, fig7, [104]) between the conductive layer and the semiconductor body, configured to electrically insulate the electrical terminal from the semiconductor body,
Oka does not explicitly show the detail of the electrical insulation region.
Yamamoto teaches a thin interfacial SiO2 layer (17 ~0.5-1nm, fig5B, [86, 94]) with an Al2O3/HfO2/ Al2O3 stack (3 as Al2O3 ~0.2-2nm, 4 as HfO2 ~1-5nm, fig5B, [74, 75, 85]).
Kim teaches HK laminate structure of HAHAH ([48]) with thin interfacial SiO2 of about 0.1-0.2 nm (208, fig2D, [69]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Oka, Yamamoto and Kim to form an HAHAH stack between two thin interfacial SiO2 layer as 230. The motivation to do so is to reduce leakage current (Kim, [47]; Yamamoto, [62]) and prevent reaction of the metal oxide layer with the substrate (Yamamoto, [102]).
The outcome of the combination teaches a first insulating layer in contact with the semiconductor body, having a first bandgap value and a first thickness, (Oka, thin interfacial SiO2 ~0.5-1nm ~8eV added between 0.0 and 212, fig7);
a second insulating layer on the first insulating layer, having a second bandgap value lower than the first bandgap value and a second thickness greater than the first thickness (232 as HfO2 ~1-5nm ~6ev, fig7); and
a third insulating layer (AHAH with Al2O3 ~0.2-2nm ~8eV, 4 as HfO2 ~1-5nm ~6eV as the rest part of 232, fig7) on the second insulating layer, having a third bandgap value comprised between the first and the second bandgap values and a third thickness greater than the second thickness.
Regarding the language of “a first insulating layer … configured to be traversed, by tunnel effect, during use, by electric charge carriers coming from the semiconductor body; a second insulating layer … configured to form a potential well for said electric charge carriers;” the Examiner notes this language constitutes functional language and while features of an apparatus may be recited either structurally or functionally, claims directed to an apparatus must be distinguished from the prior art in terms of structure rather than function. In re Schreiber, 128 F.3d 1473, 1477-78, 44 USPQ2d 1429, 1431-32 (Fed. Cir. 1997). As best can be determined by the Examiner from the specification of the present application, the structure which performs the function is simply the existence of laminated dielectric structure of a diode between anode and SiC layer, a structure which is clearly present in the device of Oka as modified by Yamamoto and Kim. Therefore, it appears the structure of a dielectric stack as modified by Yamamoto and Kim is capable of performing the function required by the claim language.
Re claim 17, Oka modified above teaches the method according to claim 10, wherein said electronic device is a diode (Oka, fig7), the manufacturing comprising: forming a cathode terminal (Oka, 270, fig7, [109]) extending at the second face of the semiconductor body; forming at least one trench (Oka, 228, fig7, [104]) extending from the first face towards the second face, said electrical insulation region (Oka, 230 as HAHAH stack between two thin interfacial SiO2 layer, fig7) extending into said trench; wherein said electrical terminal is an anode terminal (Oka, 250 and 260, fig7, [108]) of the diode and includes a metal layer (Oka, 260, fig7, [108]) having a portion extending into said trench, said electrical insulation region (Oka, 230 as HAHAH stack between two thin interfacial SiO2 layer, fig7) extending between said portion of the anode terminal and the semiconductor body.
Conclusion
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/XIAOMING LIU/Examiner, Art Unit 2812