DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action responds to the Amendment filed 10 June 2026. By this amendment, claims 1-10, 13-16 and 18-20 are amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Noguchi et al (USPN 7,042,095).
Regarding claim 1, Noguchi et al disclose a semiconductor structure, comprising:
a first interconnect structure 25b including at least one conductive element [see Fig. 9; see also col. 9, lines 56-59]; and
a second interconnect structure 38 disposed on the first interconnect structure, and including
a plurality of first conductive features 38b spaced apart from each other, at least one of the plurality of first conductive features being electrically connected to the at least one conductive element [see Fig, 17; see also col. 14, lines 37-40], respectively,
a plurality of spacer layers 38a laterally covering the plurality of first conductive features;
an etch stop layer 39 (called “barrier insulating film”) conformally covering the spacer layers and disposed over the plurality of first conductive features [see Fig. 18; see also col. 1, lines 24-30 and col. 14, lines 53-59; while Noguchi et al do not specifically disclose the use of the barrier insulating film as an etch stop layer, Noguchi et al do disclose wherein the layer is formed, for example, of silicon nitride, which is one of the materials named in the instant specification as a suitable etch stop layer], and
a dielectric layer 41 disposed on the etch stop layer, wherein the etch stop layer includes:
a top portion disposed over the plurality of first conductive features and interfacing the dielectric layer, and
a surrounding portion extending downwardly from the top portion to laterally cover the plurality of spacer layers [see Fig. 19].
Regarding claim 3, Noguchi et al disclose the semiconductor structure according to claim 1, furthermore wherein the dielectric layer includes air gaps 40 among the plurality of first conductive features, the air gaps being spaced apart from the surrounding portion of the etch stop layer by the dielectric layer [see Fig. 19].
Regarding claim 4, Noguchi et al disclose the semiconductor structure according to claim 1, furthermore wherein the surrounding portion of the etch stop layer interfaces the dielectric layer [see Fig. 19].
Regarding claim 5, Noguchi et al disclose the semiconductor structure according to claim 1, furthermore comprising at least one second conductive feature 61 which penetrates through the dielectric layer and the top portion of the etch stop layer so as to electrically connect to the at least one of the plurality of first conductive features, respectively, and which is positioned within the top portion of the etch stop layer [see Fig. 26].
Regarding claim 6, Noguchi et al disclose the semiconductor structure according to claim 1, furthermore wherein the plurality of spacer layers are separated from the dielectric layer by the surrounding portion of the etch stop layer [see Fig. 19].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9, 10 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Noguchi et al (USPN 7,042,095) in view of Chi et al (US Patent Application Publication 2015/0311151).
Regarding claim 2, Noguchi et al disclose the semiconductor structure according to claim 1. Noguchi et al do not disclose further comprising a conductive capping layer disposed on the plurality of first conductive features and below the top portion of the etch stop layer. One such as Chi et al disclose a semiconductor structure, comprising: a first interconnect structure 206 including at least one conductive element; and a second interconnect structure disposed on the first interconnect structure, and including a plurality of first conductive features 220 spaced apart from each other, at least one of the plurality of first conductive features being electrically connected to the at least one conductive element, respectively, a plurality of spacer layers 216 laterally covering the plurality of first conductive features; an etch stop layer 224 covering the spacer layers and disposed over the plurality of first conductive features, and a dielectric layer 228 disposed on the etch stop layer; and further comprising a conductive capping layer 222 disposed on the first conductive features and below the etch stop layer [see Fig. 5; see also paragraph 0023-0025]. It would have been obvious to one of ordinary skill in the art the time of invention to include the conductive capping layer of Chi et al in the structure of Noguchi et al because Chi et al disclose that this layer beneficially improves electromigration characteristics of the conductive features [see paragraph 0023].
Regarding claim 9, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 2. Furthermore, the combination of Noguchi et al and Chi et al would disclose wherein the top portion of the etch stop layer is disposed between the conductive capping layer, which is formed over the first conductive features, and the and the dielectric layer which is formed thereover.
Regarding claim 10, Noguchi et al disclose a semiconductor structure, comprising:
a first interconnect structure 25b including a conductive element [see Fig. 9; see also col. 9, lines 56-59];
a first conductive feature 38b electrically connected to the conductive element [see Fig. 17; see also col. 14, lines 37-40];
a spacer layer 38a laterally covering the first conductive feature;
an etch stop layer 39 (called “barrier insulating film”) conformally covering the spacer layer [see Fig. 18; see also col. 1, lines 24-30 and col. 14, lines 53-59; while Noguchi et al do not specifically disclose the use of the barrier insulating film as an etch stop layer, Noguchi et al do disclose wherein the layer is formed, for example, of silicon nitride, which is one of the materials named in the instant specification as a suitable etch stop layer];
a dielectric layer 41 surrounding the first conductive feature, the spacer layer, and the etch stop layer, and including an air gap 40 adjacent to the first conductive feature [see Fig. 19], wherein the etch stop layer includes:
a top portion; and
a surrounding portion extending downwardly from the top portion to laterally cover the spacer layer.
Noguchi et al do not disclose a conductive capping layer disposed on the first conductive feature, or wherein the etch stop layer conformally covers the conductive capping layer, nor finally wherein the top portion of the etch stop layer is spaced apart from the first conductive feature by the conductive capping layer and wherein the surrounding portion laterally covers the conductive capping layer. One such as Chi et al disclose semiconductor structure, comprising: a first interconnect structure 206 including at least one conductive element; and a second interconnect structure disposed on the first interconnect structure, and including a plurality of first conductive features 220 spaced apart from each other, at least one of the first conductive features being electrically connected to the at least one conductive element, respectively, a plurality of spacer layers 216 laterally covering the first conductive features; an etch stop layer 224 covering the spacer layers and disposed over the first conductive features, and a dielectric layer 228 disposed on the etch stop layer; and further comprising a conductive capping layer 222 disposed on the first conductive features and below the etch stop layer [see Fig. 5; see also paragraph 0023-0025]. It would have been obvious to one of ordinary skill in the art the time of invention to include the conductive capping layer of Chi et al in the structure of Noguchi et al because Chi et al disclose that this layer beneficially improves electromigration characteristics of the conductive features [see paragraph 0023].
Furthermore, the combination of Noguchi et al and Chi et al would result in a structure wherein the top portion of the etch stop layer is spaced apart from the first conductive feature by the conductive capping layer and wherein the surrounding portion laterally covers the conductive capping layer.
Regarding claim 13, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 10. Furthermore, Noguchi et al disclose wherein the etch stop layer further includes a bottom portion disposed below the air gap, the surrounding portion of the etch stop layer interconnecting the top portion and bottom portion of the etch stop layer [see Fig. 19].
Regarding claim 14, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 10. Furthermore, the combination of Noguchi et al and Chi et al would disclose wherein the conductive capping layer is spaced apart from the dielectric layer by the top portion of the etch stop layer.
Regarding claim 15, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 10. Furthermore, Noguchi et al disclose comprising a second conductive feature 61 which penetrates through the dielectric layer, and the top portion of the etch stop layer so as to electrically connect to the first conductive feature, and which is positioned within the top portion of the etch stop layer [see Fig. 26]. Moreover, the combination with Chi et al would result in a structure wherein the second conductive feature penetrates through the conductive capping layer.
Regarding claim 16, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 10. Furthermore, Noguchi et al disclose wherein the spacer layer is separated from the dielectric layer by the surrounding portion of the etch stop layer [see Fig. 19].
Regarding claim 17, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 10. Furthermore to the conductive capping layer, Chi et al disclose wherein the conductive capping layer includes a conductive carbon-based material, a conductive polymer, a conductive organic composite, a conductive ceramic composite, a conductive metal composite, or combinations thereof [see paragraph 0024].
Regarding claim 18, Noguchi et al disclose a semiconductor structure, comprising:
a semiconductor substrate 1; and
an interconnect structure 25 disposed on the semiconductor substrate, and including
a plurality of first conductive features 25b spaced apart from each other [see Fig. 9; see also col. 9, lines 56-59],
a plurality of spacer layers 25a laterally covering the plurality of first conductive features,
a first etch stop layer 39 (called “barrier insulating film”) conformally covering the plurality of spacer layers [see Fig. 18; see also col. 1, lines 24-30 and col. 14, lines 53-59; while Noguchi et al do not specifically disclose the use of the barrier insulating film as an etch stop layer, Noguchi et al do disclose wherein the layer is formed, for example, of silicon nitride, which is one of the materials named in the instant specification as a suitable etch stop layer],
a dielectric layer 41 disposed on the first etch stop layer; and
a second etch stop layer 30 spaced apart from the dielectric layer by the first etch stop layer [see Fig. 15; see also col. 14, lines 24-26], wherein the first etch stop layer includes:
a top portion and a bottom portion respectively distal from and proximate to the second etch stop layer, and
a surrounding portion interconnecting the top portion and the bottom portion and laterally covering the plurality of spacer layers.
Noguchi et al do not disclose a conductive capping layer disposed on the plurality of first conductive features, nor correspondingly wherein the first etch stop layer conformally covers the conductive capping layer, specifically via the surrounding portion. One such as Chi et al disclose a semiconductor structure, comprising: a first interconnect structure 206 including at least one conductive element; and a second interconnect structure disposed on the first interconnect structure, and including a plurality of first conductive features 220 spaced apart from each other, at least one of the plurality of first conductive features being electrically connected to the at least one conductive element, respectively, a plurality of spacer layers 216 laterally covering the plurality of first conductive features; an etch stop layer 224 covering the spacer layers and disposed over the plurality of first conductive features, and a dielectric layer 228 disposed on the etch stop layer; and further comprising a conductive capping layer 222 disposed on the first conductive features and below the etch stop layer [see Fig. 5; see also paragraph 0023-0025]. It would have been obvious to one of ordinary skill in the art the time of invention to include the conductive capping layer of Chi et al in the structure of Noguchi et al because Chi et al disclose that this layer beneficially improves electromigration characteristics of the conductive features [see paragraph 0023].
Regarding claim 19, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 18. Furthermore, Noguchi et al disclose wherein the bottom portion of the first etch stop layer interfaces the second etch stop layer [see Fig. 19].
Regarding claim 20, the prior art of Noguchi et al and Chi et al disclose the semiconductor structure according to claim 18. Furthermore, Noguchi et al disclose comprising a second conductive feature 61 which penetrates through the dielectric layer, and the top portion of the etch stop layer so as to electrically connect to the first conductive feature, and which is positioned within the top portion of the etch stop layer [see Fig. 26]. Moreover, the combination with Chi et al would result in a structure wherein the second conductive feature penetrates through the conductive capping layer.
Allowable Subject Matter
Claims 7, 8, 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claims 7 and 11, and claims 8 and 12 which depend therefrom, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the dielectric layer includes a lower dielectric sub-layer disposed on the first interconnect structure, and an upper dielectric sub-layer disposed on the lower dielectric sub-layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899
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