DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Oshida (US Patent Application Publication 2013/0207269) in view of Gabric et al (USPN 7,807,563).
Regarding claim 1, Oshida discloses a semiconductor structure, comprising:
a first interconnect structure 240 including at least one conductive element; and
a second interconnect structure disposed on the first interconnect structure, and including
a plurality of first conductive features 320 spaced apart from each other, at least one of the first conductive features being electrically connected to the at least one conductive element, respectively,
a plurality of spacer layers 310 laterally covering the first conductive features; and
a dielectric layer 410 disposed on the conductive features [see Fig. 1; see also paragraph 0028].
Oshida does not disclose an etch stop layer conformally covering the spacer layers and disposed over the first conductive features. One such as Gabric et al disclose a semiconductor structure, comprising: a plurality of first conductive structures 102 spaced apart from each other, a plurality of spacer layers 301 laterally covering the first conductive features; an etch stop layer 401 conformally covering the spacer layers and disposed over the first conductive features [see Fig. 4; see also col. 10, line 63 to col. 11, line 8], and a dielectric layer 701 disposed on the etch stop layer [see Fig. 7; see also col. 11, lines 31-39]. While Gabric et al do not name the conformal electrically insulating layer 401 as an etch stop layer, the materials disclosed by Gabric et al at col. 10, line 63 to col. 11, line 8 are similar to those disclosed in the instant specification in paragraph 0014 and thus would behave in predictable ways, including as an etch stop if needed. It would have been obvious to one of ordinary skill in the art at the time of invention to include the electrically insulating layer of Gabric et al, i.e. an etch stop layer as discussed above, because Gabric et al teach that this layer inhibits growth of the dielectric layer formed thereover where it is not preferred [see col. 10, line 66 to col. 11, line 1].
Regarding claim 3, the prior art of Oshida and Gabric et al disclose the semiconductor structure according to claim 1. Furthermore, Oshida discloses wherein the dielectric layer includes air gaps 500 among the first conductive features [see Fig. 1].
Regarding claims 4 and 9, the prior art of Oshida and Gabric et al disclose the semiconductor structure according to claims 1 and 2. Furthermore to the etch stop layer, Gabric et al disclose wherein the etch stop layer includes a top portion disposed over the first conductive features, and a surrounding portion extending downwardly from the top portion to cover the spacer layer [see Fig. 4].
Regarding claim 5, the prior art of Oshida and Gabric et al disclose the semiconductor structure according to claim 1. Furthermore, Oshida discloses comprising at least one second conductive feature 320 which penetrates through the dielectric layer and the top portion of the etch stop layer so as to electrically connect to that least one of the first conductive features, respectively, and which is positioned within the top portion of the etch stop layer [see Fig. 1].
Regarding claim 6, the prior art of Oshida and Gabric et al disclose the semiconductor structure according to claim 1. Furthermore to the etch stop layer, Gabric et al disclose wherein the spacer layers are separated from the dielectric layer by the etch stop layer [see Fig. 7].
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Oshida (US Patent Application Publication 2013/0207269) in view of Gabric et al (USPN 7,807,563) as applied to claim 1 above, and further in view of Chi et al (US Patent Application Publication 2015/0311151).
Regarding claim 2, the prior art of Oshida and Gabric et al disclose the semiconductor structure according to claim 1. Neither Oshida nor Gabric et al disclose further comprising a conductive capping layer disposed on the first conductive features and below the etch stop layer. One such as Chi et al disclose semiconductor structure, comprising: a first interconnect structure 206 including at least one conductive element; and a second interconnect structure disposed on the first interconnect structure, and including a plurality of first conductive features 220 spaced apart from each other, at least one of the first conductive features being electrically connected to the at least one conductive element, respectively, a plurality of spacer layers 216 laterally covering the first conductive features; an etch stop layer 224 covering the spacer layers and disposed over the first conductive features, and a dielectric layer 228 disposed on the etch stop layer; and further comprising a conductive capping layer 222 disposed on the first conductive features and below the etch stop layer [see Fig. 5; see also paragraph 0023-0025]. It would have been obvious to one of ordinary skill in the art the time of invention to include the conductive capping layer of Chi et al in the structure of Oshida, as modified by Gabric et al, because Chi et al disclose that this layer beneficially improves electromigration characteristics of the conductive features [see paragraph 0023].
Claims 10 and 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oshida (US Patent Application Publication 2013/0207269) in view of Chi et al (US Patent Application Publication 2015/0311151) and Gabric et al (USPN 7,807,563).
Regarding claim 10, Oshida discloses a semiconductor structure, comprising:
a first interconnect structure 240 including a conductive element; and
a first conductive feature 320 electrically connected to the conductive element;
a spacer layer 310 laterally covering the first conductive feature; and
a dielectric layer 410 surrounding the first conductive feature, the spacer layer, and including an air gap 500 adjacent to the first conductive feature [see Fig. 1; see also paragraph 0028].
Oshida does not disclose a conductive capping layer disposed on the first conductive features, nor an etch stop layer conformally covering the spacer layer and disposed over the first conductive feature. One such as Chi et al disclose semiconductor structure, comprising: a first interconnect structure 206 including a conductive element; a first conductive feature 220 electrically connected to the conductive element; a spacer layer 216 laterally covering the first conductive feature; a conductive capping layer 222 disposed on the first conductive feature; an etch stop layer 224 covering the spacer layer and the conductive capping layer; and a dielectric layer 228 surrounding the first conductive feature, the spacer layer, and the etch stop layer, and including an air gap 230 adjacent to the first conductive feature [see Figs. 5 and 8; see also paragraph 0023-0025]. It would have been obvious to one of ordinary skill in the art the time of invention to include the conductive capping layer of Chi et al in the structure of Oshida because Chi et al disclose that this layer beneficially improves electromigration characteristics of the conductive features [see paragraph 0023].
Furthermore, Chi et al disclose an etch stop layer, but not wherein the etch stop layer is conformally formed over the spacer layer and the conductive capping layer. One such as Gabric et al disclose a semiconductor structure, comprising: a first conductive structure 102, a spacer layer 301 laterally covering the first conductive feature; an etch stop layer 401 conformally covering the spacer layer and disposed over the first conductive feature [see Fig. 4; see also col. 10, line 63 to col. 11, line 8], and a dielectric layer 701 disposed on the etch stop layer [see Fig. 7; see also col. 11, lines 31-39]. While Gabric et al do not name the conformal electrically insulating layer 401 as an etch stop layer, the materials disclosed by Gabric et al at col. 10, line 63 to col. 11, line 8 are similar to those disclosed in the instant specification in paragraph 0014 and thus would behave in predictable ways, including as an etch stop if needed. It would have been obvious to one of ordinary skill in the art at the time of invention to include the electrically insulating layer of Gabric et al, i.e. an etch stop layer as discussed above, in a conformal manner, because Gabric et al teach that this layer inhibits growth of the dielectric layer formed thereover where it is not preferred, which feature is enhanced by the conformal nature of the layer [see col. 10, line 66 to col. 11, line 1].
Regarding claim 13, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 10. Furthermore to the conformal etch stop layer, Gabric et al disclose wherein the etch stop layer includes a top portion disposed over the first conductive features, and a surrounding portion extending downwardly from the top portion to cover the spacer layer [see Fig. 4].
Regarding claim 14, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 13. Furthermore to the conductive capping layer, Chi et al disclose wherein the conductive capping layer is disposed between the top portion of the etch stop layer and the first conductive feature [see Fig. 4].
Regarding claim 15, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 14. Furthermore, Oshida discloses comprising at least one second conductive feature 320 which penetrates through the dielectric layer and the top portion of the etch stop layer so as to electrically connect to that least one of the first conductive features, respectively, and which is positioned within the top portion of the etch stop layer [see Fig. 1].
Regarding claim 16, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 13. Furthermore to the conformal etch stop layer, Gabric et al disclose wherein the spacer layer is separated from the dielectric layer by the surrounding portion of the etch stop layer [see Fig. 4].
Regarding claim 17, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 10. Furthermore to the conductive capping layer, Chi et al disclose wherein the conductive capping layer includes a conductive carbon-based material, a conductive polymer, a conductive organic composite, a conductive ceramic composite, a conductive metal composite, or combinations thereof [see paragraph 0024].
Regarding claim 18, Oshida discloses a semiconductor structure, comprising:
a semiconductor substrate 100;
an interconnect structure disposed on the semiconductor substrate, and including
a plurality of first conductive features 240 spaced apart from each other,
a plurality of spacer layers 310 laterally covering the first conductive features, and
a dielectric layer 410 disposed on the conductive features [see Fig. 1; see also paragraph 0028].
Oshida does not disclose a conductive capping layer disposed on the first conductive features, nor an etch stop layer conformally covering the spacer layer and disposed over the first conductive feature. One such as Chi et al disclose semiconductor structure, comprising: a first interconnect structure 206 including a conductive element; a first conductive feature 220 electrically connected to the conductive element; a spacer layer 216 laterally covering the first conductive feature; a conductive capping layer 222 disposed on the first conductive feature; an etch stop layer 224 covering the spacer layer and the conductive capping layer; and a dielectric layer 228 surrounding the first conductive feature, the spacer layer, and the etch stop layer, and including an air gap 230 adjacent to the first conductive feature [see Figs. 5 and 8; see also paragraph 0023-0025]. It would have been obvious to one of ordinary skill in the art the time of invention to include the conductive capping layer of Chi et al in the structure of Oshida because Chi et al disclose that this layer beneficially improves electromigration characteristics of the conductive features [see paragraph 0023].
Furthermore, Chi et al disclose an etch stop layer, but not wherein the etch stop layer is conformally formed over the spacer layer and the conductive capping layer. One such as Gabric et al disclose a semiconductor structure, comprising: a first conductive structure 102, a spacer layer 301 laterally covering the first conductive feature; an etch stop layer 401 conformally covering the spacer layer and disposed over the first conductive feature [see Fig. 4; see also col. 10, line 63 to col. 11, line 8], and a dielectric layer 701 disposed on the etch stop layer [see Fig. 7; see also col. 11, lines 31-39]. While Gabric et al do not name the conformal electrically insulating layer 401 as an etch stop layer, the materials disclosed by Gabric et al at col. 10, line 63 to col. 11, line 8 are similar to those disclosed in the instant specification in paragraph 0014 and thus would behave in predictable ways, including as an etch stop if needed. It would have been obvious to one of ordinary skill in the art at the time of invention to include the electrically insulating layer of Gabric et al, i.e. an etch stop layer as discussed above, in a conformal manner, because Gabric et al teach that this layer inhibits growth of the dielectric layer formed thereover where it is not preferred, which feature is enhanced by the conformal nature of the layer [see col. 10, line 66 to col. 11, line 1].
Regarding claim 19, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 18. Furthermore to the conformal etch stop layer, Gabric et al disclose wherein the etch stop layer includes a top portion disposed over the first conductive features, and a surrounding portion extending downwardly from the top portion to cover the spacer layer [see Fig. 4].
Regarding claim 20, the prior art of Oshida, Chi et al and Gabric et al disclose the semiconductor structure according to claim 19. Furthermore, Oshida discloses comprising at least one second conductive feature 320 which penetrates through the dielectric layer and the top portion of the etch stop layer so as to electrically connect to that least one of the first conductive features, respectively, and which is positioned within the top portion of the etch stop layer [see Fig. 1].
Allowable Subject Matter
Claims 7, 8, 11 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: regarding dependent claims 7 and 11, and claims 8 and 12 which depend therefrom, the prior art of record fails to teach or make reasonably obvious, in combination with the other claimed elements, wherein the dielectric layer includes a lower dielectric sub-layer disposed on the first interconnect structure, and an upper dielectric sub-layer disposed on the lower dielectric sub-layer.
Conclusion
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/C.E.S./Examiner, Art Unit 2899 /VICTOR A MANDALA/Primary Examiner, Art Unit 2899