DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Doyle (U.S. 6,228,691)
Regarding claim 1. Zhao et al discloses a method (FIG. 1-8) comprising:
depositing an etch stop layer (ESL) (FIG. 1, item 103) over a dummy gate structure (FIG. 1, item 110), a first source/drain region (FIG. 1, item 102), and a second source/drain region (FIG. 1, item 102), wherein the dummy gate structure (FIG. 1, item 101) is disposed between ([0014]) the first source/drain region (FIG. 1, item 102) and the second source/drain region (FIG. 1, item 102) along a first direction (FIG. 1, left to right), the dummy gate structure (FIG. 1, item 110) is disposed over a channel region ([0014]) disposed between ([0014]) the first source/drain region (FIG. 1, item 102) and the second source/drain region (FIG. 1, item 102), and the dummy gate structure (FIG. 1, item 101) extends lengthwise (FIG. 1, into the page) along a second direction (FIG. 1, into the page) different (FIG. 1, into the page is different to left to right) from the first direction (FIG. 1, left to right)
forming a first dielectric layer (FIG. 3, item 204) over the ESL (FIG. 2, item 203) wherein the forming of the first dielectric layer (FIG. 3, item 204) includes a deposition step ([0041], i.e. deposition process) and an annealing step ([0042], i.e. The temperature of the densify HARP may be in a range);
after the forming of the first dielectric layer (FIG. 3, item 204) including the deposition step ([0041]) and the annealing step ([0042]) and before performing a chemical mechanical planarization (CMP) process (FIG. 5-7, [0062]-[0063]) on the first dielectric layer (FIG. 3, item 204), hardening ([0043]; i.e. Correspondingly, the hardness of the first dielectric layer 204 may be increased) a portion (FIG. 3, items 204) of the first dielectric layer (FIG. 3, items 204), wherein a hardened portion ([0043]) of the first dielectric layer (FIG. 3, items 204) has a first hardness ([0043]);
after the hardening ([0043]) of the portion (FIG. 3, items 204) of the first dielectric layer (FIG. 3, items 204), depositing a second dielectric layer (FIG. 4, items 205) over the hardened portion ([0043]) of the first dielectric layer (FIG. 4, items 204),
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and performing the CMP process (FIG. 5-6; [0058]) to both the first dielectric layer (FIG. 5-7, item 204) and the second dielectric layer (FIG. 5-6, item 205) to completely remove (FIG. 5-6; [0058]) the second dielectric layer (FIG. 5-6, item 204) and partially remove (FIG. 5-7; [0058]) the hardened portion ([0043]) of the first dielectric layer (FIG. 7, item 204).
Zhao et al fails to explicitly disclose wherein the second dielectric layer has a second hardness higher than the first hardness of the hardened portion of the first dielectric layer.
However, Doyle teaches wherein the second dielectric layer has a second hardness higher than the first hardness of the hardened portion of the first dielectric layer (Claim 16, i.e. depositing a second dielectric layer on said first dielectric layer, said second dielectric layer exhibiting a hardness that is substantially greater than that of said first dielectric layer).
Since Zhao et al and Doyle teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al with the teachings of wherein the second dielectric layer has a second hardness higher than the first hardness of the hardened portion of the first dielectric layer as disclosed by Doyle. The use of depositing a second dielectric layer on said first dielectric layer, said second dielectric layer exhibiting a hardness that is substantially greater than that of said first dielectric layer in Doyle provides for a controlled thickness that determines a desired thickness of silicon-on-insulator (SOI) islands (Doyle, [Claim 16]).
Regarding claim 9. Zhao et al and Doyle discloses all the limitations of the method of claim 1 above.
Zhao et al further discloses further discloses wherein the hardened portion ([0043]) of the first dielectric layer (FIG. 3, items 204) extends below a top surface (FIG. 3, items 211) of the dummy gate structure (FIG. 3, items 201).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Doyle (U.S. 6,228,691) as applied to claim 1 above, and further in view of Datta et al (U.S. 2005/0245036)
Regarding claim 2. Zhao et al and Doyle discloses all the limitations of the method of claim 1 above.
Zhao et al further discloses
wherein the dummy gate structure (FIG. 3, item 201) comprises:
an oxide layer (FIG. 3, item 210) disposed on the channel region ([0014]);
a dummy electrode layer (FIG. 3, item 211) disposed over the oxide layer (FIG. 3, items 210 and 212);
wherein the hardened portion ([0043]) of the first dielectric layer (FIG. 3, item 204) is disposed above ([0038]) the dummy electrode layer (FIG. 3, item 211) of the dummy gate structure (FIG. 3, item 201).
Zhao et al and Doyle fails to explicitly disclose
a hard mask layer over the dummy electrode layer; and
a capping layer over the hard mask layer,
Datta et al teaches a hard mask layer (FIG. 1A, item 130) over the dummy electrode layer (FIG. 1A, item 104); and
a capping layer over (FIG. 1A, item 132; [0015]) Etch stop layers 132, 133 may, for example, be made from an oxide (e.g., silicon dioxide)) the hard mask layer (FIG. 1A, item 130).
Since Zhao et al Doyle and Datta et al teach dummy structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al with the teachings of a hard mask layer over the dummy electrode layer and
a capping layer over the hard mask layer as disclosed by Datta et al. The use of etch stop layers made from an oxide (e.g., silicon dioxide) in Datta et al provides for a material that will be removed at a substantially slower rate than silicon nitride will be removed when an appropriate etch process is applied (Datta et al, [0015]).
Regarding claim 3. Zhao et al, Doyle and Datta et al discloses all the limitations of the method of claim 2 above.
Zhao et al further wherein, after the depositing of the ESL (FIG. 2, item 203), the ESL (FIG. 2, item 203) is in direct contact with the oxide layer (FIG. 2, item 212), the dummy electrode layer (FIG. 2, item 211),
Datta et al disclose the ESL (FIG. 1B, item 134) is in direct contact ([0018]) with the oxide layer (FIG. 1B, item 105), the dummy electrode layer (FIG. 1B, item 104), the hard mask layer (FIG. 1B, item 130), and the capping layer (FIG. 1B, item 132).
Regarding claim 4. Zhao et al, Doyle and Datta et al discloses all the limitations of the method of claim 2 above.
Zhao et al further discloses wherein:
the dummy electrode (FIG. 3, item 211) layer comprises polysilicon ([0027], i.e. gate electrode layer 211 is made of poly silicon);
Datta et al discloses the hard mask layer (FIG. 1A, item 130) comprises silicon nitride ([0015], 130, 131 may comprise silicon nitride), the capping layer (FIG. 1A, item 132) comprises silicon oxide ([0015], i.e. layers 132, 133 may, for example, be made from an oxide (e.g., silicon dioxide)).
Claims 5 – 7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Doyle (U.S. 6,228,691) as applied to claim 1 above, and further in view of Nishimura et al (U.S. 6,776,691).
Regarding claim 5. Zhao et al and Doyle discloses all the limitations of the method of claim 1 above.
Zhao et al discloses hardening of the first dielectric layer ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal)
Zhao et al and Doyle fails to explicitly disclose comprises treating the first dielectric layer with a fluorine-containing oxidizer (DHF), and after the treating of the first dielectric layer with the fluorine-containing oxidizer (DHF), treating the first dielectric layer with deionized water (DIW).
However, Nishimura et al teaches comprises treating the first dielectric layer with a fluorine-containing oxidizer (DHF), and after the treating of the first dielectric layer with the fluorine-containing oxidizer (DHF), treating the first dielectric layer with deionized water (DIW) (Col 10, lines 49-54, i.e. , the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature in order to remove further the natural oxide film and effect termination of the surface of the silicon wafer. Finally, the wafer is immersed in hot ultrapure water (HWP)).
Since Zhao et al, Doyle and Nishimura et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al and Doyle with the teachings of comprises treating the first dielectric layer with a fluorine-containing oxidizer (DHF), and after the treating of the first dielectric layer with the fluorine-containing oxidizer (DHF), treating the first dielectric layer with deionized water (DIW) as disclosed by Nishimura et al. The use of the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature in order to remove further the natural oxide film and effect termination of the surface of the silicon wafer. Finally, the wafer is immersed in hot ultrapure water (HWP) in Nishimura et al provides for a polishing method that can remove potassium and other alkali metals without using a high concentration chemical agent typically containing sulfuric acid and also a method of preparing a wiring section (Nishimura et al, [Col 2, lines 13-18]).
Regarding claim 6. Zhao et al, Doyle and Nishimura et al discloses all the limitations of the method of claim 5 above.
Nishimura et al further discloses wherein the treating of the first dielectric layer is performed at a temperature ranging from 15 0C to 90 0C, the fluorine-containing oxidizer is dilute hydrofluoric acid (DHF) and a concentration of hydrofluoric acid in the fluorine-containing oxidizer ranges from 0.005% to 0.1% (Col 10, lines 49-54, i.e. the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature)
Regarding claim 7. Zhao et al, Doyle and Nishimura et al discloses all the limitations of the method of claim 5 above.
Nishimura et al further discloses wherein the treating of the first dielectric layer is performed at room temperature (Col 10, lines 49-54, i.e. the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Doyle (U.S. 6,228,691) as applied to claim 1 above, and further in view of Wang et al (U.S. 2006/0252267).
Regarding claim 8. Zhao et al and Doyle discloses all the limitations of claim 1 above.
Zhao et al disclose wherein the CMP process uses a slurry ([0016]).
Zhao et al fails to explicitly disclose uses a cerium oxide (CeO2) based slurry.
However, Wang et al teaches uses a cerium oxide (CeO2) ([0028], i.e. Both the undiluted and diluted slurry can include a ceria-based abrasive, such as a CeO2 ).
Since Zhao et al, Doyle and Wang et al teach a CMP process, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al with the teachings of uses a cerium oxide (CeO2) based slurry as disclosed by Wang et al. The use of the undiluted and diluted slurry can include a ceria-based abrasive, such as a CeO2 in Wang et al provides for a multi-step CMP process wherein a relatively high force, low topology selectivity CMP process is performed first to remove protrusions, and then a relatively low force, high topology selectivity CMP process is performed (Wang et al, [0021]).
Claims 10, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004)
Regarding claim 10. Zhao et al discloses a method (FIG. 2-8), comprising:
forming a dummy gate structure (FIG. 2, item 201) over a substrate (FIG. 2, item 200);
forming a dielectric structure (FIG. 7, item 204) adjacent sidewalls of the dummy gate structure (FIG. 7, item 201), wherein the forming of the dielectric structure (FIG. 7, item 204) includes:
performing a flowable chemical vapor deposition (FCVD) process ([0041], i.e. an FCVD process) to form a first dielectric layer (FIG. 3, items 204) of the dielectric structure (FIG. 7, item 204) over and adjacent to the sidewalls of the dummy gate structure (FIG. 2, items 201), wherein the first dielectric layer (FIG. 3, items 204) contains silicon and oxygen ([0042], i.e. the first dielectric layer 204 is made of silicon oxide) and the first dielectric layer (FIG. 3, items 204) has having a first content of silicon-oxygen bonds ([0042], i.e. made of silicon oxide), and the FCVD process includes a deposition step ([0041], i.e. deposition process) and an anneal step ([0042], i.e. The temperature of the densify HARP may be in a range),
after performing the FCVD process ([0041], i.e. an FCVD process) and before performing a chemical mechanical planarization (CMP) process ([0051], i.e. after forming the second dielectric layer 205, a first polishing process may be performed (S104)) on the first dielectric layer (FIG. 3, items 204) of the dielectric structure (FIG. 7, items 204), treating ([0043]) the first dielectric layer (FIG. 3, items 204) of the dielectric structure (FIG. 7, items 204), resulting in a treated portion ([0043]; i.e. Correspondingly, the hardness of the first dielectric layer 204 may be increased) of the first dielectric layer (FIG. 3, items 204)
depositing a second dielectric layer (FIG. 4, item 205) over the treated ([0043]) portion of the first dielectric layer (FIG. 4, item 204), and
performing the CMP (FIG. 5-7, [0062]-[0063]) to completely remove the second dielectric layer FIG. 7, shows item 205 completely removed) and partially remove the treated portion ([0043]) of the first dielectric layer (FIG. 7 shows item 204 partially removed); and
after forming the dielectric structure (FIG. 7, item 204) adjacent sidewalls of the dummy gate structure (FIG. 7, item 201), replacing the dummy gate structure (FIG. 7, item 201) with a metal gate structure (FIG. 8, item 207)
Zhao et al fails to explicitly disclose treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds.
Pal et al teaches
Treating (FIG. 2i, item 207b; [0051]) the first dielectric layer (FIG. 2i, item 220), resulting in a treated portion (FIG. 2i, item 227) of the first dielectric layer (FIG. 2i, item 220) above an untreated portion (FIG. 2i, item 222) of the first dielectric layer (FIG. 2i, item 220)
Since Zhao et al, and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Zhao et al with the teachings of treating the first dielectric layer resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Zhao et al and Pal et al fails to explicitly disclose treating the first dielectric layer with an aqueous oxidizer, wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds.
However, Tong et al teaches treating the first dielectric layer with an aqueous oxidizer (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature), wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface).
Since Zhao et al, Pal et al, and Tong et al disclose silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Zhao et al and Pal et al with the teachings of treating the first dielectric layer with an aqueous oxidizer, wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds as disclosed by Tong et al. The use of the after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
Regarding claim 12. Zhao et al, Pal et al, and Tong et al discloses all the limitations of the method of claim 10 above.
Zhao et al discloses the first dielectric layer (FIG. 3, item 204) has a first hardness after (FIG. 3 is after FIG. 2) the FCVD process (FIG. 3, item 204; [0041], i.e. an FCVD process) that corresponds with a first amount of scratch defects during the CMP process (FIG. 5-7; [0057]-[0058], [0062]-[0064]) (as best understood by the 112(b) above. [0041], i.e. an FCVD process, examiner makes notes that a first amount of scratch defect during the CMP process since applicant has only claimed a FCVD process without claiming any actual process steps in the FCVD process);
Tong et al discloses the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer (Tong, Page 2762, Second Column, second paragraph) with a second hardness wherein the second hardness corresponds with a second amount of scratch defects during the CMP process (Examiner makes note that since applicant states the aqueous oxidizer provides the second hardness, Tong treated first dielectric by the aqueous oxidizer inherently provides the second hardness)
Since Zhao et al discloses the FCVD process(FIG. 3, item 204; [0041], i.e. an FCVD process) that corresponds with a first amount of CMP scratch defects during the CMP process (FIG. 5-7; [0057]-[0058], [0062]-[0064]),
And Tong et al discloses the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer (Tong, Page 2762, Second Column, second paragraph) that is higher than the first hardness (FIG. 4, item 36),
Zhao et al in combination with Tong et al inherently discloses wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process.
Since Zhao, Pal et al, and Tong et al disclose silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et al, Lou, Pal et al and Wang et al with the teachings of treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer as disclosed by Tong et al. The use of the after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II
Regarding claim 13. Zhao et al, Pal et al, and Tong et al discloses all the limitations of the method of claim 10 above.
Tong et al further discloses wherein the aqueous oxidizer includes deionized water (DIW), dilute hydrofluoric acid (DHF) or both (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004) as applied to claim 10 above, and further in view of Datta et al (2005/0245036).
Regarding claim 11. Zhao et al, Pal et al, and Tong et al discloses all the limitations of the method of claim 10 above.
Zhao et al further discloses
wherein the dummy gate structure (FIG. 3, item 201) comprises:
an oxide layer (FIG. 3, item 210) disposed on the substrate (FIG. 3, item 200);
a dummy electrode layer (FIG. 3, item 211) disposed over the oxide layer (FIG. 3, items 210 and 212);
wherein the hardened portion ([0043]) of the first dielectric layer (FIG. 3, item 204) is disposed above ([0038]) the dummy electrode layer (FIG. 3, item 211) of the dummy gate structure (FIG. 3, item 201).
Pal et al discloses
a hard mask layer (FIG. 2g, item 264) over the dummy electrode layer (FIG. 2g, item 262); and
wherein the treated portion (FIG. 2i, item 227) of the first dielectric layer (FIG. 2i, item 220) is disposed above a top (FIG. 2i, item 264) of the dummy electrode layer (FIG. 2i, item 262) of the dummy gate structure ([0039]) and the CMP process (FIG. 2j, item 208) removes ([0053]) the treated portion (FIG. 2j, item 227)of the first dielectric layer (FIG. 2j, item 220)
Zhao et al and Pal et al fail to explicitly disclose
a capping layer over the hard mask layer,
Datta et al teaches a capping layer over (FIG. 1A, item 132; [0015]) Etch stop layers 132, 133 may, for example, be made from an oxide (e.g., silicon dioxide)) the hard mask layer (FIG. 1A, item 130).
Since Zhao et al, Pal et all, and Tong et al and Datta et al teach silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al and Pal et al with the teachings of a capping layer over the hard mask layer as disclosed by Datta et al. The use of etch stop layers made from an oxide (e.g., silicon dioxide) in Datta et al provides for a material that will be removed at a substantially slower rate than silicon nitride will be removed when an appropriate etch process is applied (Datta et al, [0015]).
Claims 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004).
Regarding claim 14. Zhao et al discloses a method of forming dielectric structures (FIG. 8, items 203 and 204) of a semiconductor device (FIG. 8), the method comprising:
forming a first dielectric layer (FIG. 2, items 203) of the dielectric structures (FIG. 8, items 203 and 204) in trenches (FIG. 2, items 202) between dummy gate structures (FIG. 2, items 201) disposed over a substrate (FIG. 2, items 200), wherein the first dielectric layer (FIG. 2, items 203) is formed ([0022]) over the substrate (FIG. 2, items 200), sidewalls (FIG. 2, items 212) of the dummy gate structures (FIG. 2, items 201), and tops (FIG. 2, items 211) of the dummy gate structures (FIG. 2, items 201);
performing a flowable chemical vapor deposition (FCVD) process ([0041], i.e. an FCVD process) to form a second dielectric layer (FIG. 3, items 204) of the dielectric structures (FIG. 8, items 203 and 204) over the first dielectric layer (FIG. 3, items 203) and filling the trenches (FIG. 2, items 202) between the dummy gate structures (FIG. 3, items 201), wherein the FCVD process includes a deposition step ([0041], i.e. deposition process) and an anneal step ([0042], i.e. The temperature of the densify HARP may be in a range),
after performing the FCVD process ([0041], i.e. an FCVD process) and before performing a chemical mechanical planarization (CMP) process ([0051], i.e. after forming the second dielectric layer 205, a first polishing process may be performed (S104)) on the second dielectric layer (FIG. 3, items 204), hardening ([0043]; i.e. Correspondingly, the hardness of the first dielectric layer 204 may be increased) the second dielectric layer (FIG. 3, items 204) of the dielectric structures (FIG. 8, items 203 and 204) to form a hardened portion (FIG. 3, items 204) of the second dielectric layer (FIG. 3, items 204).
depositing a third second dielectric layer (FIG. 4, item 205) over the hardened portion ([0043]) of the second dielectric layer (FIG. 4, item 204) of the dielectric structures (FIG. 8, items 203 and 204); and
performing the CMP (FIG. 5-7, [0062]-[0063]) to completely remove the third dielectric layer (FIG. 7, shows item 205 completely removed) and partially remove the second dielectric layer (FIG. 6 shows item 204 partially removed)
Zhao et al fails to explicitly disclose hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form a hardened portion of the second dielectric layer over a non-hardened portion of the second dielectric layer
However, Pal et al teaches hardening (FIG. 2i, item 207b; [0051]) the second dielectric layer (FIG. 2i, item 220) of the dielectric structures (FIG. 2j, item 220) to form a hardened portion (FIG. 2i, item 227) of the second dielectric layer (FIG. 2i, item 220) over a non-hardened portion (FIG. 2i, item 222) of the second dielectric layer (FIG. 2i, item 220)
Since Zhao et al, and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Zhao et al with the teachings of hardening the second dielectric layer of the dielectric structures to form a hardened portion of the second dielectric layer over a non-hardened portion of the second dielectric layer as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Zhao et al and Pal et al fails to explicitly disclose hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form a hardened portion of the second dielectric layer
However, Tong et al (‘2004) teaches hardening the second dielectric layer with aqueous oxidizer (Tong, Page 2762, Second Column, second paragraph, i.e. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min) to form a hardened portion of the second dielectric layer (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface);
Since Zhao et al, Pal et al, and Tong et al (‘2004) teach silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Zhao et al and Pal et al with the teachings of the hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form a hardened portion of the second dielectric layer as disclosed by Tong et al (‘2004). The use of the HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
Regarding claim 15. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Tong et al (‘2004) further comprising tuning parameters of the hardening of the second dielectric layer of the dielectric structures with the aqueous oxidizer to provide the hardened portion of the second dielectric layer with a hardness (Tong, Page 2762, Second Column, second paragraph, i.e. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) that reduces scratch defects during the CMP process (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface).
Regarding claim 16. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Zhao et al further discloses wherein the first dielectric layer (FIG. 2, items 203) abuts the sidewalls ([0022]) and the tops ([0022]) of the dummy gate structures (FIG. 2, items 201).
Regarding claim 17. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Tong et al (‘2004) wherein the hardening of the second dielectric layer with the aqueous oxidizer comprises a treating process with deionized water (DIW) and a treating process with dilute hydrofluoric acid (DHF), or both (Tong, Page 2762, Second Column, second paragraph, i.e. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min).
Regarding claim 18. Zhao et al, Pal et al and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Tong et al (‘2004) further discloses further comprising tuning parameters of the hardening of the first dielectric layer of the isolation structures with the aqueous oxidizer to provide the hardened portion of the first dielectric layer without strain relaxation (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min).
Applicant’s specifications at [0026] states Particularly, the operation 16 is performed at a temperature below 100° C., which is consistent with certain wet bench manufacturing flows when the oxidizer 116 is aqueous. For example, the operation 16 may be performed at a temperature ranging from 15° C. to 90° C., such as at room temperature of about 25° C. Notably, such temperature is much lower than typical temperatures used for annealing the dielectric layer 114 in the operation 14. Accordingly, the operation 16 does not lead to the strain relaxation issue discussed above.
Tong discloses All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min.
Tong et al process inherently disclose without strain relaxation (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min)
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II
Regarding claim 20. Zhao et al, Pal et al and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Pal et al further comprising removing (FIG. 2b, item 264 is removed) the first dielectric layer (FIG. 2a, item 264) from over the tops of the dummy gate structures (FIG. 2b, item 262) after partially removing ([0040]-[0041]) the second dielectric layer (FIG. 2a, item 220) and exposing the first dielectric layer (FIG. 2a, item 264).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004) as applied to claim 14 above, and further in view of Peng et al (U.S. 2014/0231919)
Regarding claim 19. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Zhao et al disclose the FCVD process ([0041], i.e. an FCVD process) performed at a temperature between about 300 and 1200 (The temperature of the densify HARP may be in a range of approximately 400° C.˜450° C).
Tong et al (‘2004) discloses the hardening of the second dielectric layer of the dielectric structures is performed at a temperature less than about 100 °C for about 3 seconds to about 120 seconds. (Tong, Page 2762, Second Column, second paragraph, After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min).
Zhao et al, Pal et al, and Tong et al (‘2004) fails to explicitly disclose wherein: the FCVD process includes an annealing performed at a period of about 2 hours to 10 hours; and
However, Peng et al teaches wherein: the FCVD process includes an annealing performed at a period of about 2 hours to 10 hours ([0014], i.e. The anneal step may be performed for a period of time between about 30 minutes and about 120 minutes). .
Since Zhao et al, Pal et al, Tong et al (‘2005) and Peng et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming dielectric structures of a semiconductor device as disclosed to modify Since Zhao et al, Pal et al, and Tong et al (‘2005) with the teachings of wherein: the FCVD process includes an annealing performed at a period of about 2 hours to 10 hours as disclosed by Peng et al. The use of an anneal step (represented by arrows 37) is performed on wafer, Dielectric material is solidified as a result of the anneal.. the anneal is performed at a temperature between about 5000C and about 1,2000C, and the anneal step may be performed for a period of time between about 30 minutes and about 120 minutes in Peng et al provides for dielectric material is solidified as a result of the anneal (Peng et al, [0014]).
Response to Arguments
Regarding 102/103 rejection.
On page 14 of applicant’s remarks, applicant appears to argue with respect to claim 1, that Zhao et and Pal fails to disclose wherein the forming of the first dielectric layer includes a deposition step and an annealing step.
Examiner respectfully disagree with applicant’s asserting. Examiner respectfully points out that Zhao et discloses this limitation. Applicant has not claimed any specific deposition step and an annealing step that distinguishes from the prior art of Zhao et al.
On pages 15-16 of applicant’s remarks, applicant appears to argue that Zhao in view of Pal fails to disclose at least “after the forming of the first dielectric layer including the deposition step and the annealing step and before performing a chemical mechanical planarization (CMP) process on the first dielectric layer, hardening a portion of the first dielectric layer” in claim 1.
Examiner respectfully disagrees with applicant’s assertion. Examiner respectfully points out that Zhao in view of Doyle discloses applicant’s claim language as explained in the rejection above.
On page 17 of applicant’s remarks, applicant appears to argue that Zhao et view of Pal and Tong fails to disclose at least “after performing the FCVD process and before performing a chemical mechanical planarization (CMP) process on the first dielectric layer of the dielectric structure, treating the first dielectric layer of the dielectric structure with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer” in claim 10. Applicant further argues that each reference as a whole must teach applicant’s claim 10
Examiner respectfully disagrees with applicant’s assertion. Examiner respectfully points out that Zhao et al discloses after performing the FCVD process and before performing a chemical mechanical planarization (CMP) process on the first dielectric layer of the dielectric structure, treating the first dielectric layer of the dielectric structure with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer. Pal et al teaches treating the first dielectric layer of the dielectric structure resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer. Tong et al teaches an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 19 of applicant’s remarks, applicant appears to argues that the discrete elements i.e. manner, time are addressed, then the treating step of claim 10 had not be met.
Examiner respectfully points out that applicant has not claimed a manner or time discrete element of the treating step. Examiner respectfully points out that all the elements of applicant’s claim 10 was rejected under Zhao et al, Pal et al, and Tong et al.
On page 20 of applicant’s remarks, applicant appears to argue that the prior art has no teaching, suggestion to combine the prior art.
In response to applicant’s argument that there is no teaching, suggestion, or motivation to combine the references, the examiner recognizes that obviousness may be established by combining or modifying the teachings of the prior art to produce the claimed invention where there is some teaching, suggestion, or motivation to do so found either in the references themselves or in the knowledge generally available to one of ordinary skill in the art. See In re Fine, 837 F.2d 1071, 5 USPQ2d 1596 (Fed. Cir. 1988), In re Jones, 958 F.2d 347, 21 USPQ2d 1941 (Fed. Cir. 1992), and KSR International Co. v. Teleflex, Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007). In this case, Since Zhao et al, Pal et al, and Tong et al disclose silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention.
On page 21 of applicant’s remarks, applicant appears to be arguing impermissible hindsight. In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
On page 22 of applicant’s remarks, applicant appears to be arguing that claims 14-20 are allowable for the same analogous reasons as above.
Examiner respectfully disagrees and points out that claims 14-20 are rejected for the same analogous reasons as above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/S.E.B./ Examiner, Art Unit 2815 /JOSHUA BENITEZ ROSARIO/Supervisory Patent Examiner, Art Unit 2815
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