DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Species II: Figs. 3 and 4A-4G in the reply filed on November 11, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Information Disclosure Statement
The information disclosure statement filed August 3, 2023 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
No copy of Foreign application CN201459124 Shuzhi Dai
No copy of Non-patent literature Das, A., Sperlich, H.-P., & Heidemeyer, H. (2007). Optimizing the interface of spin-on oxide and the active area of transistor in sub70nm dram structures for better electrical performance. ECS Meeting Abstracts, MA2007-01 (14), 653-653. https://doi .org/ 10.1149/ma2007-01/14/653 (Year: 2007)
No copy of Non-Patent Literature Tong, Q.-Y., Gan, Q., Fountain, G., Hudson, G., & Enquist, P. (2004). Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching. Applied Physics Letters, 85(14), 2762-2764. https://doi.org/10.1063/1.1800275 (Year: 2004) supplied
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Regarding claim 1. Claim 1 recites the limitation “receiving a workpiece comprising: a substrate, an active region disposed over the substrate and extending lengthwise along a first direction, and a dummy gate structure disposed over the active region and the substrate and extending along a second direction perpendicular to the first direction” in the claim language. The claim language lacks antecedent support in Applicant’s original filed specification for this claim language.
Regarding claim 10. Claim 10 recites the limitation “receiving a workpiece comprising: a substrate, an active region disposed over the substrate and extending lengthwise along a first direction, and a dummy gate structure disposed over the active region and the substrate and extending along a second direction perpendicular to the first direction” in the claim language. The claim language lacks antecedent support in Applicant’s original filed specification for this claim language.
Regarding claim 14. Claim 14 recites the limitation “forming a first dielectric layer of the dielectric structures in trenches between dummy gate structures disposed over a substrate, wherein the first dielectric layer is formed over the substrate, sidewalls of the dummy gate structures, and tops of the dummy gate structures; performing a flowable chemical vapor deposition (FCVD) process to form a second dielectric layer of the dielectric structures over the first dielectric layer and filling the trenches between the dummy gate structures, the first dielectric layer containing silicon and oxygen; after performing the FCVD process and before performing a chemical mechanical planarization (CMP) process on the second dielectric layer, hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form, a hardened portion of the second dielectric layer over a non-hardened portion of the second dielectric layer; depositing a third second dielectric layer over the hardened portion of the second dielectric layer of the dielectric structures; and performing the CMP a chemical mechanical planarization (CMP) process to completely remove the third second dielectric layer and partially remove the second dielectric layer” in the claim language. The claim language lacks antecedent support in Applicant’s original filed specification for this claim language.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claims 10-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claims 10 and 14. Claim 10 recites the limitation “an oxide liner of the isolation structure” in the third paragraph of the claim language.
Applicant does not have support in the originally filed specifications that the oxide liner is encompassed in the isolation structure. Applicant’s originally filed specifications in [0028] states, the substrate 202, the fins 204, and the isolation structure 206 may be similar to the substrate 102, the fins 106, and the dielectric layer 114 in FIG. 2G
Applicant’s does not have support in the originally filed specifications that the oxide liner is part of the isolation structure, i.e. the dielectric layer 114.
Claim 14 is rejected for the same analogous reasons as claim 10 above.
Claims 11-13, 15-20 are rejected for dependence upon a 112(a) rejected instance claim.
Regarding claims 12. Claim 12 recites the limitation “the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process; and the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer with a second hardness that is higher than the first hardness, wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process” in the claim language.
Applicant does not written support in the originally filed specifications for the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process, a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process.
Regarding claims 15 and 18. Claim 15 recites the limitation “further comprising tuning parameters of the hardening of the second dielectric layer of the dielectric structures with the aqueous oxidizer to provide the hardened portion of the second dielectric layer with a hardness that reduces scratch defects during the CMP process” in the claim language. Applicant does not have a written support in the originally filed specifications for further comprising tuning parameters of the hardening of the second dielectric layer of the dielectric structures with the aqueous oxidizer to provide the hardened portion of the second dielectric layer with a hardness that reduces scratch defects during the CMP process.
Claim 18 are rejected for the same analogous reasons as claim 15 above.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1. Claim 1 recites the limitation "the hardening of the first dielectric layer" in line 14 of claim 1. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-9 are rejected for dependence on claim 1.
Regarding claim 1. Claim 1 recites the limitation "the hardened portion of the first dielectric layer" in line 15 of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claims 2-9 are rejected for dependence on claim 1.
Regarding claims 10, 12 and 14. Claim 10 recites the limitation “performing a flowable chemical vapor deposition (FCVD) process” in the claim language.
It is unclear to the examiner as to what procedures are encompassed in the process of performing a flowable chemical vapor deposition (FCVD) process.
Claim 11 is rejected for the same analogous reason as claim 10 above.
Claim 14 is rejected for the same analogous reason as claim 10 above.
Claims 11-13, and 15-20 are rejected for dependence upon a 112(b) rejected instance claim.
Regarding claims 12. Claim 12 recites the limitation “the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process; and the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer with a second hardness that is higher than the first hardness, wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process.” in the claim language.
It is unclear how the first dielectric layer has a first hardness after the FCVD process that corresponds with a first amount of scratch defects during the CMP process when the untreated first dielectric has a first amount of defects during the CMP process when the untreated first dielectric is not touched by the chemical mechanical planarization process.
Regarding claims 15, and 18. Claim 15 recites the limitation “further comprising tuning parameters of the hardening of the second dielectric layer of the dielectric structures with the aqueous oxidizer to provide the hardened portion of the second dielectric layer with a hardness that reduces scratch defects during the CMP process” in the claim language. It is unclear to the examiner as to what is encompassed by the limitation comprising tuning parameters of the hardening of the portion of the first dielectric layer. Applicant’s disclosure does not disclose tuning parameters nor what those tuning parameters are.
Claim 18 is rejected for the same analogous reasons as claim 15 above.
Regarding claim 20. Claim 20 recites the limitation "the tops of the tops" in the second line of the claim language. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773).
Regarding claim 1. Zhao et al discloses a (method FIG. 2-8) comprising:
receiving a workpiece (FIG. 2) comprising:
a substrate (FIG. 2, item 200)
an active region ([0014]) disposed over the substrate (FIG. 2, item 200) and extending lengthwise along a first direction (FIG. 2, into the page), and
a dummy gate structure (FIG. 2, item 201) disposed over the active region ([0014]) and the substrate (FIG. 2, item 200) and extending along a second direction (FIG. 2, left to right) perpendicular (FIG. 2, into the page is perpendicular to left to right) to the first direction (FIG. 2, into the page);
depositing an etch stop layer (ESL) (FIG. 2, item 203) over the workpiece (FIG. 2),
forming a first dielectric layer (FIG. 3, item 204) over the ESL (FIG. 2, item 203) wherein the forming of the first dielectric layer (FIG. 3, item 204) includes a deposition step ([0041], i.e. an FCVD process) and an annealing step ([0042]);
after the forming of the first dielectric layer (FIG. 3, item 204) including the deposition step ([0041], i.e. an FCVD process) and the annealing step ([0042]) and before performing a chemical mechanical planarization (CMP) process (FIG. 5-7, [0062]-[0063]) on the first dielectric layer (FIG. 3, item 204), hardening([0043]) a portion of the first dielectric layer (FIG. 3, items 204), wherein a hardened portion ([0043]) of the first dielectric layer (FIG. 3, items 204) has a first hardness ([0043]);
after the hardening ([0043]) of the first dielectric layer (FIG. 3, items 204), depositing a second dielectric layer (FIG. 4, items 205) over the hardened portion ([0043]) of the first dielectric layer (FIG. 4, items 204),
wherein the second dielectric layer (FIG. 4, items 205) has a second hardness ([0050], i.e. process may include TEOS) higher (([0078], i.e. the density of the second dielectric layer may be greater to the density of the first dielectric) than the first hardness ([0043]) of the hardened portion ([0043]) of the first dielectric layer (FIG. 3, items 204);
(The prior art discloses the same materials, same flowable properties and same annealing range of the first dielectric layer as what disclosed by Applicant. The prior art discloses the same materials of the second dielectric layer as what disclosed by Applicant. Specifically, Applicant discloses in [0030] of specification materials suitable for the second dielectric layer 118 include tetraethylorthosilicate oxide. See applicant’s disclosure [0012]-[0014], [0023], and [0030]).
The prior art discloses the same materials, same flowable properties and same annealing range of as Applicant.
As such, applicant’s claimed wherein the second dielectric layer has a second hardness higher than the first hardness of the hardened portion of the first dielectric layer is inherent in the materials and the process used as in the Peng et al.
“[T]he discovery of a previously unappreciated property of a prior art composition, or of a scientific explanation for the prior art’s functioning, does not render the old composition patentably new to the discoverer.” Atlas Powder Co. v. Ireco Inc., 190 F.3d 1342, 1347, 51 USPQ2d 1943, 1947 (Fed. Cir. 1999). Thus the claiming of a new use, new function or unknown property which is inherently present in the prior art does not necessarily make the claim patentable. In re Best, 562 F.2d 1252, 1254, 195 USPQ 430, 433 (CCPA 1977). >In In re Crish, 393 F.3d 1253, 1258, 73 USPQ2d 1364, 1368 (Fed. Cir. 2004), the court held that the claimed promoter sequence obtained by sequencing a prior art plasmid that was not previously sequenced was anticipated by the prior art plasmid which necessarily possessed the same DNA sequence as the claimed oligonucleotides. The court stated that “just as the discovery of properties of a known material does not make it novel, the identification and characterization of a prior art material also does not make it novel.”
and performing the CMP process (FIG. 5-6; [0058]) to both the first dielectric layer (FIG. 5-7, item 204) and the second dielectric layer (FIG. 5-6, item 205) to completely remove (FIG. 5-6; [0058]) the second dielectric layer (FIG. 5-6, item 204) and partially remove (FIG. 5-7; [0058]) the hardened portion ([0043]) of the first dielectric layer (FIG. 7, item 204).
Zhao et al fails to explicitly disclose hardening a portion of the first dielectric layer.
However, Pal et al teaches
Hardening (FIG. 2i, item 207b; [0051]) a portion (FIG. 2i, item 227) of the first dielectric layer (FIG. 2i, item 220).
Since Zhao et al, and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Zhao et al with the teachings of hardening a portion of the first dielectric layer as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Regarding claim 9. Zhao et al, and Pal et al and discloses all the limitations of the method of claim 1 above.
Zhao et al further discloses further discloses wherein the hardened portion ([0043]) of the first dielectric layer (FIG. 3, items 204) extends below a top surface (FIG. 3, items 211) of the dummy gate structure (FIG. 3, items 201).
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Pal et al (U.S. 2013/0115773) as applied to claim 1 above, and further in view of Datta et al (U.S. 2005/0245036)
Regarding claim 2. Zhao et al, and Pal et al and discloses all the limitations of the method of claim 1 above.
Zhao et al further discloses
wherein the dummy gate structure (FIG. 3, item 201) comprises:
an oxide layer (FIG. 3, item 210) disposed on the active region ([0014]);
a dummy electrode layer (FIG. 3, item 211) disposed over the oxide layer (FIG. 3, items 210 and 212);
wherein the hardened portion ([0043]) of the first dielectric layer (FIG. 3, item 204) is disposed above ([0038]) the dummy electrode layer (FIG. 3, item 211) of the dummy gate structure (FIG. 3, item 201).
Pal et al discloses
a hard mask layer (FIG. 2g, item 264) over the dummy electrode layer (FIG. 2g, item 262); and
Zhao et al and Pal et al fail to explicitly disclose
a capping layer over the hard mask layer,
Datta et al teaches a capping layer over (FIG. 1A, item 132; [0015]) Etch stop layers 132, 133 may, for example, be made from an oxide (e.g., silicon dioxide)) the hard mask layer (FIG. 1A, item 130).
Since Zhao et al, Pal et all and Datta et al teach dummy structures, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al and Pal et al with the teachings of a capping layer over the hard mask layer as disclosed by Datta et al. The use of etch stop layers made from an oxide (e.g., silicon dioxide) in Datta et al provides for a material that will be removed at a substantially slower rate than silicon nitride will be removed when an appropriate etch process is applied (Datta et al, [0015]).
Regarding claim 3. Zhao et al, Pal et al, and Datta et al discloses all the limitations of the method of claim 2 above.
Zhao et al further wherein, after the depositing of the ESL (FIG. 2, item 203), the ESL (FIG. 2, item 203) is in direct contact with the oxide layer (FIG. 2, item 212), the dummy electrode layer (FIG. 2, item 211),
Pal et al discloses the ESL (FIG. 2g, item 263) is in direct contact with the hard mask layer (FIG. 2g, item 264), and
Datta et al disclose the ESL (FIG. 1B, item 134) is in direct contact ([0018]) with the oxide layer (FIG. 1B, item 105), the dummy electrode layer (FIG. 1B, item 104), the hard mask layer (FIG. 1B, item 130), and the capping layer (FIG. 1B, item 132).
Regarding claim 4. Zhao et al, Pal et al, and Datta et al discloses all the limitations of the method of claim 2 above.
Zhao et al further discloses wherein:
the dummy electrode (FIG. 3, item 211) layer comprises polysilicon ([0027], i.e. gate electrode layer 211 is made of poly silicon);
Pal et al discloses the hard mask layer (FIG. 2g, item 264) comprises silicon nitride ([0039], i.e. cap layer system 264 may comprise a silicon nitride material); and
Datta et al discloses the capping layer (FIG. 1A, item 132) comprises silicon oxide ([0015], i.e. layers 132, 133 may, for example, be made from an oxide (e.g., silicon dioxide)).
Claims 5 – 7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Pal et al (U.S. 2013/0115773) as applied to claim 1 above, and further in view of Nishimura et al (U.S. 6,776,691).
Regarding claim 5. Zhao et al, and Pal et al discloses all the limitations of the method of claim 1 above.
Zhao et al discloses hardening of the first dielectric layer ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal)
Zhao et al and Pal et al fails to explicitly disclose comprises treating the first dielectric layer with a fluorine-containing oxidizer (DHF), and after the treating of the first dielectric layer with the fluorine-containing oxidizer (DHF), treating the first dielectric layer with deionized water (DIW).
However, Nishimura et al teaches comprises treating the first dielectric layer with a fluorine-containing oxidizer (DHF), and after the treating of the first dielectric layer with the fluorine-containing oxidizer (DHF), treating the first dielectric layer with deionized water (DIW) (Col 10, lines 49-54, i.e. , the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature in order to remove further the natural oxide film and effect termination of the surface of the silicon wafer. Finally, the wafer is immersed in hot ultrapure water (HWP)).
Since Zhao et al, Pal and Nishimura et al teach a CMP process, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al and Pal et al with the teachings of comprises treating the first dielectric layer with a fluorine-containing oxidizer (DHF), and after the treating of the first dielectric layer with the fluorine-containing oxidizer (DHF), treating the first dielectric layer with deionized water (DIW) as disclosed by Nishimura et al. The use of the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature in order to remove further the natural oxide film and effect termination of the surface of the silicon wafer. Finally, the wafer is immersed in hot ultrapure water (HWP) in Nishimura et al provides for a polishing method that can remove potassium and other alkali metals without using a high concentration chemical agent typically containing sulfuric acid and also a method of preparing a wiring section (Nishimura et al, [Col 2, lines 13-18]).
Regarding claim 6. Zhao et al, Pal et al and Nishimura et al discloses all the limitations of the method of claim 5 above.
Nishimura et al further discloses wherein the treating of the first dielectric layer is performed at a temperature ranging from 15 0C to 90 0C, the fluorine-containing oxidizer is dilute hydrofluoric acid (DHF) and a concentration of hydrofluoric acid in the fluorine-containing oxidizer ranges from 0.005% to 0.1% (Col 10, lines 49-54, i.e. the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature)
Regarding claim 7. Zhao et al, Pal et al and Nishimura et al discloses all the limitations of the method of claim 5 above.
Nishimura et al further discloses wherein the treating of the first dielectric layer is performed at room temperature (Col 10, lines 49-54, i.e. the wafer is cleansed with 0.1 wt % dilute hydrofluoric acid (DHF) at room temperature)
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611) and Pal et al (U.S. 2013/0115773) as applied to claim 1 above, and further in view of Wang et al (U.S. 2006/0252267).
Regarding claim 8. Zhao et al and Pal et al discloses all the limitations of claim 1 above.
Zhao et al disclose wherein the CMP process uses a slurry ([0016]).
Pal et al disclose wherein the CMP process uses a slurry ([0040]).
Zhao et al and Pal et al fails to explicitly disclose uses a cerium oxide (CeO2) based slurry.
However, Wang et al teaches uses a cerium oxide (CeO2) ([0028], i.e. Both the undiluted and diluted slurry can include a ceria-based abrasive, such as a CeO2 ).
Since Zhao et al, Pal et al, and Wang et al teach a CMP process, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al and Pal et al with the teachings of uses a cerium oxide (CeO2) based slurry as disclosed by Wang et al. The use of the undiluted and diluted slurry can include a ceria-based abrasive, such as a CeO2 in Wang et al provides for a multi-step CMP process wherein a relatively high force, low topology selectivity CMP process is performed first to remove protrusions, and then a relatively low force, high topology selectivity CMP process is performed (Wang et al, [0021]).
Claims 10, 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004)
Regarding claim 10. Zhao et al discloses a method (FIG. 2-8), comprising:
forming a dummy gate structure (FIG. 2, item 201) over a substrate (FIG. 2, item 200);
forming a dielectric structure (FIG. 7, item 204) adjacent sidewalls of the dummy gate structure (FIG. 7, item 201), wherein the forming of the dielectric structure (FIG. 7, item 204) includes:
performing a flowable chemical vapor deposition (FCVD) process ([0041], i.e. an FCVD process) to form a first dielectric layer (FIG. 3, items 204) of the dielectric structure (FIG. 7, item 204) over and adjacent to the sidewalls of the dummy gate structure (FIG. 2, items 201), wherein the first dielectric layer (FIG. 3, items 204) contains silicon and oxygen ([0042], i.e. the first dielectric layer 204 is made of silicon oxide) and the first dielectric layer (FIG. 3, items 204) has having a first content of silicon-oxygen bonds ([0042], i.e. made of silicon oxide),
after performing the FCVD process ([0041], i.e. an FCVD process) and before performing a chemical mechanical planarization (CMP) process ([0051], i.e. after forming the second dielectric layer 205, a first polishing process may be performed (S104)) on the first dielectric layer (FIG. 3, items 204) of the dielectric structure (FIG. 7, items 204), treating ([0043]) the first dielectric layer (FIG. 3, items 204) of the dielectric structure (FIG. 7, items 204), resulting in a treated portion of the first dielectric layer ([0007], i.e. a densified first dielectric layer with an increased hardness formed on the surface of the stop layer by a densify high aspect ratio process)
depositing a second dielectric layer (FIG. 4, item 205) over the treated portion of the first dielectric layer (FIG. 4, item 204), and
performing the CMP (FIG. 5-7, [0062]-[0063]) to completely remove the second dielectric layer FIG. 7, shows item 205 completely removed) and partially remove the treated portion ([0043]) of the first dielectric layer (FIG. 7 shows item 204 partially removed); and
after forming the dielectric structure (FIG. 7, item 204) adjacent sidewalls of the dummy gate structure (FIG. 7, item 201), replacing the dummy gate structure (FIG. 7, item 201) with a metal gate structure (FIG. 8, item 207)
Zhao et al fails to explicitly disclose treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer, wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds.
Pal et al teaches
Treating (FIG. 2i, item 207b; [0051]) the first dielectric layer (FIG. 2i, item 220), resulting in a treated portion (FIG. 2i, item 227) of the first dielectric layer (FIG. 2i, item 220) above an untreated portion (FIG. 2i, item 222) of the first dielectric layer (FIG. 2i, item 220)
Since Zhao et al, and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Zhao et al with the teachings of treating the first dielectric layer resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Zhao et al and Pal et al fails to explicitly disclose treating the first dielectric layer with an aqueous oxidizer, wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds.
However, Tong et al teaches treating the first dielectric layer with an aqueous oxidizer (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature), wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface).
Since Zhao et al, Pal et al, and Tong et al disclose silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Zhao et al and Pal et al with the teachings of treating the first dielectric layer with an aqueous oxidizer, wherein the treated portion of the first dielectric layer has a second content of silicon-oxygen bonds greater than the first content of silicon-oxygen bonds as disclosed by Tong et al. The use of the after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
Regarding claim 12. Zhao et al, Pal et al, and Tong et al discloses all the limitations of the method of claim 10 above.
Zhao et al discloses the first dielectric layer (FIG. 3, item 204) has a first hardness after (FIG. 3 is after FIG. 2) the FCVD process (FIG. 3, item 204; [0041], i.e. an FCVD process) that corresponds with a first amount of scratch defects during the CMP process (FIG. 5-7; [0057]-[0058], [0062]-[0064]) (as best understood by the 112(b) above. [0041], i.e. an FCVD process, examiner makes notes that a first amount of scratch defect during the CMP process since applicant has only claimed a FCVD process without claiming any actual process steps in the FCVD process);
Tong et al discloses the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer (Tong, Page 2762, Second Column, second paragraph) with a second hardness wherein the second hardness corresponds with a second amount of scratch defects during the CMP process (Examiner makes note that since applicant states the aqueous oxidizer provides the second hardness, Tong treated first dielectric by the aqueous oxidizer inherently provides the second hardness)
Since Zhao et al discloses the FCVD process(FIG. 3, item 204; [0041], i.e. an FCVD process) that corresponds with a first amount of scratch defects during the CMP process (FIG. 5-7; [0057]-[0058], [0062]-[0064]),
And Tong et al discloses the treating the first dielectric layer with the aqueous oxidizer provides the treated portion of the first dielectric layer (Tong, Page 2762, Second Column, second paragraph) that is higher than the first hardness (FIG. 4, item 36),
Zhao et al in combination with Tong et al inherently discloses wherein the second hardness corresponds with a second amount of scratch defects during the CMP process that is less than the first amount of scratch defects during the CMP process.
Since Zhao, Pal et al, and Tong et al disclose silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Peng et al, Lou, Pal et al and Wang et al with the teachings of treating the first dielectric layer with an aqueous oxidizer, resulting in a treated portion of the first dielectric layer above an untreated portion of the first dielectric layer as disclosed by Tong et al. The use of the after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II
Regarding claim 13. Zhao et al, Pal et al, and Tong et al discloses all the limitations of the method of claim 10 above.
Tong et al further discloses wherein the aqueous oxidizer includes deionized water (DIW), dilute hydrofluoric acid (DHF) or both (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min. Without DI water rinsing after DHF dip, the wafers were spin dried and bonded spontaneously in air at room temperature).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004) as applied to claim 10 above, and further in view of Datta et al (2005/0245036).
Regarding claim 11. Zhao et al, Pal et al, and Tong et al discloses all the limitations of the method of claim 10 above.
Zhao et al further discloses
wherein the dummy gate structure (FIG. 3, item 201) comprises:
an oxide layer (FIG. 3, item 210) disposed on the substrate (FIG. 3, item 200);
a dummy electrode layer (FIG. 3, item 211) disposed over the oxide layer (FIG. 3, items 210 and 212);
wherein the hardened portion ([0043]) of the first dielectric layer (FIG. 3, item 204) is disposed above ([0038]) the dummy electrode layer (FIG. 3, item 211) of the dummy gate structure (FIG. 3, item 201).
Pal et al discloses
a hard mask layer (FIG. 2g, item 264) over the dummy electrode layer (FIG. 2g, item 262); and
wherein the treated portion (FIG. 2i, item 227) of the first dielectric layer (FIG. 2i, item 220) is disposed above a top (FIG. 2i, item 264) of the dummy electrode layer (FIG. 2i, item 262) of the dummy gate structure ([0039]) and the CMP process (FIG. 2j, item 208) removes ([0053]) the treated portion (FIG. 2j, item 227)of the first dielectric layer (FIG. 2j, item 220)
Zhao et al and Pal et al fail to explicitly disclose
a capping layer over the hard mask layer,
Datta et al teaches a capping layer over (FIG. 1A, item 132; [0015]) Etch stop layers 132, 133 may, for example, be made from an oxide (e.g., silicon dioxide)) the hard mask layer (FIG. 1A, item 130).
Since Zhao et al, Pal et all, and Tong et al and Datta et al teach silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method as disclosed to modify Zhao et al and Pal et al with the teachings of a capping layer over the hard mask layer as disclosed by Datta et al. The use of etch stop layers made from an oxide (e.g., silicon dioxide) in Datta et al provides for a material that will be removed at a substantially slower rate than silicon nitride will be removed when an appropriate etch process is applied (Datta et al, [0015]).
Claims 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004).
Regarding claim 14. Zhao et al discloses a method of forming dielectric structures (FIG. 8, items 203 and 204) of a semiconductor device (FIG. 8), the method comprising:
forming a first dielectric layer (FIG. 2, items 203) of the dielectric structures (FIG. 8, items 203 and 204) in trenches (FIG. 2, items 202) between dummy gate structures (FIG. 2, items 201) disposed over a substrate (FIG. 2, items 200), wherein the first dielectric layer (FIG. 2, items 203) is formed ([0022]) over the substrate (FIG. 2, items 200), sidewalls (FIG. 2, items 212) of the dummy gate structures (FIG. 2, items 201), and tops (FIG. 2, items 211) of the dummy gate structures (FIG. 2, items 201);
performing a flowable chemical vapor deposition (FCVD) process ([0041], i.e. an FCVD process) to form a second dielectric layer (FIG. 3, items 204) of the dielectric structures (FIG. 8, items 203 and 204) over the first dielectric layer (FIG. 3, items 203) and filling the trenches (FIG. 2, items 202) between the dummy gate structures (FIG. 3, items 201), the first dielectric layer containing silicon and oxygen ([0042], i.e. the first dielectric layer 204 is made of silicon oxide);
after performing the FCVD process ([0041], i.e. an FCVD process) and before performing a chemical mechanical planarization (CMP) process ([0051], i.e. after forming the second dielectric layer 205, a first polishing process may be performed (S104)) on the second dielectric layer (FIG. 3, items 204), hardening ([0043]) the second dielectric layer (FIG. 3, items 204) of the dielectric structures (FIG. 8, items 203 and 204) to form a hardened portion ([0043]) of the second dielectric layer (FIG. 3, items 204).
depositing a third second dielectric layer (FIG. 4, item 205) over the hardened portion ([0043]) of the second dielectric layer (FIG. 4, item 204) of the dielectric structures (FIG. 8, items 203 and 204); and
performing the CMP (FIG. 5-7, [0062]-[0063]) to completely remove the third dielectric layer (FIG. 7, shows item 205 completely removed) and partially remove the second dielectric layer (FIG. 6 shows item 204 partially removed)
Zhao et al fails to explicitly disclose hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form a hardened portion of the second dielectric layer over a non-hardened portion of the second dielectric layer
However, Pal et al teaches hardening (FIG. 2i, item 207b; [0051]) the second dielectric layer (FIG. 2i, item 220) of the dielectric structures (FIG. 2j, item 220) to form a hardened portion (FIG. 2i, item 227) of the second dielectric layer (FIG. 2i, item 220) over a non-hardened portion (FIG. 2i, item 222) of the second dielectric layer (FIG. 2i, item 220)
Since Zhao et al, and Pal et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the a method of forming a semiconductor device as disclosed to modify Zhao et al with the teachings of hardening the second dielectric layer of the dielectric structures to form a hardened portion of the second dielectric layer over a non-hardened portion of the second dielectric layer as disclosed by Pal et al. The use of a process sequence including a planarization process and a surface modification process is repeated at least once upon performing a replacement gate approach in Pal et al provides for increasing flexibility and enhancing overall process conditions (Pal et al, [0051]).
Zhao et al and Pal et al fails to explicitly disclose hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form a hardened portion of the second dielectric layer
However,
Tong et al (‘2004) teaches hardening the second dielectric layer with aqueous oxidizer (Tong, Page 2762, Second Column, second paragraph, i.e. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min) to form a hardened portion of the second dielectric layer (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface);
Since Zhao et al, Pal et al, and Tong et al (‘2004) teach silicon oxide covered wafers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming a semiconductor device as disclosed to modify Zhao et al and Pal et al with the teachings of the hardening the second dielectric layer of the dielectric structures with an aqueous oxidizer to form a hardened portion of the second dielectric layer as disclosed by Tong et al (‘2004). The use of the HF aqueous solution and the number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively after rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) in Tong et al provides for Achieving a strong bond at low temperatures is critical for bonding of thermally mismatched or thermally sensitive wafers including processed device wafers (Tong et al, Page 2762, first column, second paragraph).
Regarding claim 15. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Tong et al (‘2004) further comprising tuning parameters of the hardening of the second dielectric layer of the dielectric structures with the aqueous oxidizer to provide the hardened portion of the second dielectric layer with a hardness (Tong, Page 2762, Second Column, second paragraph, i.e. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) that reduces scratch defects during the CMP process (Tong et al, Page 2764, Second Column, last paragraph, i.e. The number of Si–O–Si covalent bonds at the bonding interface appears to be significantly increased by the formation of fluorinated silicon oxide (SiOF) that absorbs water effectively which is the by-product of the polymerization reaction at the bonding interface).
Regarding claim 16. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Zhao et al further discloses wherein the first dielectric layer (FIG. 2, items 203) abuts the sidewalls ([0022]) and the tops ([0022]) of the dummy gate structures (FIG. 2, items 201).
Regarding claim 17. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Tong et al (‘2004) wherein the hardening of the second dielectric layer with the aqueous oxidizer comprises a treating process with deionized water (DIW) and a treating process with dilute hydrofluoric acid (DHF), or both (Tong, Page 2762, Second Column, second paragraph, i.e. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min).
Regarding claim 18. Zhao et al, Pal et al and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Tong et al (‘2004) further discloses further comprising tuning parameters of the hardening of the first dielectric layer of the isolation structures with the aqueous oxidizer to provide the hardened portion of the first dielectric layer without strain relaxation (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min).
Applicant’s specifications at [0026] states Particularly, the operation 16 is performed at a temperature below 100° C., which is consistent with certain wet bench manufacturing flows when the oxidizer 116 is aqueous. For example, the operation 16 may be performed at a temperature ranging from 15° C. to 90° C., such as at room temperature of about 25° C. Notably, such temperature is much lower than typical temperatures used for annealing the dielectric layer 114 in the operation 14. Accordingly, the operation 16 does not lead to the strain relaxation issue discussed above.
Tong discloses All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min.
Tong et al process inherently disclose without strain relaxation (Tong, Page 2762, Second Column, second paragraph, i.e. All wafers were cleaned in standard RCA1 solution for 15 min at 70–80°C. After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min)
"Products of identical chemical composition cannot have mutually exclusive properties." In re Spada, 911 F.2d 705, 709, 15 USPQ2d 1655, 1658 (Fed. Cir. 1990). A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties applicant discloses and/or claims are necessarily present. Id. (Applicant argued that the claimed composition was a pressure sensitive adhesive containing a tacky polymer while the product of the reference was hard and abrasion resistant. "The Board correctly found that the virtual identity of monomers and procedures sufficed to support a prima facie case of unpatentability of Spada’s polymer latexes for lack of novelty.") MPEP 2112.01 II
Regarding claim 20. Zhao et al, Pal et al and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Pal et al further comprising removing (FIG. 2b, item 264 is removed) the first dielectric layer (FIG. 2a, item 264) from over the tops of the tops of the dummy gate structures (FIG. 2b, item 262) after partially removing ([0040]-[0041]) the second dielectric layer (FIG. 2a, item 220) and exposing the first dielectric layer (FIG. 2a, item 264)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al (U.S. 2015/0287611), Pal et al (U.S. 2013/0115773), and Tong et al (“Low-temperature bonding of silicon-oxide-covered wafers using diluted HF etching”, 2004) as applied to claim 14 above, and further in view of Peng et al (U.S. 2014/0231919)
Regarding claim 19. Zhao et al, Pal et al, and Tong et al (‘2004) discloses all the limitations of the method of claim 14 above.
Zhao et al disclose the FCVD process ([0041], i.e. an FCVD process).
Tong et al (‘2004) discloses the hardening of the second dielectric layer of the dielectric structures is performed at a temperature less than about 100 °C for about 3 seconds to about 120 seconds. (Tong, Page 2762, Second Column, second paragraph, After rinsing in de-ionized (DI) water, they were dipped in a diluted (0.02%–0.5%) HF aqueous solution (DHF) for 1–2 min).
Zhao et al, Pal et al, and Tong et al (‘2004) fails to explicitly disclose wherein: the FCVD process includes an annealing performed at a temperature between about 300 °C and about 1200 °C and a period of about 2 hours to 10 hours; and
However, Peng et al teaches wherein: the FCVD process includes an annealing performed at a temperature between about 300 °C and about 1200 °C ([0014], i.e. Referring to FIG. 5, an anneal step (represented by arrows 37) is performed on wafer 100. Dielectric material 36 is solidified as a result of the anneal.. the anneal is performed at a temperature between about 5000C and about 1,2000C) and a period of about 2 hours to 10 hours ([0014], i.e. The anneal step may be performed for a period of time between about 30 minutes and about 120 minutes). .
Since Zhao et al, Pal et al, Tong et al (‘2005) and Peng et al teach dielectric layers, it would have been obvious to one having ordinary skill in the art of semiconductors before the effective filing date of the claimed invention to have combined the method of forming dielectric structures of a semiconductor device as disclosed to modify Since Zhao et al, Pal et al, and Tong et al (‘2005) with the teachings of wherein: the FCVD process includes an annealing performed at a temperature between about 300 °C and about 1200 °C and a period of about 2 hours to 10 hours as disclosed by Peng et al. The use of an anneal step (represented by arrows 37) is performed on wafer, Dielectric material is solidified as a result of the anneal.. the anneal is performed at a temperature between about 5000C and about 1,2000C, and the anneal step may be performed for a period of time between about 30 minutes and about 120 minutes in Peng et al provides for dielectric material is solidified as a result of the anneal (Peng et al, [0014]).
Conclusion
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/JAY C KIM/Primary Examiner, Art Unit 2815
/S.E.B./ Examiner, Art Unit 2815