Detailed Action
This office action is in response to the amendment filed on April 20th, 2026. Claims 1, 4-5, 7-9, 11-17, and 20-26 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed April 20th, 2026, have been fully considered but they are not persuasive.
Applicant argues (pgs. 11-16, “Remarks”) that Sze and the other cited references fail to teach the limitations presented in amended Claims 1, 7 and 13.
However, as seen below, Claim 13 is now rejected by the combination of Sze, Kim, and Lim.
Therefore, applicant’s arguments are not persuasive and are moot in view of the new grounds of rejection.
Applicant’s arguments have overcome the 35 U.S.C. 112(b) rejections of the previous office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 7-9, 11-12, and 23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 recites the limitation "the side of the substrate" in lines 21-22. There is insufficient antecedent basis for this limitation in the claim. For the purpose of examination, the limitation will be interpreted as “a side of the substrate”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate that the corresponding limitations are addressed with a secondary reference/embodiment in an obviousness analysis.
Claims 13-14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Sze et al. (2020/0105812 A1; hereinafter Sze) in view of Kim et al. (2021/0335877 A1; hereinafter Kim) and Lim et al. (2020/0119072 A1; hereinafter Lim)
Regarding Claim 13, Sze (see fig. 16) teaches a method, comprising:
forming a deep trench isolation (DTI) structure ([0027]-[0028], 156, 158) in a substrate ([0022], 103), wherein the DTI structure extends from a topmost surface of the substrate to a bottommost surface of the substrate;
forming, in the substrate (103), a photodiode ([0021], 110) that does not extend beyond the DTI structure;
forming a first dielectric layer ([0029], 119, 120, see fig. 15) over (fig. 16 is rotated by 180 degrees when compared to the claimed invention, so 119 and 120 can be interpreted to be over the bottom surface of the substrate 103) the topmost surface (bottom surface of 103, see fig. 16) of the substrate (103); and
forming, in the first dielectric layer (119, 120) and between the DTI structure (156, 158), a plurality of conductive structures ([0056], 602);
forming an oxide layer over the bottommost surface of the substrate; forming a metal layer over the oxide layer; removing first portions of the oxide layer and first portions of the metal layer to form a grid structure comprising second portions of the oxide layer and second portions of the metal layer, wherein the second portions of the oxide layer and second portions of the metal layer are disposed over the DTI structure and laterally aligned with the DTI structure, and wherein the second portions of the oxide layer are between the bottommost surface of the substrate and the second portions of the metal layer; and forming a second dielectric layer over, different from the oxide layer and the metal layer, on a top surface, and sidewalls, of the grid structure.
Sze doesn’t teach a deep trench isolation (DTI) structure that extends from a topmost surface of the substrate to a bottommost surface of the substrate and that the photodiode does not extend beyond the DTI structure.
However, Kim (fig. 16) teaches a deep trench isolation (DTI) structure ([0057], 120) that extends from a top most surface of the substrate ([0168], 110b) to a bottom most surface of the substrate ([0168], 110a) and that the photodiode ([0168], PD) does not extend beyond the DTI structure ([0170], 120). Kim also teaches the DTI structure serves to separate the pixels ([0058]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the method of forming a DTI structure of Kim for the method of forming a DTI structure of Sze, since simple substitution of a method of forming a DTI structure for another is an appropriate rationale to support a rejection under 35 U.S.C. 103. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Sze doesn’t teach forming an oxide layer over the bottommost surface of the substrate; forming a metal layer over the oxide layer; removing first portions of the oxide layer and first portions of the metal layer to form a grid structure comprising second portions of the oxide layer and second portions of the metal layer, wherein the second portions of the oxide layer and second portions of the metal layer are disposed over the DTI structure and laterally aligned with the DTI structure, and wherein the second portions of the oxide layer are between the bottommost surface of the substrate and the second portions of the metal layer; and forming a second dielectric layer over, different from the oxide layer and the metal layer, on a top surface, and sidewalls, of the grid structure.
However, Lim (figs. 18-24) teaches forming an oxide layer ([0068], 33, 34, see fig. 21) over the bottommost surface of the substrate ([0064], top of 10, see fig. 23); forming a metal layer ([0070], 35, 36, see fig. 21) over the oxide layer (33, 34); removing first portions of the oxide layer (portion of 34 removed, see figs. 22-23) and first portions of the metal layer (portions of 35, 36 removed, see figs. 22-23) to form a grid structure ([0074], 40, see fig. 23) comprising second portions of a second oxide layer ([0039], [0068], 41, 33, see fig. 23) and second portions of a metal layer ([0040], 42, see fig. 23), wherein the second portions of the second oxide layer (41) and the second portions of the metal layer (42) are disposed over the DTI structure ([0064], 13, see fig. 19) and laterally aligned (see fig. 23) with the DTI structure (13), and wherein the second portions of the second oxide layer (41) are between the side of the substrate (top of 10) and the second portions of the metal layer (42); and forming a dielectric layer ([0077], 50, see fig. 23), different from the second oxide layer (41) and the metal layer (42), on a top surface, and sidewalls, of the grid structure (top and sidewalls of 40). Lim also teaches that the grid pattern may reflect incident light obliquely incident on the substrate, thereby causing more incident light to reach the photodiode and reducing or preventing crosstalk ([0029]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Sze to include the formation of a grid structure of Lim to reduce or prevent crosstalk.
Regarding Claim 14, Kim (fig. 8) teaches the method of claim 13, wherein the DTI structure (120) is at least partially tapered ([0150]) from top most surface of the substrate (110b) to the bottommost surface of the substrate (110a).
Regarding Claim 20, Sze (fig. 16) teaches the method of claim 15, further comprising: forming a color filter ([0026], 106) over the second dielectric layer ([0027], 160). Sze doesn’t teach forming a micro-lens layer over the color filter layer.
However, Kim (fig. 4) teaches forming a micro-lens layer ([0102], 180) over the color filter layer ([0100], 170). Kim also teaches the microlenses help concentrate incident light onto the photodiode ([0103]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Sze to include the microlens of Kim to help concentrate incident light.
Claims 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sze, Kim, and Lim as applied to Claim 13 above, and further in view of Kim et al. (2022/0173143 A1; hereinafter Kim2).
Regarding Claim 15, Sze doesn’t teach the method of claim 13, wherein forming the DTI structure in the substrate comprises: forming a first portion of the DTI structure in a first portion of the substrate; and forming a second portion of the DTI structure in a second portion of the substrate.
However, Kim2 (see figs. 5A-F), in a similar method, teaches forming the DTI structure ([0061]-[0063], 20, 30) in the substrate ([0077], 1) comprises: forming a first portion of the DTI structure (20) in a first portion of the substrate ([0053], the side of substrate 1 where 20 is formed, see fig. 5A); and forming a second portion of the DTI structure (30) in a second portion of the substrate ([0053], the side of substrate 1 where 30 is formed, see fig. 5D). Kim2 also teaches that a two portion DTI structure may reduce process defects and increase a thickness of the substrate ([0072]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Sze to include the DTI structure of Kim2 to reduce process defects.
Regarding Claim 16, Kim2 (see figs. 5A-F) teaches the method of claim 15, wherein the first portion of the DTI structure (20) is tapered in a first direction (see fig. 5F), and wherein the second portion of the DTI structure (30) is tapered in a second direction (see fig. 5F) opposite from the first direction.
Regarding Claim 17, Kim2 (see figs. 5A-F) teaches the method of claim 15, wherein the second portion of DTI structure (30) is formed after the first portion of the DTI structure (20), the photodiode ([0047], PD), and the plurality of conductive structures ([0060], 15, 17) are formed.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Sze, Kim, and Lim as applied to Claim 13 above, and further in view of Kobayashi (2012/0199883 A1; hereinafter Kobayashi).
Regarding Claim 21, Sze doesn’t teach the method of claim 13, wherein the photodiode comprises a p-type region and a plurality of n-type regions.
However, Kobayashi (fig. 5A) teaches that the photodiode ([0029], photoelectric conversion unit) comprises a p-type region ([0050], 107) and a plurality of n-type regions ([0084], 101, 501). Kobayashi also teaches that by having different N-type regions at different depths can increase sensitivity ([0088]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Sze to include the photodiode of Kobayashi to increase sensitivity.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Sze, Kim, and Lim as applied to Claim 13 above, and further in view of Mun et al. (10811453 B1; hereinafter Mun).
Regarding Claim 24, Sze doesn’t teach the method of claim 13, wherein after removing the first portions of the oxide layer and first portions of the metal layer, the second portions and third portions of the oxide layer remain, wherein the second portions of the oxide layer are a greater distance from the bottommost surface of the substrate than third portions of the oxide layer.
However, Mun (fig. 8D) teaches after removing the first portions of the oxide layer (Col. 10, Lines 27 and 66; portion of 28a removed for opening 812) and first portions of the metal layer (Col. 10, Line 66; 80 removed for opening 812), the second portions (portions of 28a under 80) and third portions of the oxide layer (portions of 28a under 24b) remain, wherein the second portions of the oxide layer (28a under 80) are a greater distance (see fig. 8D) from the bottommost surface of the substrate (Col. 6, Line 43; top of 50) than third portions of the oxide layer (28a under 24b). Mun also teaches that this structure allows the color filters to be embedded into the second oxide layer and that the height of the microlenses above may be controlled as needed (Col. 11, Lines 4-23).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the method of Sze to include second oxide layer structure of Mun to embed color filters and adjust microlens height.
Allowable Subject Matter
Claims 1, 4-5, 22, and 25-26 are allowed.
The following is an examiner’s statement of reasons for allowance. None of the cited references, either singly or in combination, teach or render obvious the limitations presented in Claim 1 wherein “forming, after forming the transfer gate, a first oxide layer over the transfer gate and the topmost surface of the substrate; connecting, after forming the first oxide layer, the transfer gate to a conductive structure of a plurality of conductive structures, wherein the plurality of conductive structures resides entirely above the first oxide layer; forming, after connecting the transfer gate to the conductive structure and over the bottommost surface of the substrate, a grid structure comprising portions of a second oxide layer and portions of a metal layer”.
Claim 7 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter. None of the cited references, either singly or in combination, teach or render obvious the limitations presented in Claim 7 wherein “forming, after forming the transfer gate, an oxide layer over the transfer gate and on a top surface of the substrate; connecting, after forming the oxide layer, the photodiode to a first conductive structure of a plurality of conductive structures, wherein the plurality of conductive structures resides entirely above the oxide layer; forming, after connecting the photodiode to the first conductive structure and over a side, a grid structure comprising portions of a second oxide layer and portions of a metal layer”.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADIN HRNJIC whose telephone number is (571)270-1794. The examiner can normally be reached Monday-Friday 8:00 AM - 4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/A.H./Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817