Prosecution Insights
Last updated: April 19, 2026
Application No. 18/364,964

CMOS Fabrication Methods for Back-Gate Transistor

Final Rejection §103
Filed
Aug 03, 2023
Examiner
HA, NATHAN W
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
2 (Final)
91%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
99%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1043 granted / 1144 resolved
+23.2% vs TC avg
Moderate +8% lift
Without
With
+7.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
10 currently pending
Career history
1154
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
43.5%
+3.5% vs TC avg
§102
34.8%
-5.2% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1144 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant's arguments regarding the election/restriction requirement of claims 1-20 in the reply filed on 12/15/25 is acknowledged. Again, this issue was addressed by the Examiner previously (see the office action issued on 8/12/25.) The Applicant was given an opportunity to elect a species and claims that are read on the species (See also the notice of non-compliance issued on 6/18/25.) For the purpose of examination and to expedite the process of prosecution, the office elected claims 16 and 20. Claims 16 and 20 were previously rejected and also address in the office action below. The requirement is still deemed proper and is therefore made FINAL. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Moriguchi et al. (US 2010/0295047, previously cited, hereinafter, Moriguchi) in view of FURUIE (US 2018/0151837, previously cited, hereinafter, Furuie) and CHOI et al. (US 2017/0229554, previously cited, hereinafter, Choi.) In regard to claims 16 and 20, in figs. 9 and 10, Moriguchi discloses a device comprising: a semiconductor substrate 1; a first work function layer 2 over the substrate, wherein the first work function layer is an n-type work function layer, n-type transistor, (para [0090]); a first low-dimensional semiconductor layer 4 (para [0089]) on a first top surface and a first sidewall of the first work function layer; first source/drain contacts 5a/5b (para [0091]) contacting opposing end portions of the first low-dimensional semiconductor layer; and a dielectric layer 8 over and contacting a channel portion of the first low- dimensional semiconductor layer. Moriguchi, however, does not clearly show a dielectric layer over the semiconductor substrate; an isolation layer over the dielectric layer. Furuie, in fig. 2, for example, discloses an analogous device including transistors (para [0030]) over a substrate 112 and dielectric layer 101 and isolation layer 113. The additional layers provide support, isolation and protection to the devices that formed on the substrate. It is common in the art. Therefore, it would be obvious to one of ordinary skill in the art at the time of the application was filed to form additional layers as taught in order to provide support, isolation and protection to the devices that formed on the substrate. The combination does not show, wherein the dielectric doping layer comprises a metal selected from aluminum and hafnium, and wherein the channel portion of the first low-dimensional semiconductor layer further comprises the metal. Choi, in fig. 9, discloses an analogous device including a dielectric layer and further teaches that aluminum oxide and hafnium oxide may be used (para [0058].) These materials are used to alter the dielectric constant of the dielectric layer. This is common in the art. Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to use the known materials as taught in order to improve the device’s property. Response to Arguments The Remarks of 12/15/25 have been fully considered. However, the rejection of claims 16 and 20 under 35 U.S.C. § 103 as unpatentable over Moriguchi in view of Furuie and Choi is determined to be proper and is, therefore, maintained (see the above rejection.) On page 9 of the remarks, applicant argues that the examiner has not established the obviousness of claim 16. The requirements for a proper response to a rejection may be found in 37 CFR 1.111(b) and MPEP § 707.07. The remarks do not provide any specific reasons as to why either the findings of fact or the legal conclusion of obviousness is allegedly in error. The legal decisions cited discuss various aspects of an obviousness analysis, but Applicant’s remarks are only generalizations not tied to the facts of the cases. Thus, the remarks in response to the obviousness rejection do not comply with 37 CFR 1.111(b) and MPEP § 707.07. However, Applicant’s reply is considered to be a bona fide attempt at a response and is being accepted as a complete response. The remarks, for example, the combination of Moriguchi and Furuie and Choi does not disclose the metal as claimed (remarks’ page 9.) Regarding the substance of the examiner’s obviousness rejection as argued on page 9 of the remarks, the requirements for obviousness are discussed in MPEP § 2142. As explained in the previous Office Action (and repeated above), the only difference between claims 16 and 20 and the teachings of Moriguchi and Furuie is the selection of additional layers and the well-known metal (claim 16 claims the metal is selected from aluminum and hafnium.) The Office action also explained that the combination of Moriguchi and Furuie teaches the dielectric layer without mentioning one of the metals that is formed by the metal as currently claimed, further limits as hafnium in claim 20. As previously stated, both Moriguchi and Furuie are directed to the dielectric that would have the same function on a substrate as currently claimed. Choi was incorporated therein with Moriguchi and Furuie to show the obviousness of the metal. In this case the metal may be either aluminum or hafnium. Furthermore, Choi teaches that by combining these high-K materials would further improve the connectivity and capacitance since the materials have higher dielectric constants (Choi’s para [0058].) Choi suggests several known materials, for example, hafnium oxide, hafnium oxynitride, aluminum oxide, aluminum oxide, etc. These materials are well-known to one of ordinary skill in the art. Thus, as explained in the previous Office action (also repeated above), one of ordinary skill in the art would reasonably have expected that by selecting one of the known materials, a composition would be obtained that was effective for a higher dielectric constant and capacitance. The rejection of claims 16 and 20 as obvious over Moriguchi and Furuie and Choi is, therefore, maintained. It is noted that there were several prior art documents were cited previously also show the use of the known material as mentioned above. For example, MINAMI (US 2023/0009509), Suzuki et al. (2022/0115629), FURUIE (US 2018/0151837), and Ellinger et al. (US 9,620,501.) Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NATHAN W HA/Primary Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Aug 03, 2023
Application Filed
Nov 11, 2024
Response after Non-Final Action
Aug 12, 2025
Non-Final Rejection — §103
Dec 15, 2025
Response Filed
Feb 13, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
91%
Grant Probability
99%
With Interview (+7.7%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 1144 resolved cases by this examiner. Grant probability derived from career allow rate.

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