DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on August 3, 2023, December 29, 2023 and February 2, 2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 10, 15 and 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The claimed limitation of "first word line", as recited in claim 2, is unclear as to whether said limitation is the same as or different from “a first word line”, as recited in claim 1.
The claimed limitation of "the first word line is … longer than the second word line", as recited in claim 10, is unclear as to which dimension of the first word line is longer than which dimension of the second word line applicant refers.
The claimed limitation of "the second word line is … shorter than the first word line", as recited in claim 15, is unclear as to which dimension of the second word line is shorter than which dimension of the first word line applicant refers.
The claimed limitation of "sidewalls of the first conductive line and the second conductive line", as recited in claim 17, is unclear as to sidewall or sidewalls of which element applicant refers.
Claim 17 recites the limitation "the second insulating material" in line 13. There is insufficient antecedent basis for this limitation in the claim. Also, it is unclear as to whether said limitation is the same as or different from “an insulating material”, as recited in claim 17, line 10.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20, as best understood, is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Young et al. (2022/0231050).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As for claim 1, Young et al. show in Figs. 1A-1C, 2, 27A-27E and related text a device 200, comprising:
a plurality of vertically stacked word lines 72 comprising a first word line 72A and a second word line 72B;
a source line 108 intersecting the first word line and the second word line;
a bit line 106 intersecting the first word line and the second word line, the bit line being insulated from the source line by a first dielectric material 98A/98B;
a memory film 90 between the first word line and the source line and between the first word line and the bit line; and
a first semiconductor material 92 between the memory film and the source line and between the memory film and the bit line, wherein the memory film extends from a level of a top surface of the plurality of vertically stacked word lines to directly under the bit line.
As for claim 2, Young et al. show first word line provides a gate for a first transistor 202, the second word line provides a gate for a second transistor 202, the source line provides a first source/drain region for the first transistor and a second source/drain region for the second transistor, and the bit line provides a third source/drain region for the first transistor and a fourth source/drain region for the second transistor (Fig. 1A).
As for claim 3, Young et al. show the bit line physically contacts a first sidewall of the first semiconductor material and a second sidewall of the first semiconductor material, the first sidewall of the first semiconductor material being laterally displaced from the second sidewall of the first semiconductor material (Fig. 1A).
As for claim 4, Young et al. show a second dielectric material 102 contacting a sidewall of the first semiconductor material and a sidewall of the source line (Fig. 1A).
As for claim 5, Young et al. show an additional bit line 106 on an opposing side of the second dielectric material as the source line (Fig. 1A).
As for claim 6, Young et al. show the second dielectric material contacts a sidewall of the additional bit line (Fig. 1A).
As for claim 7, Young et al. show a second semiconductor material 92 between the first word line and the additional bit line, wherein the second semiconductor material is insulated from the first semiconductor material by the second dielectric material (Fig. 1A).
As for claim 8, Young et al. show the memory film is further disposed between the first word line and the second semiconductor material, and wherein the memory film extends continuously from the first semiconductor material to the second semiconductor material (Fig. 1A).
As for claim 9, Young et al. show the memory film is a ferroelectric material ([0025]).
As for claim 10, Young et al. show the first word line is disposed under and is longer than the second word line (Fig. 1A, 27B).
As for claim 11, Young et al. show in Figs. 1A-1C, 2, 27A-27E and related text a device 200, comprising:
a first memory cell (lowest one of) 202 comprising a first thin film transistor, wherein the first thin film transistor comprises:
a first gate electrode made of a section of a first word line 72A; and
a first channel region made of a first section of a semiconductor material 92, a ferroelectric material 90 being disposed between the first channel region and the first gate electrode;
a source line 108, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor;
a bit line 106, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor, wherein the ferroelectric material and the semiconductor material each extends directly under the bit line; and
a second memory cell (2nd from the lowest one of) 202 over the first memory cell, the second memory cell comprising a second thin film transistor over the first thin film transistor.
As for claim 12, Young et al. show the second thin film transistor comprises:
a second gate electrode made of a section of a second word line 72B over the first word line; and
a second channel region 92 made of a second section of the semiconductor material, the second section of the semiconductor material being disposed over the first section of the semiconductor material, and the ferroelectric material being disposed between the second channel region and the second gate electrode (Figs. 1A, 27B).
As for claim 13, Young et al. show a second portion of the source line provides a first source/drain electrode for the second thin film transistor (Fig. 1A).
As for claim 14, Young et al. show a second portion of the bit line provides a second source/drain electrode for the second thin film transistor (Fig. 1A).
As for claim 15, Young et al. show the second word line is shorter than the first word line (Figs. 1A, 27E).
As for claim 16, Young et al. show a top surface of the bit line is wider than a bottom surface of the bit line (Fig. 27B).
As for claim 17, Young et al. show in Figs. 1A-1C, 2, 27A-27E and related text a device 200, comprising:
a first conductive line 72A and a second conductive line 72B vertically stacked over a semiconductor substrate;
a memory film 90 on sidewalls of the first conductive line and the second conductive line;
a first oxide semiconductor (OS) material 92, wherein the memory film separates the first OS material from the first conductive line and the second conductive line;
a third conductive line 106 on a sidewall of the first OS material;
a fourth conductive line 108 on the sidewall of the first OS material; and
an insulating material 98A/98B on the sidewall of the first OS material, the insulating material separating the third conductive line from the fourth conductive line, wherein the second insulating material physically contacts a first sidewall of the third conductive line, and wherein a third insulating material 202 physically contacts a second sidewall of the third conductive line that is opposite to the first sidewall of the third conductive line.
As for claim 18, Young et al. show the first OS material extends continuously from the third conductive line to the fourth conductive line (Fig. 1A).
As for claim 19, Young et al. show the memory film is made of a ferroelectric material ([0025]).
As for claim 20, Young et al. show a semiconductor substrate 50;
a plurality of transistors on the semiconductor substrate ([0031]); and
an interconnect structure 320 between the plurality of transistors and the first conductive line (Figs. 1A-1C, 2; [0017]).
Claim(s) 1-7 and 9, as best understood, is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jiang et al. (2021/0118900).
As for claim 1, Jiang et al. show in Figs. 17A-17B and related text a device, comprising:
a plurality of vertically stacked word lines 300 comprising a first word line (bottommost one of) 300 and a second word line (one above the bottommost one of) 300;
a source line 500 (at 110 of left one of 100) intersecting the first word line and the second word line;
a bit line 500 (at 110 of left one of 100) intersecting the first word line and the second word line, the bit line being insulated from the source line by a first dielectric material 400;
a memory film 200 between the first word line and the source line and between the first word line and the bit line; and
a first semiconductor material 100 between the memory film and the source line and between the memory film and the bit line, wherein the memory film extends from a level of a top surface of the plurality of vertically stacked word lines to directly under the bit line.
As for claim 2, Jiang et al. show first word line provides a gate for a first transistor, the second word line provides a gate for a second transistor, the source line provides a first source/drain region for the first transistor and a second source/drain region for the second transistor, and the bit line provides a third source/drain region for the first transistor and a fourth source/drain region for the second transistor (Figs. 17A-17B).
As for claim 3, Jiang et al. show the bit line physically contacts a first sidewall of the first semiconductor material and a second sidewall of the first semiconductor material, the first sidewall of the first semiconductor material being laterally displaced from the second sidewall of the first semiconductor material (Fig. 17B).
As for claim 4, Jiang et al. show a second dielectric material 654 (thermally) contacting a sidewall of the first semiconductor material and a sidewall of the source line (Fig. 17B).
As for claim 5, Jiang et al. show an additional bit line 500 (at 120 of right one of 100) on an opposing side of the second dielectric material as the source line (Fig. 17B).
As for claim 6, Jiang et al. show the second dielectric material (thermally) contacts a sidewall of the additional bit line (Fig. 17B).
As for claim 7, Jiang et al. show a second semiconductor material 100 between the first word line and the additional bit line, wherein the second semiconductor material is insulated from the first semiconductor material by the second dielectric material (Fig. 17B).
As for claim 9, Jiang et al. show the memory film is a ferroelectric material ([0036], lines 13-14).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 10, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (2021/0118900) in view of Herner et al. (2020/0185411).
Jiang et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, including the first word line is disposed under, except the first word line is longer than the second word line.
Herner et al. teach in Figs. 15-16 and related text the first word line is longer than the second word line.
Jiang et al. and Herner et al. are analogous art because they are directed to a memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Jiang et al. with the specified feature(s) of Herner et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the first word line being longer than the second word line, as taught by Herner et al., in Jiang et al.'s device, in order to simplify the processing steps of making the device and improve the performance of the device.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1, 2 and 9-15, as best understood, is rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 6-10 of U.S. Patent No. 12,069,864 in view of Jiang et al. (2021/0118900).
U.S. Patent No. 12,069,864 shows:
As for claim 1, a device (claim 1), comprising:
a plurality of vertically stacked word lines comprising a first word line and a second word line (lines 3-6);
a source line intersecting the first word line and the second word line (lines 11-12);
a bit line intersecting the first word line and the second word line, the bit line being insulated from the source line by a first dielectric material (lines 13-15);
a memory film between the first word line and the source line and between the first word line and the bit line (lines 16-18); and
a first semiconductor material between the memory film and the source line (lines 20-23), wherein the memory film extends under the bit line.
As for claim 11, a device (claims 8 and 9), comprising:
a first memory cell comprising a first thin film transistor (claim 8, lines 3-4), wherein the first thin film transistor comprises:
a first gate electrode made of a section of a first word line (lines 6-7); and
a first channel region made of a first section of a semiconductor material (lines 13-14), a ferroelectric material (lines 10);
a source line, wherein a first portion of the source line provides a first source/drain electrode for the first thin film transistor (lines 16-20);
a bit line, wherein a first portion of the bit line provides a second source/drain electrode for the first thin film transistor (lines 21-23), wherein the ferroelectric material and the semiconductor material each extends directly under the bit line (lines 23-26); and
a second memory cell over the first memory cell, the second memory cell comprising a second thin film transistor over the first thin film transistor (claim 9).
As for claim 12, the second thin film transistor comprises:
a second gate electrode made of a section of a second word line over the first word line (claim 10, lines 1-3); and
U.S. Patent No. 12,069,864 does not disclose the first semiconductor material between the memory film and the bit line, and the memory film extends from a level of a top surface of the plurality of vertically stacked word lines (claim 1); the ferroelectric material being disposed between the first channel region and the first gate electrode (claim 11); a second channel region made of a second section of the semiconductor material, the second section of the semiconductor material being disposed over the first section of the semiconductor material, and the ferroelectric material being disposed between the second channel region and the second gate electrode (claim 12).
Jiang et al. teach in Figs. 17A-17B and related text:
As for claim 1, the first semiconductor material 100 between the memory film 200 and the bit line 500, and
the memory film extends from a level of a top surface of the plurality of vertically stacked word lines 300 to directly under the bit line.
As for claim 11, the ferroelectric material 200 being disposed between the first channel region and the first gate electrode.
As for claim 12, a second channel region made of a second section of the semiconductor material 100, the second section of the semiconductor material being disposed over the first section of the semiconductor material, and the ferroelectric material being disposed between the second channel region and the second gate electrode.
U.S. Patent No. 12,069,864 and Jiang et al. are analogous art because they are directed to a memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify U.S. Patent No. 12,069,864 with the specified feature(s) of Jiang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the first semiconductor material between the memory film and the bit line; the memory film extending from a level of a top surface of the plurality of vertically stacked word lines; the ferroelectric material being disposed between the first channel region and the first gate electrode, and a second channel region made of a second section of the semiconductor material, the second section of the semiconductor material being disposed over the first section of the semiconductor material, and the ferroelectric material being disposed between the second channel region and the second gate electrode, as taught by Jiang et al. in U.S. Patent No. 12,069,864’s device, in order to improve the performance of the device.
As for claim 2, the combined device shows first word line provides a gate for a first transistor, the second word line provides a gate for a second transistor, the source line provides a first source/drain region for the first transistor and a second source/drain region for the second transistor, and the bit line provides a third source/drain region for the first transistor and a fourth source/drain region for the second transistor (‘864: claim 2).
As for claim 9, the combined device shows the memory film is a ferroelectric material (‘864: claim 6).
As for claim 10, the combined device shows the first word line is disposed under and is longer than the second word line (‘864: claim 7).
As for claim 13, the combined device shows a second portion of the source line provides a first source/drain electrode for the second thin film transistor (‘864: claim 9).
As for claim 14, the combined device shows a second portion of the bit line provides a second source/drain electrode for the second thin film transistor (‘864: claim 9).
As for claim 15, the combined device shows the second word line is shorter than the first word line (864’: claim 10).
Claims 17-19, as best understood, are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 15 and 18 of U.S. Patent No. 12,069,864. Although the claims at issue are not identical, they are not patentably distinct from each other because
As for claim 17, U.S. Patent No. 12,069,864 shows a device (claim 15), comprising:
a first conductive line and a second conductive line vertically stacked over a semiconductor substrate (lines 2-3; note: when one layer over another layer, which implicitly implies that the one layer is vertically stacked over the another layer);
a memory film on sidewalls of the first conductive line and the second conductive line (lines 6-7);
a first oxide semiconductor (OS) material, wherein the memory film separates the first OS material from the first conductive line and the second conductive line (lines 8-11);
a third conductive line on a sidewall of the first OS material (lines 12-13);
a fourth conductive line on the sidewall of the first OS material (lines 14-15); and
an insulating material on the sidewall of the first OS material, the insulating material separating the third conductive line from the fourth conductive line, wherein the second insulating material physically contacts a first sidewall of the third conductive line, and wherein a third insulating material physically contacts a second sidewall of the third conductive line that is opposite to the first sidewall of the third conductive line (lines 16-25).
As for claim 18, U.S. Patent No. 12,069,864 discloses the first OS material extends continuously from the third conductive line to the fourth conductive line (claim 15; lines 15-17).
As for claim 19, U.S. Patent No. 12,069,864 discloses the memory film is made of a ferroelectric material (claim 18).
Claim 20, as best understood, is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 15 of U.S. Patent No. 12,069,864 in view of Herner et al. (2020/0185411).
U.S. Patent No. 12,069,864 disclosed substantially the entire claimed invention, as applied to claim 17 above, including a semiconductor substrate (claim 15, line 3).
U.S. Patent No. 12,069,864 does not disclose a plurality of transistors on the semiconductor substrate; and an interconnect structure between the plurality of transistors and the first conductive line.
Herner et al. teach in Figs. 1, 13, 14, 16 and related text a plurality of transistors on the semiconductor substrate (not shown); and
an interconnect structure 5 between the plurality of transistors and the first conductive line (Fig. 1; [0030]).
U.S. Patent No. 12,069,864 and Herner et al. are analogous art because they are directed to a memory device and one of ordinary skill in the art would have had a reasonable expectation of success to modify U.S. Patent No. 12,069,864 with the specified feature(s) of Herner et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a plurality of transistors on the semiconductor substrate; and an interconnect structure between the plurality of transistors and the first conductive line, as taught by Herner et al., in U.S. Patent No. 12,069,864's device, in order to provide electrical connectivity of the device.
Conclusion
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/MEIYA LI/Primary Examiner, Art Unit 2811