DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 17-36 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu(USPGPUB DOCUMENT: 2022/0216141, hereinafter Wu) in view of Horng (USPGPUB DOCUMENT: 2007/0205248, hereinafter Horng) and Shieh (USPGPUB DOCUMENT: 2010/0219502, hereinafter Shieh).
Re claim 17 Wu discloses a method of manufacturing a semiconductor structure, comprising: forming a first passivation layer(217) over an interconnect structure(106/105/103/111) of a semiconductor substrate(102); forming a first capacitor(303) over the first passivation layer(217); forming a second passivation layer(306) over the first passivation layer(217), the second passivation layer(306) laterally surrounding(as viewed from the left) an insulator(topmost portions of 312) of the first capacitor(303); forming a third passivation layer(332/334) over the second passivation layer(306), the third passivation layer(332/334) covering an upper electrode(324) of the first capacitor(303); and forming a plurality of contact features(322A/B/C).
Wu does not disclose forming a plurality of contact features(322A/B/C) over the third passivation layer(332/334); wherein the first capacitor is at an elevation lower than elevation of a bottommost surface of each contact feature.
Horng disclose forming a plurality of contact features(36/38/40) over the third passivation layer(30).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Horng to the teachings of Wu in order to have capacitor formation process and resulting structure that is less costly and complicated than current processes and structures [Abstract, Sanders].
Wu and Horng do not disclose wherein the first capacitor is at an elevation lower than elevation of a bottommost surface of each contact feature.
Shieh disclose wherein the first capacitor(312/310/246) is at an elevation lower than elevation of a bottommost surface of each contact feature(412/522).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shieh to the teachings of Wu in order to preventing power spikes on the power lines from damaging other circuitry [0003ct, Shieh].
Re claim 18 Wu and Horng and Shieh disclose the method of claim 17, further comprising: forming a fourth passivation layer over the plurality of contact features(322A/B/C) and the third passivation layer(332/334).
Re claim 19 Wu and Horng and Shieh disclose the method of claim 17, wherein the forming of the first capacitor(303) comprises: forming a lower electrode(322A/B/C) of the first capacitor(303) over the first passivation layer(217); forming an opening of the second passivation layer(306), thereby exposing a portion of the lower electrode(322A/B/C); filling the opening with a high-k dielectric material, thereby forming the insulator(topmost portions of 312) surrounded by the second passivation layer(306); and forming the upper electrode(324) of the first capacitor(303) over the insulator(topmost portions of 312) prior to the formation of the third passivation layer(332/334).
Re claim 20 Wu and Horng and Shieh disclose the method of claim 17, further comprising: forming a second capacitor in the interconnect structure(106/105/103/111), wherein the second capacitor is proximal to a bottom surface of the first passivation layer(217).
Re claim 21 Wu discloses a method of manufacturing a semiconductor structure, comprising: receiving a substrate(102) comprising an interconnect structure(106/105/103/111) formed thereon; forming a first passivation structure(217/306) over the interconnect structure(106/105/103/111); forming a capacitor structure(capacitor in 303); and forming a plurality of contact features(322A/B/C) over the first passivation structure(217/306), wherein the capacitor structure(capacitor in 303) is disposed between two adjacent contact features(322A/B).
Wu does not disclose forming a capacitor structure(capacitor in 303) in the first passivation structure(217/306); and the capacitor structure is at an elevation lower than elevation of a bottommost surface of each contact feature.
Horng disclose forming a capacitor structure(28/46/12)[0038] in the first passivation structure(30/4);
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Horng to the teachings of Wu in order to have capacitor formation process and resulting structure that is less costly and complicated than current processes and structures [Abstract, Sanders].
Wu and Horng do not disclose the capacitor structure is at an elevation lower than elevation of a bottommost surface of each contact feature.
Shieh disclose the capacitor structure(312/310/246) is at an elevation lower than elevation of a bottommost surface of each contact feature(412/522).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shieh to the teachings of Wu in order to preventing power spikes on the power lines from damaging other circuitry [0003ct, Shieh].
Re claim 22 Wu and Horng and Shieh disclose the method of claim 21, wherein the forming of the first passivation structure(217/306) further comprises: forming a first passivation layer(217) over the interconnect structure(106/105/103/111); forming a second passivation layer(306) over the first passivation layer(217); and forming a third passivation layer(332/334) over the second passivation layer(306).
Re claim 23 Wu and Horng and Shieh disclose the method of claim 22, wherein a thickness of the second passivation layer(306) is greater than a thickness of the first passivation layer(217).
Re claim 24 Wu and Horng and Shieh disclose the method of claim 22, wherein the first passivation layer(217), the second passivation layer(306) and the third passivation layer(332/334) comprise a same material.
Re claim 25 Wu and Horng and Shieh disclose the method of claim 22, wherein the forming of the capacitor structure(capacitor in 303) further comprises: forming a lower electrode(322A/B/C) over the first passivation layer(217); forming an insulator(topmost portions of 312) over the lower electrode(322A/B/C) in the second passivation layer(306); and forming an upper electrode(324) over the insulator(topmost portions of 312).
Re claim 26 Wu and Horng and Shieh disclose the method of claim 25, wherein the third passivation layer(332/334) covers a top surface of the upper electrode(324).
Re claim 27 Wu and Horng and Shieh disclose the method of claim 25, wherein the forming of the insulator(topmost portions of 312) further comprises: forming an opening in the second passivation layer(306) to expose a portion of the lower electrode(322A/B/C); and filling the opening with a high-k dielectric material to form the insulator(topmost portions of 312).
Re claim 28 Wu and Horng and Shieh disclose the method of claim 21, further comprising forming a second passivation structure(217/306) over the plurality of contact features(322A/B/C).
Re claim 29 Wu and Horng and Shieh disclose the method of claim 28, wherein the second passivation structure(217/306) is conformal to a profile of the plurality of contact features(322A/B/C).
Re claim 30 Wu and Horng and Shieh disclose the method of claim 21, wherein an edge or a corner of at least one of the two adjacent contact features(322A/B) overlaps the capacitor structure(capacitor in 303).
Re claim 31 Wu discloses a method of manufacturing a semiconductor structure, comprising: receiving a substrate(102) comprising an interconnect structure(106/105/103/111) formed thereon; forming a passivation structure(217/306) over the interconnect structure(106/105/103/111); forming a second capacitor structure(capacitor in 303) in the passivation structure(217/306); and forming a contact feature(322A/B/C) over the passivation structure(217/306), wherein the second capacitor structure(capacitor in 303) overlaps the first capacitor(303) structure.
Wu does not disclose forming first capacitor(303) structure in the interconnect structure(106/105/103/111); wherein the second capacitor structure is at an elevation lower than elevation of a bottommost surface of the contact feature.
Horng disclose forming first capacitor(28/46/12)[0038] structure in the interconnect structure[0033];
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Horng to the teachings of Wu in order to have capacitor formation process and resulting structure that is less costly and complicated than current processes and structures [Abstract, Sanders].
Wu and Horng do not disclose wherein the second capacitor structure is at an elevation lower than elevation of a bottommost surface of the contact feature.
Shieh disclose wherein the second capacitor structure(312/310/246) is at an elevation lower than elevation of a bottommost surface of the contact feature(412/522).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Shieh to the teachings of Wu in order to preventing power spikes on the power lines from damaging other circuitry [0003ct, Shieh].
Re claim 32 Wu and Horng and Shieh disclose the method of claim 31, wherein the second capacitor structure(capacitor in 303) is separated from the first capacitor(303) structure by the passivation structure(217/306).
Re claim 33 Wu and Horng and Shieh disclose the method of claim 31, wherein a lateral distance between an edge of the contact feature(322A/B/C) and the second capacitor structure(capacitor in 303) is greater than 0.
Re claim 34 Wu and Horng and Shieh disclose the method of claim 21, wherein the interconnect structure(106/105/103/111) comprises an intermetal dielectric structure (IMD) structure and a plurality of metal lines formed in the IMD structure.
Re claim 35 Wu and Horng and Shieh disclose the method of claim 31, wherein the first capacitor(303) structure comprises: a first lower electrode(322A/B/C); a first upper electrode(324); and a first insulator(topmost portions of 312) disposed between the first lower electrode(322A/B/C) and the first upper electrode(324), wherein the first insulator(topmost portions of 312) comprises a high-k dielectric material.
Re claim 36 Wu and Horng and Shieh disclose the method of claim 32, wherein the second capacitor structure(capacitor in 303) comprises: a second lower electrode(322A/B/C); a second upper electrode(324); and a second insulator(topmost portions of 312) disposed between the second lower electrode(322A/B/C) and the second upper electrode(324), wherein the second insulator(topmost portions of 312) comprises a high-k dielectric material.
Response to Arguments
Applicant’s arguments with respect to claim(s) 17-36 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights