DETAILED ACTION
This Office action responds to the patent application no. 18/365,470 filed on August 4, 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6, 8, 14, and 15 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “first source/drain contact” in line 4 which is unclear how it relates to “a first source/drain contact” in line 2.
Claim 8 recites the limitation “channel members” in lines 7 and 8 which are unclear how they relate to “channel members” in line 5 and each other.
Claim 8 recites the limitation “inner spacer features” in line 11 which is unclear how it relates to “inner spacer features” in line 8.
Claim 14 recites the limitation "the stacking" in line 4. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “sacrificial layers” in lines 8 and 21 which are unclear how they relate “sacrificial layers” in line 5 and each other.
Claim 14 recites the limitation “a second region” in lines 9 and 14 which are unclear how they relate to each other.
Claim 15 recites the imitation “sacrificial layers” in lines 2 and 6 which are unclear how they relate to each other in this claim and other “sacrificial layers” in Claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 and 7 are rejected under 35 U.S.C. 102(a)(2) as being clearly anticipated by Lin et al. (Lin hereinafter) (US 2023/0028900).
Regarding Claims 1-4 and 7:
Lin (see Figure 1C) teaches {1} a semiconductor device, comprising: a first base fin and a second base fin extending from a substrate; an isolation feature 134 disposed between the first base fin and the second base fin; a first dummy epitaxial layer 118a disposed on the first base fin; a second dummy epitaxial layer 118c/118d disposed on the second base fin; a first insulator layer 120a over the first dummy epitaxial layer; a second insulator layer 120c/120d over the second dummy epitaxial layer; a first source/drain feature 110a disposed on the first insulator layer; and a second source/drain feature 110c/110d disposed on the second insulator layer, wherein a thickness of the first dummy epitaxial layer measured from a top surface of the first base fin is smaller than a thickness of the second dummy epitaxial layer measured from a top surface of the second base fin; {2} the first dummy epitaxial layer and the second dummy epitaxial layer comprise undoped silicon germanium (SiGe) or undoped silicon (Si); {3} the first insulator layer and the second insulator layer comprise silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbonitride, silicon oxide, aluminum oxide, or hafnium oxide; {4} the first insulator layer and the second insulator layer comprise a thickness between about 3 nm and about 8 nm; and {7} a first spacer layer 136/134 disposed along and in contact with sidewalls of the first dummy epitaxial layer, the first insulator layer, and the first source/drain feature.
Lin (see ¶ [0033], [0045], [0070], [0075]) teaches “the dielectric isolation structures 120a may include SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials … may have a thickness between 1 nm and 15 nm … other thicknesses and materials can be utilized for the dielectric isolation structures 120a without departing from the present disclosure”; “the epitaxial semiconductor regions 118c and 118d of the transistors 104c and 104d have a greater height than the epitaxial semiconductor regions 118a and 118b of the transistors 104a and 104b”; “The epitaxial semiconductor layer 118a-d can include an intrinsic semiconductor material … may include intrinsic Si … are not doped”; and “dielectric isolation structures 120a, 120c, and 120d can be formed by various processes … can have a thickness between 3 nm and 5 nm”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Lin hereinafter) (US 2023/0028900) as applied to claim 1 above, and further in view of Lin et al. (Lin2 herein after) (US 11,342,338).
Regarding to Claims 5 and 6:
Lin does not explicitly teach different height for the source/drain features and source/drain contacts.
Lin (see Fig. 30 and ¶ [0046], [0075]) teaches source/drain metal contact 274/276 and metal silicide features 272 formed on source/drain features 238/240 and “a dielectric layer may be deposited in a blanket deposition at regions of the transistors 104a, 104c, and 104d”.
Lin2 (see col.15/ll.2-) teaches “the size and shapes of the epitaxial source/drain features 226A-226D may be controlled with the combination of epitaxial growth and etching processes … according to design requirements … the top portion 226A(t) and 226D(t) may have a size greater than that of the top portions 226B(t) and 226C(t)”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Lin to further include the teaching of Lin2 to selectively control the size and shape of the epitaxial source/drain features so that some of the source/drain features can be shorter or taller than the others and the subsequent source/drain contacts can be shorter or taller than the others to meet the design requirements.
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (Lin hereinafter) (US 2023/0028900) in view of Zheng et al. (Zheng hereinafter) (US 11,315,934).
Regarding Claims 8-13:
Lin (see Figures 1A-1D) teaches {8} a semiconductor structure, comprising: a first source/drain feature 110a and a second source/drain feature 110b; a first source/drain contact 111a over the first source/drain feature; a second source/drain contact 111b over the second source/drain feature; a plurality of channel members 106a extending between and in contact with the first source/drain feature and the second source/drain feature; a gate structure 108a wrapping around each of the plurality of channel members; a plurality of inner spacer features 114 interleaving the plurality of channel members and spacing the gate structure apart from sidewalls of the first source/drain feature; {10} the first source/drain feature is disposed on a first insulator layer 120a, wherein the second source/drain feature is disposed on a second insulator layer; {11} the first insulator layer 120a and the second insulator layer comprise silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon oxycarbide, silicon carbonitride, silicon oxide, aluminum oxide, or hafnium oxide; {12} the first insulator layer is disposed on a first dummy epitaxial layer 118a, wherein the second insulator layer is disposed on a second dummy epitaxial layer 118b; and {13} the first dummy epitaxial layer and the second dummy epitaxial layer comprise undoped silicon germanium (SiGe) or undoped silicon (Si).
Lin (see ¶ [0023], [0033], [0044], and [0070]) teaches “source/drain regions 11a are both in contact with each of the nanostructures 106a”, “the dielectric isolation structures 120a may include SiN, SiON, SiOCN, SiOC, SiCN, SiO, AlO, HfO, or other suitable dielectric materials”; “the P-type transistor 104b may also include dielectric isolation structures similar to the dielectric isolation structure 120a of the transistor 104a”; “The epitaxial semiconductor layer 118a-d can include an intrinsic semiconductor material … may include intrinsic Si … are not doped”.
However, Lin does not explicitly teach {8} a helmet layer disposed on the gate structure and in contact with a topmost one of the plurality of inner spacer features, wherein the helmet layer is disposed between the first source/drain contact and the second source/drain contact and {9} the helmet layer is in contact with a top surface of the gate structure.
Zhang (col.3/ll.19-59) teaches “directed depopulation of one or more channels in a nanowire or nanoribbon transistor … bottom-up channel depopulation … top-down channel depopulation … transistors with different drive currents may be needed for different circuit types … to achieving different drive currents by depopulating the number of nanowire transistor channels in device structure … channel depopulation of nanowire transistor to provide for modulation of drive currents in different devices, which may be needed for different circuits … a depopulation dopant is implanted into the top Si layer … the top Si layer is rendered non-conducting without negatively impacting the underlying Si layers”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Lin to further include the teaching of Zhang to depopulate the topmost channel member to modulate the drive current for different circuit types based on design requirements.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claims 14 and 15 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b), 2nd paragraph, set forth in this Office action.
Regarding to Claim 14: The prior art of record neither anticipates nor renders obvious a method of a semiconductor device, wherein selectively and partially recessing sidewalls of the plurality of the sacrificial layer to form inner spacer recesses, selectively removing the high-germanium layer in the first fin-shaped structure to form a top gap, forming inner spacer features in the inner spacer recesses; forming a helmet feature in the top gap. These features in combination with other elements in the claim are neither disclosed nor suggested by the prior art of record.
Claims 15-20 depend on claim 14 so they are allowable for the same reason.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814