Prosecution Insights
Last updated: April 19, 2026
Application No. 18/366,255

INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME

Non-Final OA §103
Filed
Aug 07, 2023
Examiner
FERNANDES, ERROL V
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
667 granted / 786 resolved
+16.9% vs TC avg
Moderate +12% lift
Without
With
+11.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
28 currently pending
Career history
814
Total Applications
across all art units

Statute-Specific Performance

§103
58.7%
+18.7% vs TC avg
§102
36.7%
-3.3% vs TC avg
§112
4.0%
-36.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 786 resolved cases

Office Action

§103
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Group I, Species III, (Figs. 24-26), claims 7, 8, 10, 13, 14 and 17-26 in the reply filed on 02/18/2026 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. US 2017/0278816 A1 in further view of Tsao et al. US 2020/0020603 A1. Regarding claims 14 and 17, Li discloses: A method (Figs. 1A/1B and 9-12) comprising: forming first reflowable connectors on a first subset of bond pads (inner 336) of a package substrate (110), the first reflowable connectors disposed in a center of the package substrate in a top-down view (Figs. 1A/1B and 9-11; inner 530/130); forming second reflowable connectors on a second subset of the bond pads (outer 336) of the package substrate, the second reflowable connectors disposed in an edge/corner of the package substrate in the top-down view, the second reflowable connectors having a greater height than the first reflowable connectors (Figs. 1A/1B and 9-11; outer 530/135); after forming the first reflowable connectors and the second reflowable connectors, placing the package substrate on an interposer (Fig. 11, 101 BGA package attached to interposer as noted in para 0049). Li does not disclose: reflowing the first reflowable connectors and the second reflowable connectors to bond the package substrate to the interposer. Tsao discloses a publication from a similar field of endeavor in which: reflowing the reflowable connectors to bond a package substrate to a PCB (Fig. 7; para 0047). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the same reflow process taught by Tsao would be required to permanently bond the package substrate on the interposer of Li. (claim 17) Li; Figs. 1A/1B and 9-11. Claims 21 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. US 2017/0278816 A1 in view of Tsao et al. US 2020/0020603 A1 in further view of Tsai et al. US 2023/0361015 A1. Regarding claims 21 and 26, Li discloses: A method (Figs. 1A/1B and 9-12) comprising: forming reflowable connectors (Figs. 1A/1B and 9-11; 530/130/135) on bond pads (336) of a package substrate (110), wherein forming the reflowable connectors comprises: forming a first subset of the reflowable connectors in a first process, the first subset of the reflowable connectors being formed on a first subset of the bond pads (inner 336), the first subset of the bond pads being in a center of the package substrate (Figs. 1A/1B and 9-11; inner 530/130); forming a second subset of the reflowable connectors in a second process, the second process being distinct from the first process, the second subset of the reflowable connectors being formed on a second subset of the bond pads (outer 336), the second subset of the bond pads being in an edge/corner of the package substrate, the first subset of the bond pads having a greater width than the second subset of the bond pads (Figs. 1A/1B and 9-11; outer 530/135); and reflowing the first subset and the second subset of the reflowable connectors with a single reflow, the second subset of the reflowable connectors having a greater height than the first subset of the reflowable connectors, the second subset of the reflowable connectors having a greater volume than the first subset of the reflowable connectors (Fig. 11; para 0047); placing the package substrate on an interposer (Fig. 11, 101 BGA package attached to interposer as noted in para 0049) Li does not disclose: reflowing the reflowable connectors to bond the package substrate to the interposer. forming a first and second subset of the reflowable connectors in a first process and second process. Tsao discloses a publication from a similar field of endeavor in which: reflowing the reflowable connectors to bond a package substrate to a PCB (Fig. 7; para 0047). It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to understand that the same reflow process taught by Tsao would be required to permanently bond the package substrate on the interposer of Li. Li/Tsao do not disclose: forming a first and second subset of the reflowable connectors in a first process and second process. Tsai discloses a publication from a similar field of endeavor in which: forming a first (Fig. 11B; 66 solder features) and second subset (Fig. 11A; 64 solder features) of the reflowable connectors in a first process and second process. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to employ separate processes as taught by Tsai for determining the first and second reflowable connectors of Li to determine solder regions characterized by differing materials. (claim 26) Li; Figs. 1A/1B and 9-11. Allowable Subject Matter Claims 18-20 and 22-25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art fails to teach or clearly suggest the limitation of claim 18 stating “wherein the interposer comprises reflowable layers, a first subset of the reflowable layers are in contact with the first reflowable connectors, a second subset of the reflowable layers are in contact with the second reflowable connectors, the first reflowable connectors and the first subset of the reflowable layers are reflowed to form first conductive connectors, the second reflowable connectors and the second subset of the reflowable layers are reflowed to form second conductive connectors, and a second height of the second conductive connectors is greater than a first height of the first conductive connectors”; of claim 19 stating “wherein the interposer comprises reflowable layers, a first subset of the reflowable layers are in contact with the first reflowable connectors, a second subset of the reflowable layers are in contact with the second reflowable connectors, and the second subset of the reflowable layers are thicker than the first subset of the reflowable layers”; of claim 20 stating “wherein the interposer comprises reflowable layers, a first subset of the reflowable layers are in contact with the first reflowable connectors, a second subset of the reflowable layers are in contact with the second reflowable connectors, and the second subset of the reflowable layers are wider than the first subset of the reflowable layers”; of claim 22 stating “singulating the interposer after reflowing the reflowable connectors”; of claim 23 stating “wherein the interposer comprises reflowable layers, and wherein placing the package substrate comprises contacting the reflowable connectors to the reflowable layers without gaps between the reflowable connectors and the reflowable layers”; of claim 24 stating “wherein the interposer comprises reflowable layers, wherein a first subset of the reflowable layers contact the first subset of the reflowable connectors, a second subset of the reflowable layers contact the second subset of the reflowable connectors, and the second subset of the reflowable layers are thicker than the first subset of the reflowable layers”; and of claim 25 stating “wherein the interposer comprises reflowable layers, wherein a first subset of the reflowable layers contact the first subset of the reflowable connectors, a second subset of the reflowable layers contact the second subset of the reflowable connectors, and the second subset of the reflowable layers are wider than the first subset of the reflowable layers”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Claims 7, 8, 10 and 13 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art fails to teach or clearly suggest the limitation of claim 7 stating “forming reflowable layers on an interposer”. In light of these limitations, the prior art fails to anticipate or make obvious the claimed invention. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERROL V FERNANDES whose telephone number is (571)270-7433. The examiner can normally be reached on 9-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ERROL V FERNANDES/Primary Examiner, AU 2893
Read full office action

Prosecution Timeline

Aug 07, 2023
Application Filed
Mar 05, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12604781
PACKAGE STRUCTURE INCLUDING GUIDING PATTERNS
2y 5m to grant Granted Apr 14, 2026
Patent 12599043
SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
2y 5m to grant Granted Apr 07, 2026
Patent 12593738
FLIP CHIP PACKAGE FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 31, 2026
Patent 12588470
GLASS CARRIER STACKED PACKAGE ASSEMBLY METHOD
2y 5m to grant Granted Mar 24, 2026
Patent 12588554
Semiconductor Device and Method Forming Same
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
96%
With Interview (+11.6%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 786 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month