DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 06/26/2026 Claims 1-20 are pending for this examination.
Response to Arguments
Applicant’s reply filed on 06/26/2026 has been entered and considered. Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot. Thus, this rejection is properly made FINAL.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “the first dielectric structure being laterally between a vertical sidewall of the upper nano structure and the semiconductor region, the first dielectric structure having a hat-shaped profile between the semiconductor region and the gate structure”, in claim 1, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 1, The instant claims recite limitation “the first dielectric structure being laterally between a vertical sidewall of the upper nano structure and the semiconductor region” is not clear because first dielectric structure later laterally between a vertical sidewall of the upper nano structure and the semiconductor region is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claims 3-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, because of their dependency status from claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10, 12-14, 16 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Cho et al (US 2018/0294331 A1; hereafter Cho).
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Regarding claim 10. Cho discloses a semiconductor device comprising:
a substrate (Fig [1-4], substrate 102, Para [ 0028]);
a plurality of nano structures (Fig [1-4], nano-sheet stack structures NSS, Para [ 0057]) over the substrate (substrate 102), the plurality of nano structures (Fig [1-4], nano-sheet stack structures NSS, Para [ 0057]) comprising an upper nano structure (nano-sheets N3, Para [ 0034]) and lower nano structures (nano-sheets N1/N2 , Para [ 0034]) between the upper nano structure (nano-sheets N3 , Para [ 0034]) and the substrate (Fig [1-4], substrate 102);
a gate structure (gate structure [150, 145], Para [ 0037-0039]) over the plurality of nano structures (Fig [1-4], nano-sheet NSS, Para [ 0057]), the gate structure comprising a gate dielectric (gate structure [145] , Para [ 0037-0039]) and a gate electrode (gate structure [150] , Para [ 0037-0039]), the gate structure (gate structure [150, 145]) being between adjacent ones of the lower nano structures (nano-sheets N1/N2 , Para [ 0034]) and between the upper nano structure (nano-sheets N3 , Para [ 0034]) and an upper one of the lower nano structures (nano-sheets N1/N2 , Para [ 0034]) ;
an outer spacer (gate insulating liner 134) laterally adjacent the gate structure (gate structure [150, 145]);
an inner spacer structure (inner spacer 140, Para [ 0096]) adjacent the gate structure (gate structure [150, 145]), the inner spacer structure (inner spacer 140, Para [ 0096]) having portions being between adjacent ones of the lower nano structures (nano-sheets N1/N2, Para [ 0034]), the inner spacer structure (inner spacer 140, Para [ 0096]) extending below the outer spacers (gate insulating liner 134); and
a first source/drain region (source/drain protection layer 143, Para [ 0054]) contacting an end of the lower nano structures (nano-sheets N1/N2, Para [ 0034]), wherein the inner spacer (inner spacer 140, Para [ 0096]) structure extends between the upper nano structure (nano-sheets N3, Para [ 0034]) and the first source/drain region (source/drain protection layer 143, Para [ 0054]) along a line parallel to an upper surface of the substrate (Fig [1-4], substrate 102, Para [ 0028]).
Regarding claim 12. Cho discloses the semiconductor device of claim 10, Cho further discloses wherein the inner spacer structure (inner spacer 140, Para [ 0096]) has a hat-shaped profile (inner spacer 140, Para [ 0096]) between the gate structure (gate structure [150, 145]) and the first source/drain region (source/drain protection layer 143, Para [ 0054]).
Regarding claim 13. Cho discloses the semiconductor device of claim 12, Cho further discloses wherein a crown of the hat-shaped profile (inner spacer 140, Para [ 0096]) faces toward the gate structure (gate structure [150, 145]).
Regarding claim 14. Cho discloses the semiconductor device of claim 10, Cho further discloses wherein the gate electrode (gate structure [150]) has a concave surface facing the first source/drain region (source/drain protection layer 143, Para [ 0054]).
Regarding claim 16. Cho discloses a semiconductor device comprising:
a substrate (Fig [1-4], substrate 102, Para [ 0028]);
a channel region (Fig [1-4], nano-sheet stack structures NSS, Para [ 0057]) including a plurality of nano structures (Fig [1-4], nano-sheet stack structures NSS, Para [ 0057]) over the substrate (Fig [1-4], substrate 102), the plurality of nano structures (Fig [1-4], nano-sheet stack structures NSS, Para [ 0057]) comprising one or more lower nano structures (nano-sheets N1/N2, Para [ 0034]) and an upper nano structure (nano-sheets N3) over the one or more lower nano structures (nano-sheets N1/N2);
a gate structure (gate structure [150, 145], Para [ 0037-0039]) over the channel region (Fig [1-4], nano-sheet stack structures NSS, Para [ 0034, 0057]), the gate structure (gate structure [150, 145] , Para [ 0037-0039]) comprising a gate dielectric (gate structure [145] , Para [ 0037-0039]) and a gate electrode (gate electrode [150] , Para [ 0037-0039]), the gate structure (gate structure [150, 145] , Para [ 0037-0039]) being interposed between adjacent ones of the plurality of nano structures (Fig [1-4], nano-sheet NSS, Para [ 0057]);
an outer spacer (gate insulating liner 134) laterally adjacent the gate structure (gate structure [150, 145]);
an inner spacer structure (inner spacer 140, Para [ 0096]) adjacent the gate structure (gate structure [150, 145]), the inner spacer (inner spacer 140, Para [ 0096]) structure comprising a plurality of inner spacers (inner spacer 140, Para [ 0096]), each of the inner spacers (inner spacer 140, Para [ 0096]) being interposed between adjacent ones of the one or more lower nano structures (nano-sheets N1/N2 , Para [ 0034]), the inner spacer structure (inner spacer 140, Para [ 0096]) extending below the channel region (Fig [1-4], nano-sheets NSS, Para [ 0057]); and
a first source/drain region (source/drain protection layer 143, Para [ 0054]) adjacent the channel region (Fig [1-4], nano-sheets NSS, Para [ 0057]), the inner spacer structure (inner spacer 140, Para [ 0096]) extending between the upper nano structure (nano-sheets N3) and the first source/drain region (source/drain protection layer 143, Para [ 0054]) to isolate ( at least a portion vertically isolate) the upper nano structure nano-sheets N3) from the first source/drain region (source/drain protection layer 143, Para [ 0054]).
Regarding claim 19. Cho discloses the semiconductor device of claim 16, Cho further discloses wherein each inner spacer of the plurality of inner spacers have a hat-shaped profile (inner spacer 140, Para [ 0096]).
Claim Rejection- 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cho et al (US 2018/0294331 A1; hereafter Cho) as applied claims above and further in view of LEE et al (US 2017/0213913 A1; hereafter LEE).
Regarding claim 8. Cho discloses the semiconductor structure of claim 7, But, Cho does not disclose explicitly wherein the dielectric material of the first dielectric structure has a dielectric constant higher than the dielectric material of the gate spacer.
In a similar field of endeavor, LEE discloses wherein the dielectric material of the first dielectric structure has a dielectric constant higher than the dielectric material of the gate spacer (Para [ 0030-0031] discloses different dielectric constant of dielectric materials. Based on the different dielectric constant, dielectric material of the first dielectric structure can have dielectric constant higher than the dielectric material of the gate spacer).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Cho in light of LEE teaching “wherein the dielectric material of the first dielectric structure has a dielectric constant higher than the dielectric material of the gate spacer (Para [ 0030-0031] discloses different dielectric constant of dielectric materials. Based on the different dielectric constant, dielectric material of the first dielectric structure can have dielectric constant higher than the dielectric material of the gate spacer)” for further advantage such as to control resistance in gate region and improve device performance.
Allowable Subject Matter
Claims 11, 15, 17-18 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner's Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 11. wherein the inner spacer structure extends along a vertical sidewall of the outer spacer.
Regarding claim 15. wherein each of lower nano structures comprises a first segment and a second segment with the second segment having a larger diameter than the first segment, and the first source/drain region laterally contacts an edge portion of first segment, wherein the first segment is between the first source/drain region and the second segment.
Regarding claim 17. wherein the one or more lower nano structures extend past a lateral boundary of the outer spacer toward the first source/drain region.
Regarding claim 18. a second source/drain region adjacent the channel region, wherein the channel region is between the first source/drain region and the second source/drain region, wherein each of the one or more lower nano structures comprises: a first segment at an edge closest to the first source/drain region, the first segment having a first thickness; a second segment adjacent to the first segment, the second segment having a second thickness greater than the first thickness; and a third segment at an edge closest to the second source/drain region, the second segment being between the first segment and the third segment, the third segment having a third thickness less than the second thickness.
Regarding claim 20. wherein the inner spacer structure extends along a sidewall of the outer spacer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
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