Attorney’s Docket Number: 2023-0188/24061.4806US01
Filing Date: 8/07/2023
Inventors: Chou et al.
Examiner: Thomas McCoy
DETAILED ACTION
This Office action responds to the amendments filed 3/17/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first
inventor to file provisions of the AIA . In the event the determination of the status of the application as
subject to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing
from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art
relied upon, and the rationale supporting the rejection, would be the same under either status.
Acknowledgement
The Amendment filed on 3/17/2026, responding to the Office action mailed 12/18/2025, has been entered. Applicant amended claims 1, 10-11, and 25, added claim 29, and cancelled claim 22. The present Office action is made with all the suggested amendments being fully considered.
Response to Amendments
Applicant’s amendments to the claims have overcome the respective claim rejections
under 35 U.S.C. 103 as previously formulated in the Non-Final Office action mailed on 12/18/2025. Accordingly, the claim rejections of 35 U.S.C. 103 are hereby withdrawn. Accordingly, pending in this application are claims 1-12, 21, and 23-29. New grounds of rejections are presented below, however, as necessitated by applicant’s amendments to the claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Tung (US 20200058614 A1) in view of Jeng (US 20220045016 A1) further in view of Camacho (US 20090302452 A1).
Regarding claim 1, Tung (see, e.g., figs. 1J-1K) shows most aspects of the instant invention, including an integrated circuit (IC) package, comprising:
a first integrated circuit (IC) device (e.g., chip structure 140, see paragraph 36);
an interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c), disposed over (e.g., flip orientation of fig. 1K) the first IC device (e.g., chip structure 140) wherein the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c) includes a plurality of interconnection components (e.g., wiring layers 116b + conductive vias 116c);
a cavity (see, e.g., cavity formed in fig. 1J) disposed in the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c) in a cross-sectional side view;
a conductive via structure (e.g., conductive via structure 160) disposed at least partially within the cavity (see, e.g., annotated fig. 1 below) in the cross-sectional side view, wherein the conductive via structure (e.g., conductive via structure 160) is electrically coupled to the first IC device (e.g., chip structure 140) through at least a subset (e.g., note that the conductive via 160 is coupled to chip structure 140 through the wiring layers 116b, conductive pads 118, et cetera…see fig. 1K) of the interconnect components (e.g., wiring layers 116b + conductive vias 116c) of the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c);
a non-metallic material (e.g., protective layer 150 + paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide containing material (e.g., silicon oxide)…”) partially filling the cavity (see, e.g., annotated fig. 1 below);
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Annotated Fig. 1
Tung (see, e.g., figs. 1J-1K), however, fails to show a second IC device having a first portion disposed partially within the cavity in the cross-sectional side view and having a second portion disposed outside the cavity in the cross-sectional view, wherein the second IC device is electrically coupled to the first IC device, through at least a subset of the interconnect components of the interconnection structure.
Jeng (see, e.g., fig. 1J), in a similar device to Tung, teaches a second IC device (e.g., chip-containing structure 124B) electrically coupled to a first IC device (e.g., chip-containing structure 124A) through a subset of interconnect components (e.g., multiple conductive features 106) of an interconnection structure (see, e.g., paragraph 33 “The interconnection structure includes multiple dielectric layers 108 and multiple conductive features 106”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the second IC device of Jeng within the cavity of Tung (replacing the conductive via structure), in order to achieve the expected result of providing an additional IC device within the package, supplying numerous electrically coupled chip as needed. Note that the second IC device replaces the conductive via structure, and hence is disposed within the same cavity and connected to the same interconnect components, surrounded by the non-metallic material.
Tung in view of Jeng, however, fails to teach wherein the second IC device has a second portion disposed outside the cavity in the cross-sectional side view.
Camacho (see, e.g., fig. 13), in a similar device to Tung in view of Jeng, teaches an IC device (e.g., integrated circuit device 332) has a second portion disposed outside (e.g., note the portion of integrated circuit device 332 extending above the top surface of the cavity) a cavity (e.g., central recess 1104) in a cross-sectional side view (e.g., cross-sectional side view shown in fig. 13).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the extension-out-of-cavity configuration of Camacho within the device of Tung in view of Jeng, in order to achieve the expected result of configuring the second IC device closer to the conductive components of the RDL (which are also disposed above the cavity), increasing the processing speed between the second IC device and conductive components due to the shortened electrical distance (note that the IC device of Camacho has interconnect bond wires directly connecting the IC device to the terminals), providing connection between the second IC device and the semiconductor structure through the RDL (see, e.g., the bottom 112 structure in annotated fig. 1), and an increased processing speed between the conductive components on the other side of the RDL and the second IC device through the direct wired connection.
Regarding claim 3, Jeng (see, e.g., fig. 1J) teaches that the IC devices can include a system on chip (SoC) device (see, e.g., paragraph 46 “The integrated circuit devices include…system-on-chip (SoC) devices…”), and the second IC device (e.g., chip-containing structure 124B) includes a chip that includes a plurality of passive components but no transistors (see, e.g., paragraph 139 “In some embodiments, the device elements are passive device elements”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the system on chip configuration of Jeng within the first IC device of Tung, in order to optimize the performance of the chip structure, defining and designing the hardware as needed. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the passive components within the added second device of Tung in view of Jeng further in view of Camacho, in order to achieve the expected result of consuming, storing, or releasing the electrical energy as needed.
Regarding claim 4, Jeng (see, e.g., fig. 1J) teaches that the IC devices can include a system on chip (SoC) device (see, e.g., paragraph 46 “The integrated circuit devices include…system-on-chip (SoC) devices…”) and the second IC device (e.g., chip-containing structure 124B) includes a chip that includes transistors (see, e.g., paragraph 45 “Each of the chip structures 124A-124D may include a semiconductor substrate, an interconnection structure 125, and the conductive pillars 126. In some embodiments, various device elements are formed in and/or on the semiconductor substrate of the chip structures 124A-124D. Examples of the various device elements include transistors…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the system on chip configuration of Jeng within the first IC device of Tung in view of Jeng further in view of Camacho, in order to optimize the performance of the chip structure, defining and designing the hardware as needed. It also would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the transistors of Jeng within the added second IC device of Tung in view of Jeng further in view of Camacho, in order to achieve the expected result of providing current switches within the device.
Regarding claim 5, Tung (see, e.g., fig. 1K) shows wherein an uppermost surface of the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c) is more elevated vertically (remember that the interconnection structure lies below the non-metallic material (e.g., protective layer 150 + paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide containing material (e.g., silicon oxide)…”) before the orientation of fig. 1K is flipped) than an uppermost surface of the non-metallic material (e.g., protective layer 150 + paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide containing material (e.g., silicon oxide)…”) in the cross-sectional side view.
Regarding claim 8, Tung (see, e.g., figs. 1J-1K) shows the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c) includes an isolation material (e.g., dielectric material 116a + paragraph 25 “The dielectric layer 116a is made of an oxide-containing material (e.g., silicon oxide)…”) in which the interconnection components (e.g., wiring layers 116b + conductive vias 116c) are embedded, and the non-metallic material (e.g., protective layer 150 + paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide containing material (e.g., silicon oxide)…”) partially filling the cavity (see, e.g., cavity formed in fig. 1J) has a same material composition (see, e.g., paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide-containing material (e.g., silicon oxide)…”) as the isolation material (e.g., dielectric material 116a + paragraph 25 “The dielectric layer 116a is made of an oxide-containing material (e.g., silicon oxide)…”).
Claims 6-7, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Tung in view of Jeng further in view Camacho and Gu (US 20150318262 A1).
Regarding claim 6, Tung in view of Jeng further in view of Camacho fails to teach an under bump metallization (UBM) structure disposed over the interconnection structure in the cross-sectional side view, wherein no dam structure is disposed between the UBM structure and the second IC device in the top view, and a solder bump disposed over the UBM structure in the cross-sectional side view.
Gu (see, e.g., fig. 2), in a similar device to Tung in view of Jeng further in view of Camacho, teaches an under bump metallization (UBM) structure (e.g., third under bump (UBM) layer 252) in a cross-sectional view, and a solder bump (e.g., solder ball 204) disposed under the UBM structure (e.g., third under bump (UBM) layer 252) in the cross-sectional side view.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the UBM and solder bump of Gu on under the substrate of Tung in view of Jeng further in view of Camacho, in order to provide a connectivity interface onto the substrate’s surface for electrical coupling between the substrate and additional devices as necessary. Note that the orientation of Tung is flipped, and so implementing the UBM and solder bump beneath the substrate respectively, hence the flipped orientation will disclose the solder bump over the UBM structure, over the interconnection structure in the cross-sectional side view.
Regarding claim 7, Tung (see, e.g., figs. 1J-1K) shows the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c) includes an isolation material (e.g., dielectric material 116a + paragraph 25 “The dielectric layer 116a is made of an oxide-containing material (e.g., silicon oxide) or another suitable insulating material”) in which the interconnection components (e.g., wiring layers 116b + conductive vias 116c) are embedded, and the non-metallic material (e.g., protective layer 150 + paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide containing material (e.g., silicon oxide)…”) partially filling the cavity (see, e.g., cavity formed in fig. 1J) includes an underfill material (see, e.g., paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide-containing material (e.g., silicon oxide)…”).
Tung in view of Jeng further in view of Camacho, however, fails to explicitly teach the non-metallic material has a different material composition than the isolation material.
Gu (see, e.g., fig. 2), in a similar device to Tung in view of Jeng further in view of Camacho, teaches a dielectric layer (e.g., first dielectric layer 202) comprising a material other than silicon oxide (see, e.g., paragraph 60 “In some implementations, an inorganic dielectric layer may include one of at least, silicon oxide, silicon nitride, silicon carbon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the dielectric material of a composition other than SiO2 (say, silicon nitride) within the dielectric layer of Tung in view of Jeng further in view of Camacho, because many are recognized in the semiconductor art for their usage in dielectric materials, as taught by Gu, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Regarding claim 9, Tung (see, e.g., figs. 1J-1K) shows the interconnection structure (e.g., dielectric layer 116a + wiring layers 116b + conductive vias 116c) includes an isolation material (e.g., dielectric material 116a + paragraph 25 “The dielectric layer 116a is made of an oxide-containing material (e.g., silicon oxide)…”) in which the interconnection components (e.g., wiring layers 116b + conductive vias 116c) are embedded, and the non-metallic material (e.g., protective layer 150 + paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide containing material (e.g., silicon oxide)…”) partially filling the cavity (see, e.g., cavity formed in fig. 1J) includes the isolation material (see, e.g., paragraph 56 “The protective layer 150 is made of an insulating material such as an oxide-containing material (e.g., silicon oxide)…” + paragraph 25 “The dielectric layer 116a is made of an oxide-containing material (e.g., silicon oxide)…”).
Tung in view of Jeng further in view of Camacho, however, fails to explicitly teach the non-metallic material includes an underfill material having a different material composition than the isolation material.
Gu (see, e.g., fig. 2), in a similar device to Tung in view of Jeng in view of Camacho, teaches a dielectric layer (e.g., first dielectric layer 202) comprising a material other than silicon oxide (see, e.g., paragraph 60 “In some implementations, an inorganic dielectric layer may include one of at least, silicon oxide, silicon nitride, silicon carbon…”).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include an additional dielectric material of a composition other than SiO2 (say, silicon nitride) within the dielectric layer of Tung in view of Jeng further in view of Camacho, in order to diversify the dielectric material profile, and because many are recognized in the semiconductor art for their usage in dielectric materials, as taught by Gu, and selecting between known equivalents would be within the level of ordinary skill in the art. KSR International Co. v. Teleflex Inc., 550 U.S.--,82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 10-12, 21, 23-28 are allowed.
Claims 2 and 29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, Tung (US 20200058614 A1) in view of Jeng (US 20220045016 A1) teaches most aspects of the integrated circuit (IC) package.
However, Tung in view of Jeng fails to disclose or suggest wherein the first one of the conductive components of the RDL structure has a lower vertical position than the second one of the conductive components of the RDL structure in a cross-sectional side view.
Regarding claim 25, Tung (US 20200058614 A1) in view of Jeng (US 20220045016 A1) teaches most aspects of the integrated circuit (IC) package.
However, Tung in view of Jung fails to disclose or suggest wherein an uppermost surface of the underfill material is disposed below an uppermost point of the cavity.
Therefore, the above limitations in the entirety of the claim are neither anticipated nor rendered obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee, and, to avoid processing delays, should preferably accompany the issue fee. Such admissions should be clearly labeled “Comments on Statement of Reasons for Allowance”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
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