DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 8/28/2026 is acknowledged.
Applicant amended claim 1.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/14/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5, and 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 2020/0373301) (hereafter Kim).
Regarding claim 1, Kim (see upside down figure of Fig. 5) discloses a semiconductor structure, comprising:
a power rail (POR1 in Fig. 5, paragraph 0034);
an isolation structure (second and fourth 122 from the left corner of Fig. 5, paragraph 0031) over the power rail (POR1 in Fig. 5);
first (third SDB from the left corner of Fig. 5, paragraph 0028) and second source/drain (S/D) features (fourth SD1 and fourth UAC from the left corner of Fig. 5, paragraph 0028) over the isolation structure (second and fourth 122 from the left corner of Fig. 5), defining a first direction (horizontal direction in Fig. 5) from the first S/D feature (third SD1 from the left corner of Fig. 5) to the second S/D feature (fourth SD1 and fourth UAC from the left corner of Fig. 5);
one or more channel layers (CHP in Fig. 5, paragraph 0047) over the isolation structure (second and fourth 122 from the left corner of Fig. 5) and connecting the first (third SDB from the left corner of Fig. 5) and the second S/D features (fourth SD1 and fourth UAC from the left corner of Fig. 5);
a first via structure (UV, third UAC, and third SDE from the left corner of Fig. 5, paragraph 0034) extending through the isolation structure (second and fourth 122 from the left corner of Fig. 5) and electrically connecting the first S/D feature (third SDB from the left corner of Fig. 5) and the power rail (POR1 in Fig. 5); and
a first dielectric feature (124 and third 122 from the left corner of Fig. 5, paragraph 0031) extending through (see Fig. 5, wherein third 122 from the left corner of Fig. 5 extending through second and fourth 122 from the left corner of Fig. 5) the isolation structure (second and fourth 122 from the left corner of Fig. 5) and physically contacting the second S/D feature (fourth SD1 and fourth UAC from the left corner of Fig. 5) and the power rail (POR1 in Fig. 5),
wherein the first via structure (UV, third UAC, and third SDE from the left corner of Fig. 5) has a first width (vertical length of UV, third UAC, and third SDE from the left corner of Fig. 5) in a first cross-section perpendicular to the first direction (horizontal direction in Fig. 5), the first dielectric feature (124 and third 122 from the left corner of Fig. 5) has a second width (vertical length of 124 and third 122 from the left corner of Fig. 5) in the first cross-section, and the first width (vertical length of UV, third UAC, and third SDE from the left corner of Fig. 5) is greater than the second width (vertical length of 124 and third 122 from the left corner of Fig. 5), the second width (vertical length of 124 and third 122 from the left corner of Fig. 5) is a greatest width of the first dielectric feature (124 and third 122 from the left corner of Fig. 5) in the first cross-section.
Regarding claim 4, Kim further discloses the semiconductor structure of claim 1, wherein an outermost layer of the first dielectric feature (124 and third 122 from the left corner of Fig. 5) is a portion of a silicon nitride liner 124 (Fig. 5), and the via structure (UV and third UAC from the left corner of Fig. 5) adjoins the isolation structure (second and fourth 122 from the left corner of Fig. 5) in the first cross-section and adjoins the silicon nitride liner 124 (Fig. 5) in a third cross-section along the first direction (horizontal direction in Fig. 5).
Regarding claim 5, Kim further discloses the semiconductor structure of claim 1, wherein the first cross-section is through each of the first (third SD1 from the left corner of Fig. 5) and second source/drain features (fourth SD1 and fourth UAC from the left corner of Fig. 5).
Regarding claim 9, Kim further discloses the semiconductor structure of claim 1, wherein the first via structure (UV, third UAC, and third SDE from the left corner of Fig. 5) directly interfaces the isolation structure (second and fourth 122 from the left corner of Fig. 5).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1 above, and further in view of Park et al. (US 2020/0303264) (hereafter Park).
Regarding claim 2, Kim discloses the semiconductor structure of claim 1, however Kim does not disclose the first width is greater than the second width by about 10 % to about 40 %.
Park discloses the first width (thickness of RL and RU in Fig. 8; and see paragraph 0046, wherein “range of 3 nm to 10 nm”; and see paragraph 0041, wherein “range of 10 to 30 nm” such that the thickness of RL and RU is range of 13 nm to 40 nm) is greater than the second width (thickness of 218 in Fig. 8; and see paragraph 0041, wherein “range of 10 to 30 nm”) by about 10 % to about 40 %.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the first width is greater than the second width by about 10 % to about 40 %, as taught by Park, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Regarding claim 3, Kim discloses the semiconductor structure of claim 1, however Kim does not disclose the first width is greater than the second width by about 4 nm to about 20 nm.
Park discloses the first width (thickness of RL and RU in Fig. 8; and see paragraph 0046, wherein “range of 3 nm to 10 nm”; and see paragraph 0041, wherein “range of 10 to 30 nm” such that the thickness of RL and RU is range of 13 nm to 40 nm) is greater than the second width (thickness of 218 in Fig. 8; and see paragraph 0041, wherein “range of 10 to 30 nm”) by about 4 nm to about 20 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the first width is greater than the second width by about 4 nm to about 20 nm, as taught by Park, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1 above, and further in view of Nakjin et al. (US 2021/0126102) (hereafter Nakjin).
Regarding claim 7, Kim discloses the semiconductor structure of claim 1, however Kim does not disclose a silicide feature disposed between the first via structure and the first S/D feature.
Nakjin discloses a silicide feature (SC in Fig. 2A, paragraph 0048) disposed between the first via structure (AC in Fig. 2A, paragraph 0048) and the first S/D feature (SD1 in Fig. 2A, paragraph 0048).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form a silicide feature disposed between the first via structure and the first S/D feature, as taught by Nakjin, since silicide patterns SC (Nakjin, Fig. 2A, paragraph 0048) may be disposed between the active contact AC (Nakjin, Fig. 2A, paragraph 0048) and the first source/drain pattern SD1 (Nakjin, Fig. 2A, paragraph 0048) and between the active contact AC (Nakjin, Fig. 2A, paragraph 0048) and the second source/drain pattern SD2 (Nakjin, Fig. 2B, paragraph 0048), respectively to provide reliable metal-semiconductor contact and reduce electrical resistance between the active contact AC and the first source/drain pattern SD1 (Nakjin, Fig. 2A, paragraph 0048).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Nakjin as applied to claim 7 above, and further in view of Lee et al. (US 2020/0105867) (hereafter Lee).
Regarding claim 8, Kim in view of Nakjin discloses the semiconductor structure of claim 7, however Kim and Nakjin do not disclose a gap disposed adjacent the silicide feature, wherein the gap extends from the first via structure to the first S/D feature.
Lee discloses a gap 150a (Fig. 2I, paragraph 0032) disposed adjacent the silicide feature 148 (Fig. 2I, paragraph 0030), wherein the gap 150a (Fig. 2I) extends from the first via structure 136 (Fig. 2I, paragraph 0032) to the first S/D feature 106 (Fig. 2I, paragraph 0042).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim in view of Nakjin to form a gap disposed adjacent the silicide feature, wherein the gap extends from the first via structure to the first S/D feature, as taught by Lee, in order to minimize (Lee, paragraph 0011) coupling capacitance between the metal gates and contact plugs, air gaps can help reduce coupling capacitance because air has lower dielectric constant (k=1) than other dielectric materials.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 1 above, and further in view of Lee et al. (US 2020/0105867) (hereafter Lee).
Regarding claim 21, Kim discloses the semiconductor structure of claim 1, however Kim does not disclose an air gap disposed under the first via structure and the isolation structure.
Lee discloses an air gap 150a (Fig. 2I, paragraph 0032) disposed under the first via structure 136 (Fig. 2I, paragraph 0032) and the isolation structure 110 (Fig. 2I, paragraph 0015).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form an air gap disposed under the first via structure and the isolation structure, as taught by Lee, in order to minimize (Lee, paragraph 0011) coupling capacitance between the metal gates and contact plugs, air gaps can help reduce coupling capacitance because air has lower dielectric constant (k=1) than other dielectric materials.
Allowable Subject Matter
Claims 10-20 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Kim et al. (US 2020/0373301), discloses a backside power rail (POR1 in Fig. 5, paragraph 0034); an isolation structure 124 (Fig. 5, paragraph 0031) having a first surface (bottom surface of 124 in Fig. 5) interfacing the backside power rail (POR1 in Fig. 5); and first (third SD1 from the left corner of Fig. 5, paragraph 0028) and second source/drain (S/D) features (fourth SD1 and fourth UAC from the left corner of Fig. 5, paragraph 0028) but fails to disclose a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the backside power rail, wherein along a first cross- sectional view the first via structure has a first width and the first dielectric feature has a second width, and the first width is greater than the second width. Additionally, the prior art does not teach or suggest a semiconductor structure, comprising: a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the backside power rail, wherein along a first cross- sectional view the first via structure has a first width and the first dielectric feature has a second width, and the first width is greater than the second width in combination with other elements of claim 10.
In addition, a closest prior art, Kim et al. (US 2020/0373301), discloses a power rail (POR1 in Fig. 5, paragraph 0034); an isolation structure 124 (Fig. 5, paragraph 0031) comprising a first insulating material having a first surface (bottom surface of 124 in Fig. 5) interfacing the power rail (POR1 in Fig. 5); first (third SD1 from the left corner of Fig. 5, paragraph 0028) and second source/drain (S/D) features (fourth SD1 and fourth UAC from the left corner of Fig. 5, paragraph 0028) over a second surface (top surface of 124 in Fig. 5) of the isolation structure 124 (Fig. 5), the second surface (top surface of 124 in Fig. 5) opposing the first surface (bottom surface of 124 in Fig. 5); and a first via structure (UV and third UAC from the left corner of Fig. 5, paragraph 0034) extending through the isolation structure 124 (Fig. 5) and electrically connecting the first S/D feature (third SD1 from the left corner of Fig. 5) and the power rail (POR1 in Fig. 5) but fails to disclose a dielectric fin extending between the first S/D feature and the second S/D feature in a first cross-sectional view; a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail; an air gap between the second source/drain feature and a first sidewall of the dielectric fin; wherein the first via structure interfaces a second sidewall of the dielectric fin. Additionally, the prior art does not teach or suggest a semiconductor structure, comprising: a dielectric fin extending between the first S/D feature and the second S/D feature in a first cross-sectional view; a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail; an air gap between the second source/drain feature and a first sidewall of the dielectric fin; wherein the first via structure interfaces a second sidewall of the dielectric fin in combination with other elements of claim 17.
A closest prior art, Kim et al. (US 2020/0373301), discloses (see upside down figure of Fig. 5) a semiconductor structure, comprising: a backside power rail (POR1 in Fig. 5, paragraph 0034); an isolation structure 124 (Fig. 5, paragraph 0031) having a first surface (bottom surface of 124 in Fig. 5) interfacing the backside power rail (POR1 in Fig. 5); first (third SD1 from the left corner of Fig. 5, paragraph 0028) and second source/drain (S/D) features (fourth SD1 and fourth UAC from the left corner of Fig. 5, paragraph 0028) over a second surface (top surface of 124 in Fig. 5) of the isolation structure 124 (Fig. 5), the second surface (top surface of 124 in Fig. 5) opposing the first surface (bottom surface of 124 in Fig. 5); a plurality of channel layers (CHP in Fig. 5, paragraph 0047) over the isolation structure 124 (Fig. 5) and connecting the first (third SD1 from the left corner of Fig. 5) and the second S/D features (fourth SD1 and fourth UAC from the left corner of Fig. 5); a first via structure (UV and third UAC from the left corner of Fig. 5, paragraph 0034) extending through the isolation structure 124 (Fig. 5) and electrically connecting the first S/D feature (third SD1 from the left corner of Fig. 5) and the backside power rail (POR1 in Fig. 5) but fails to teach a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the backside power rail, wherein along a first cross- sectional view the first via structure has a first width and the first dielectric feature has a second width, and the first width is greater than the second width as the context of claim 10. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 11-16 depend on claim 10.
In addition, a closest prior art, Kim et al. (US 2020/0373301), discloses (see upside down figure of Fig. 5) a semiconductor structure, comprising: a power rail (POR1 in Fig. 5, paragraph 0034); an isolation structure 124 (Fig. 5, paragraph 0031) comprising a first insulating material having a first surface (bottom surface of 124 in Fig. 5) interfacing the power rail (POR1 in Fig. 5); first (third SD1 from the left corner of Fig. 5, paragraph 0028) and second source/drain (S/D) features (fourth SD1 and fourth UAC from the left corner of Fig. 5, paragraph 0028) over a second surface (top surface of 124 in Fig. 5) of the isolation structure 124 (Fig. 5), the second surface (top surface of 124 in Fig. 5) opposing the first surface (bottom surface of 124 in Fig. 5); a plurality of channel layers (CHP in Fig. 5, paragraph 0047) over the isolation structure 124 (Fig. 5) and connecting the first (third SD1 from the left corner of Fig. 5) and the second S/D features (fourth SD1 and fourth UAC from the left corner of Fig. 5) in a second cross-sectional view; and a first via structure (UV and third UAC from the left corner of Fig. 5, paragraph 0034) extending through the isolation structure 124 (Fig. 5) and electrically connecting the first S/D feature (third SD1 from the left corner of Fig. 5) and the power rail (POR1 in Fig. 5) but fails to teach a dielectric fin extending between the first S/D feature and the second S/D feature in a first cross-sectional view; a first dielectric feature extending through the isolation structure and physically contacting the second S/D feature and the power rail; an air gap between the second source/drain feature and a first sidewall of the dielectric fin; wherein the first via structure interfaces a second sidewall of the dielectric fin as the context of claim 17. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 18-20 depend on claim 17.
Response to Arguments
1. Applicant's arguments filed 8/28/2026 have been fully considered.
2. The applicant argues (REMARKS, first paragraph in page 7) that “In asserting that Kim provides the relative widths recited, the Examiner compared a width defined by a vertical length of a portion of the alleged first dielectric feature to that of the dimension of an entirety of Kim's layers combined to form the alleged first via structure. In particular, the Examiner stated, "the first dielectric feature 124 (Fig. 5) has a second width (vertical length of 124 in Fig. 5) in the first cross-section, and the first width (vertical length of UV and third UAC from the left corner of Fig. 5) is greater than the second width (vertical length of 124 in Fig. 5)". Id. As discussed in the interview with the Examiner, claim 1 has been amended to further define where the second width is measured, i.e., the second width is a greatest width of the first dielectric feature in the first cross-section. Therefore, the claim as amended precludes the selective measurement previously suggested by the Examiner. The rejection of claim 1 as amended should be withdrawn.” However, after further consideration of the Kim et al. (US 2020/0373301), Kim et al. (US 2020/0373301) disclose the first via structure (UV, third UAC, and third SDE from the left corner of Fig. 5) has a first width (vertical length of UV, third UAC, and third SDE from the left corner of Fig. 5) in a first cross-section perpendicular to the first direction (horizontal direction in Fig. 5), the first dielectric feature (124 and third 122 from the left corner of Fig. 5) has a second width (vertical length of 124 and third 122 from the left corner of Fig. 5) in the first cross-section, and the first width (vertical length of UV, third UAC, and third SDE from the left corner of Fig. 5) is greater than the second width (vertical length of 124 and third 122 from the left corner of Fig. 5), the second width (vertical length of 124 and third 122 from the left corner of Fig. 5) is a greatest width of the first dielectric feature (124 and third 122 from the left corner of Fig. 5) in the first cross-section.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights