DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, claims 1-14 and newly added claims 21-26, in the reply filed on February 20, 2026, is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 5, and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (U.S. Pub. 2021/0082832) [Hereafter “Yang”].
Regarding claims 1-2, Yang [Figs.3-4] discloses a method of processing a substrate, the method comprising:
forming a pattern of an electrically conductive [212-214] layer over the substrate, the electrically conductive layer and a first dielectric layer [210] being exposed at a surface of the substrate;
selectively depositing a graphene layer [220] over the electrically conductive layer relative to the first dielectric layer [Fig.3A];
selectively depositing a second dielectric layer [222] over the first dielectric layer relative to the graphene layer [Fig.3B]; and
depositing a third dielectric layer [226] over the substrate, the third dielectric layer covering the second dielectric layer and the graphene layer [Fig.3D].
further comprising:
patterning the third dielectric layer to form a recess [228-230], the third dielectric layer covering the graphene layer after the patterning, the recess being aligned with a portion of the pattern of the electrically conductive layer [Fig.3D]; and
extending the recess [228] to expose the graphene layer [Para.28].
Regarding claims 5 and 7, Yang [Figs.3-4] discloses a method of processing a substrate further comprising,
depositing a fourth dielectric layer over the third dielectric layer [226 (multiple layers); Para.25];
further comprising:
prior to depositing the third dielectric layer [226], depositing an etch stop layer (ESL) [224] over the substrate;
patterning the third dielectric layer [226] to form a recess, the ESL being exposed at a bottom of the recess after the patterning [Para.26]; and
removing the ESL to expose the graphene layer [Fig.3D].
Claim(s) 9-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Clark (U.S. Pub. 2022/0238323).
Regarding claim 9, Clark [Figs.3-7] discloses a method of processing a substrate, the method comprising:
forming a first recess in a first dielectric layer [210] of the substrate [Fig.3A];
filling the first recess with an electrically conductive material [220];
selectively depositing a graphene layer [302] [Para.28] over the electrically conductive material;
selectively depositing a second dielectric layer [310] over the first dielectric layer;
depositing a third dielectric layer [510-512] over the substrate to cover the graphene layer and the second dielectric layer.
performing a first etch process to form a second recess in the third dielectric layer, the recess being aligned with a portion of the first recess [Figs.5D-F]; and
performing a second etch process to extend the second recess and expose the graphene layer [Figs.5F-H], the second etch process being selective to the graphene layer [Para.48].
Regarding claims 10-12, Clark [Figs.3-7] discloses a method of processing a substrate
wherein a top surface of the second dielectric layer [310] is positioned higher than a top surface of the graphene layer [302] [Fig.3F];
wherein the recess is formed as a fully self-aligned via, the method further comprising, after the second etch process, filling the extended second recess with a second electrically conductive material [Figs.7A-B];
wherein the second dielectric layer [610] has a thickness between 2 nm and 10 nm [Paras.33-34].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. Pub. 2021/0082832) in view of Clark (U.S. Pub. 2022/0238323).
Regarding claim 9, Yang [Figs.2-4] discloses a method of processing a substrate, the method comprising:
forming a first recess in a first dielectric layer [210] of the substrate [Fig.2A];
filling the first recess with an electrically conductive material [212-214];
selectively depositing a graphene layer [220] over the electrically conductive material;
selectively depositing a second dielectric layer [222] over the first dielectric layer;
depositing a third dielectric layer [226] over the substrate to cover the graphene layer and the second dielectric layer.
Yang [Fig.3D] [Para.26] discloses one or more etching steps and various etching methods can be used to form the interconnect opening. Yang fails to explicitly disclose the specific etching steps comprising,
performing a first etch process to form a second recess in the third dielectric layer, the recess being aligned with a portion of the first recess; and
performing a second etch process to extend the second recess and expose the graphene layer, the second etch process being selective to the graphene layer.
However, Clark [Figs.5A-J,6-7] discloses and makes obvious the separate etching steps with exposing the next layer to be etched wherein the process comprising,
performing a first etch process to form a second recess in the third dielectric layer, the recess being aligned with a portion of the first recess; and
performing a second etch process to extend the second recess and expose the graphene layer, the second etch process being selective to the graphene layer [302] [Figs.5D-H].
It would have been obvious to include the specific etching steps as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 3-4, 6, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (U.S. Pub. 2021/0082832) in view of Clark (U.S. Pub. 2022/0238323).
Regarding claims 3-4, and 6, Yang [Fig.3D] [Para.26] discloses one or more etching steps and various etching methods can be used to form the interconnect opening. Yang fails to explicitly disclose the claimed specific etching steps. However, Clark [Figs.5A-J,6-7] discloses and makes obvious the separate etching steps with exposing the next layer to be etched wherein the process comprising
wherein the patterning comprises an anisotropic plasma etch using a first plasma, and wherein the extending comprises an isotropic etch that is selective to the graphene layer [Figs.5D-H];
further comprising:
monitoring etch products generated from the patterning [Appears obvious] [Figs.5A-H]; and
terminating the patterning when an element of the second dielectric layer is detected in the etch products [Figs.5D-H];
further comprising:
patterning the fourth dielectric layer [514] to form a recess, the third dielectric layer being exposed at a bottom of the recess after the patterning [Figs.5D-H]; and
patterning the third dielectric layer to extend the recess and expose the graphene layer [Fig.5H].
It would have been obvious to include the specific etching steps as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 8, Yang discloses various dielectric materials can be used, but fails to explicitly disclose the claimed materials of the respective dielectric layers. However, it would be obvious to provide
wherein the first dielectric layer and the third dielectric layer comprise silicon oxide, and wherein the second dielectric layer comprises silicon carbonitride, silicon oxycarbonitride, silicon oxide, titanium oxide, titanium nitride, aluminum oxide, aluminum nitride, or boron nitride.
It is well-known and obvious in semiconductor manufacturing and is well within the general knowledge of one of ordinary skill in the art to use suitable alternative materials for the respective dielectric layers to facilitate selective etching. It would have been obvious to include the claimed materials of the respective dielectric layers, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 13-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clark (U.S. Pub. 2022/0238323).
Regarding claims 13-14, Clark discloses the method further comprising,
prior to depositing the third dielectric layer, depositing an etch stop layer (ESL) [312] over the substrate, and wherein the ESL [312] is exposed at a bottom of the second recess after the first etch process, and wherein the second etch process removes the ESL [Figs.5D-G];
wherein the ESL [312] comprises SiN, SiCN, SiOCN, or SiON [Para.41].
Clark fails to explicitly disclose wherein a top surface of the second dielectric layer is positioned at a same level as a top surface of the graphene layer. However, setting the relative thickness of the second dielectric layer to be at a same level as a top surface of the graphene layer would be well-known and obvious in semiconductor manufacturing and is well within the general knowledge of one of ordinary skill in the art. It would have been obvious to provide the relative heights as claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim(s) 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Clark (U.S. Pub. 2022/0238323).
Regarding claim 21, Clark [Figs.3-7] discloses a method of processing a substrate, the method comprising:
forming a pattern of an electrically conductive layer over the substrate, the electrically conductive layer and a first dielectric layer being exposed at a surface of the substrate;
selectively depositing a graphene layer over the electrically conductive layer relative to the first dielectric layer;
selectively depositing a second dielectric layer over the first dielectric layer relative to the graphene layer, wherein a top surface of the second dielectric layer is positioned higher than a top surface of the graphene layer;
depositing a third dielectric layer over the substrate, the third dielectric layer covering the second dielectric layer and the graphene layer;
performing a first etch process to form a recess in the third dielectric layer, the recess being aligned with a portion of the pattern of the electrically conductive layer;
performing a second etch process selective to the graphene layer to extend the recess and expose the graphene layer.
Clark [Figs.3-7] discloses a method as discussed above in the treatment of claims 9-10. Clark fails to explicitly disclose monitoring etch products generated from the first etch process;
terminating the first etch process when an element of the second dielectric layer is detected in the etch products.
Clark [Para.47] discloses suitable etch technique, anisotropic reactive ion etching (RIE), and including one or more steps having different etch chemistries. It would be obvious to provide monitoring etch products generated from the first etch process; and terminating the first etch process when an element of the second dielectric layer is detected in the etch products. It has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claims 22-25, Clark [Figs.3-7] discloses a method of processing a substrate,
further comprising:
depositing an etch stop layer (ESL) over the substrate after selectively depositing the second dielectric layer and prior to depositing the third dielectric layer, the ESL covering the graphene layer and the second dielectric layer, wherein the first etch process exposes the ESL at a bottom of the recess, and wherein the second etch process removes the ESL and exposes the graphene layer [Discussed above];
wherein the ESL comprises silicon nitride, silicon carbonitride, silicon oxycarbonitride, or silicon oxynitride, and has a thickness between 2 nm and 5 nm [Discussed above];
wherein:
the first etch process comprises an anisotropic plasma etch,
the second etch process comprises an isotropic etch [Clark [Para.47] discloses suitable etch technique, anisotropic reactive ion etching (RIE), and including one or more steps having different etch chemistries], and
the second dielectric layer has a thickness between 2 nm and 10 nm [Discussed above];
further comprising:
depositing a fourth dielectric layer [514] over the third dielectric layer [510],
wherein the first etch process patterns the fourth dielectric layer and partially etches into the third dielectric layer to form an initial recess, and wherein the first etch process is terminated when the element of the second dielectric layer is detected in the etch products, the third dielectric layer providing etch resistance to slow an etch rate as the first etch process approaches the second dielectric layer [Figs.5D-F] [Clark [Para.47] discloses suitable etch technique, anisotropic reactive ion etching (RIE), and including one or more steps having different etch chemistries];
wherein:
the third dielectric layer comprises a first silicon oxide having a first density,
the fourth dielectric layer comprises a second silicon oxide having a second density lower than the first density
[specifying known materials for the respective dielectric layers is well-known and obvious in semiconductor manufacturing and is well within the general knowledge of one of ordinary skill in the art. It would have been obvious to provide the dielectric materials claimed, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007)], and
the second dielectric layer comprises silicon carbonitride, silicon oxycarbonitride, titanium oxide, titanium nitride, aluminum oxide, aluminum nitride, or boron nitride [Discussed above].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BAC H AU/Primary Examiner, Art Unit 2898
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