Prosecution Insights
Last updated: October 01, 2026
Application No. 18/366,531

Dopant Concentration Boost in Epitaxially Formed Material

Non-Final OA §102§112
Filed
Aug 07, 2023
Priority
Nov 29, 2016 — provisional 62/427,752 +2 more
Examiner
ISAAC, STANETTA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
4 (Non-Final)
86%
Grant Probability
Favorable
4-5
OA Rounds
0m
Est. Remaining
50%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
838 granted / 977 resolved
+17.8% vs TC avg
Minimal -36% lift
Without
With
+-36.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
39 currently pending
Career history
1027
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
44.3%
+4.3% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 977 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the amendment filed on 7/15/26. Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 7/15/26 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 21-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In claim 21, lines 12-13, it is unclear how during the repeated step of step (b) would occur since in lines 4-5, “(b) the epitaxially growing of the doped layer is formed directly on the substrate in the recess by interacting materials of a precursor fluid with the material of the substrate”. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 33-40 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (US PGPub 2015/0255606, hereinafter referred to as “Cheng”). Cheng discloses the semiconductor method as claimed. See figures 1-9 and corresponding text, where Cheng teaches, in claim 33, a method comprising: forming a recess (S1) in a substrate (3), the recess having a bottom and sidewalls extending to the top of the recess (S1); (figures 5-9; [0037-0060]) forming a lined recess by lining the bottom and the entire sidewalls of the recess with a bottommost layer (10) in direct contact with the substrate (3), the bottommost layer (10) comprising semiconductor material doped with a first dopant species to a predetermined dopant concentration; at least partially filling the lined recess with semiconductor material by repeating a pattern of alternately epitaxially growing respective boosting layers (11), substantially free of the first dopant species, and respective first layers doped with the first dopant species, followed by epitaxially growing respective boosting layers, substantially free of the first dopant species, until a desired portion of the recess is filled, wherein the respective boosting layers have a high concentration of unbound first dopant bonding sites relative to respective doped first layers, and wherein each of the respective boosting layers is sandwiched between respective first layers or between one of the respective first layers (12) and the bottommost layer (10); (figure 8; [0053-0060]) and activating the first dopant species to diffuse from respective first layers to respective unbound first dopant bonding sites in the respective boosting layers. Cheng teaches, in claim 34, wherein epitaxially growing respective first layers doped with a first dopant species is performed in a first process chamber while a first dopant based vapor is being introduced into the first process chamber, and further wherein epitaxially growing respective boosting layers is performed in the first process chamber while the first dopant based vapor is being withheld from the first process chamber (figures 5-9; [0037-0060]). Cheng teaches, in claim 36, wherein respective first layers are lattice mismatched to respective boosting layers (figures 5-9; [0037-0060]). Cheng teaches, in claim 36, wherein a ratio of thicknesses of respective first layers to respective boosting layers is in a range of from 10:1 to 2:1 (figures 5-9; [0037-0060]). Cheng teaches, in claim 37, wherein respective first layers are epitaxially grown conformally on a bottom and sidewalls of the recess (figures 5-9; [0037-0060]). Cheng teaches, in claim 38, a method comprising: (figures 5-9; [0037-0060]) forming a recess (S1) in a semiconductor substrate (3), the recess having a bottom surface and having sidewalls extending to a topmost surface of the substrate; epitaxially growing a first layer (100 of doped material in contact with the substrate in the recess, the doped material comprising a semiconductor material and a first dopant, the doped material lining the bottom of the recess and the sidewalls of the recess and extending along the sidewalls to the topmost surface of the substrate; epitaxially growing a boosting layer (11) on the first layer of doped material in the recess, wherein the boosting layer has a high concentration of unbound dopant bonding sites relative to the first layer of doped material; growing a second layer (12) of the doped material on the boosting layer (figure 8; [0053-0060]); and activating dopants in the first layer of doped material and the second layer of the doped material to bond with unbound dopant bonding sites in the boosting layer. Cheng teaches, in claim 39, wherein prior to the step of activating, the boosting layer is substantially free of the first dopant (figures 5-9; [0037-0060]). Cheng teaches, in claim 40, further comprising removing portions of the boosting layer during the process of epitaxially growing the boosting layer (figures 5-9; [0037-0060]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at 571-270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STANETTA D ISAAC/Examiner, Art Unit 2898 August 8, 2026
Read full office action

Prosecution Timeline

Show 4 earlier events
Dec 18, 2024
Response Filed
Oct 06, 2025
Non-Final Rejection mailed — §102, §112
Jan 05, 2026
Response Filed
May 05, 2026
Final Rejection mailed — §102, §112
Jul 06, 2026
Response after Non-Final Action
Jul 15, 2026
Request for Continued Examination
Jul 22, 2026
Response after Non-Final Action
Aug 12, 2026
Non-Final Rejection mailed — §102, §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751037
MONOLITHIC FIELD-EFFECT TRANSISTOR-ANTENNA DEVICE FOR TERAHERTZ WAVE DETECTION WITH INDEPENDENT PERFORMANCE PARAMETERS
4y 7m to grant Granted Sep 29, 2026
Patent 12751310
DICING DIE ATTACH FILM AND METHOD OF PRODUCING THE SAME, AND SEMICONDUCTOR PACKAGE AND METHOD OF PRODUCING THE SAME
4y 4m to grant Granted Sep 29, 2026
Patent 12733494
SEMICONDUCTOR ELEMENT BONDING PORTION AND SEMICONDUCTOR DEVICE
4y 7m to grant Granted Sep 08, 2026
Patent 12733528
MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
3y 10m to grant Granted Sep 08, 2026
Patent 12720899
METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE, SEMICONDUCTOR PACKAGE, AND IMAGING APPARATUS
4y 3m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

4-5
Expected OA Rounds
86%
Grant Probability
50%
With Interview (-36.2%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 977 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month