DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 39-58 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Molnar et al. (US 20230187407 A1; Molnar).
Regarding claim 39, Molnar discloses an integrated circuit device (Fig. 2B, 100; ¶114) comprising: a first active circuitry (Fig. 2B, 104; ¶ 120) in a device portion of the integrated circuit device; a first non-conductive layer (Fig. 2B, 238; ¶120) over the device portion, the first non-conductive layer at least partially defining a direct bonding surface (Fig. 2B, 230; ¶ 118) of the integrated circuit device; and a trace line (Fig. 2B, not shown; ¶120) connected to the first active circuitry and extending at least partially into the first non-conductive layer, wherein the trace line is configured to provide electrical communication between the first active circuitry and a debugging chip (Fig. 2B, 102; ¶ 96), the trace line terminating at or below (via portion of metallization routing connected to 230) the direct bonding surface.
Regarding claim 40, Molnar discloses the integrated circuit device of Claim 39, further comprising a plurality of contact features (Fig. 2B, end of via portion of metallization routing connected to 230; ¶ 118) at least partially embedded within the first non-conductive layer (Fig. 2B, 238; ¶120), the plurality of contact features (The plurality of contact featured between 102 and 236)
configured to connect only to corresponding contact features (Fig. 2B, 230 contacts of 102; ¶ 115) of the debugging chip. (Fig. 2B, 102; ¶ 96)
Regarding claim 41, Molnar discloses the integrated circuit device of Claim 40, wherein the first non-conductive layer (Fig. 2B, 238; ¶120) comprises a bonding surface (Fig. 2B, 228; ¶118) prepared for direct hybrid bonding (¶118).
Regarding claim 42, Molnar discloses the integrated circuit device of Claim 40, wherein the plurality of contact features (Fig. 2B, 230 contacts of 104; ¶ 118) is connected to the trace line. (Fig. 2B, 238 metallization routing connected to 230; ¶ 118)
Regarding claim 43, Molnar discloses the integrated circuit device of Claim 40, further comprising a second non- conductive layer (Fig. 2B, 232; ¶119) over the first non-conductive layer. (Fig. 2B, 238; ¶120)
Regarding claim 44, Molnar discloses the integrated circuit device of Claim 39, wherein the trace line (Fig. 2B, 238 a horizontal portion connected; ¶ 118) terminates at or below a bonding surface (Fig. 2B, 230; ¶ 118) of the integrated circuit device (Fig. 2B, 104; ¶ 120), the trace line not (physically) connected to a contact pad at the bonding surface (Fig. 2B, 230; ¶ 118) of the integrated circuit device.
Regarding claim 45, Molnar discloses an integrated circuit comprising the integrated circuit device of Claim 39, the bonded structure further comprising a debugging element (Fig. 2B, 102; ¶ 96) directly bonded (Fig. 2B, DTD; ¶ 118) to the integrated circuit device (Fig. 2B, 104; ¶ 120) , wherein a first non-conductive layer (Fig. 2B, 238; ¶ 118) of the integrated circuit device is directly bonded to a second non-conductive layer (Fig. 2B, 220; ¶ 117) of the debugging element without an intervening adhesive (DTD ¶118) ; and wherein a first contact feature (Fig. 2B, lower contact of 218 of 230 similar to 250; ¶ 118) of the integrated circuit device is directly bonded to a second contact feature (Fig. 2B, upper contact of 218 of 230 similar to 250; ¶ 118) of the debugging element without an intervening adhesive.
Regarding claim 46, Molnar discloses the integrated circuit of Claim 45, wherein the debugging chip (Fig. 2B, 102; ¶ 96) is configured to debug the first active circuitry. (Fig. 2B, 104; ¶ 120)
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 47, Molnar discloses a bonded structure comprising: an integrated circuit device (Fig. 2B, 104; ¶ 120) comprising first active circuitry; and a debugging element (Fig. 2B, 102; ¶ 96) comprising debugging circuitry, the debugging element directly bonded (Fig. 2B, 230; ¶ 118) to the integrated circuit device without an adhesive along a bonding interface; wherein the debugging circuitry is configured to debug logic of first active circuitry of the integrated circuit device.
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 48, Molnar discloses the bonded structure of Claim 47, wherein the debugging element (Fig. 2B, 102; ¶ 96) comprises a chip.
Regarding claim 49, Molnar discloses the bonded structure of Claim 47, wherein a first non-conductive bonding layer (Fig. 2B, lower oxide 230; ¶ 118) of the integrated circuit device (Fig. 2B, 104; ¶ 120) is directly bonded to a second non-conductive bonding layer (Fig. 2B, upper oxide 230; ¶ 118) of the debugging element (Fig. 2B, 102; ¶ 96) without an intervening adhesive (hybrid bonding ¶118); and wherein a first contact feature (Fig. 2B, lower contact of 230; ¶ 118) of the integrated circuit device is directly bonded to a second contact feature (Fig. 2B, upper contact of 230; ¶ 118) of the debugging element without the intervening adhesive (hybrid bonding ¶118).
Regarding claim 50, Molnar discloses the bonded structure of Claim 49, wherein a majority of the first and second contact features (Fig. 2B, 230; ¶ 118) are configured to debug (¶96) at least a portion of the first active circuitry of the integrated circuit device. (Fig. 2B, 104; ¶ 120)
Regarding claim 51, Molnar discloses the bonded structure of Claim 50, wherein debugging (Fig. 2B, 102; ¶ 96) at least a portion of the first active circuitry (Fig. 2B, 104; ¶ 120) comprises probing the first active circuitry so as to produce a one or more signals from the first active circuitry; collecting the one or more signals; storing the one or more signals; and analyzing the one or more signals. (product by process)
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 52, Molnar discloses the bonded structure of Claim 51, wherein the debugging circuitry (¶96) is configured to transmit (through direct bond 230) one or more signals to the first active circuitry.
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 53, Molnar discloses the bonded structure of Claim 52, wherein the one or more signals (Fig. 2B, through the plurality of contacts 230; ¶ 118) probe one or more portions of the first active circuitry. (Product by process)
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 54, Molnar discloses a debugging chip comprising: a debugging circuitry; wherein the debugging circuitry (Fig. 2B, 102; ¶ 96) is configured to debug a circuitry of an element (Fig. 2B, 104; ¶ 120) directly bonded (hybrid bonding ¶118) to the debugging chip, wherein debugging the circuitry of the element comprises analyzing signals emitted from the element (the nature of debugging circuitry); and a bonding layer (Fig. 2B, 230; ¶ 118) configured for direct hybrid bonding without an adhesive, the bonding layer comprising a non-conductive bonding layer (oxide-oxide; ¶118) and a plurality of contact (metal to metal; ¶118) features at least partially embedded within the non-conductive bonding layer.
Regarding claim 55, Molnar discloses the debugging chip of Claim 54, wherein the debugging chip (Fig. 2B, 102; ¶ 96) is directly bonded to an integrated circuit device (Fig. 2B, 104; ¶ 120), without an adhesive (hybrid bonding; ¶118), wherein the integrated circuit device comprises an active circuitry.
Regarding claim 56, Molnar discloses the debugging chip of Claim 55, wherein the debugging circuitry (Fig. 2B, 102; ¶ 96) is configured (the nature of debugging circuitry) to probe the active circuitry (Fig. 2B, 104; ¶ 120) of the integrated circuit device.
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 57, Molnar discloses the debugging chip of Claim 56, wherein the debugging circuitry (Fig. 2B, 102; ¶ 96) is configured to store signals produced from the active circuitry of the integrated circuit device. (Fig. 2B, 104; ¶ 120)
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Regarding claim 58, Molnar discloses the debugging chip of Claim 57, wherein the debugging circuitry (Fig. 2B, 102; ¶ 96) is configured to manipulate signals produced from the active circuitry of the integrated circuit device. (Fig. 2B, 104; ¶ 120)
The way a debugging circuit works is to monitor (probe), control (manipulate), and analyze code execution (signals) directly. This process involves analyzing signals through probing contacts.
Also, the presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product.
Conclusion
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899