DETAILED ACTION
This Office Action is in response to RCE filed March 5, 2026.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 31 are objected to because of the following informalities:
On line 9 of claim 1, “the pair of metal contacts comprises” should be replaced with “the pair of metal contacts comprise”, because “the pair of metal contacts” is a plural noun.
On line 33 of claim 31, “layerin” should be replaced with “layer in”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 and 21-34 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
(1) Regarding claim 1, Applicants did not originally disclose that “a length of the bottom surface of the first outer portion in the first direction is less than one-half a width of the first portion of the patterned second oxide semiconductor layer in the first direction” as recited on lines 23-25, and “a length of the bottom surface of the second outer portion in the first direction is less than one-half a width of the second portion of the patterned second oxide semiconductor layer in the first direction” as recited on lines 30-32, because (a) these limitations recite that the length of the bottom surface of the “1st outer” that is not in contact with the patterned gate electrode 102 in the first or lateral direction is less than one-half the width of the “1st” in the first direction illustrated below,
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(b) however, the limitation cited above is based on an assumption or hypothesis that the drawings of current application are exactly to the scale, which Applicants did not originally disclose, (c) rather, Applicants originally disclosed in paragraph [0066] of current application that “Referring to FIG. 7A, the patterned photoresist layer (not shown) may be used as a mask to etch the continuous high k dielectric layer 104L and the continuous first oxide semiconductor layer 106L such that a patterned high-k dielectric layer 104 and a patterned first oxide semiconductor layer 106 are formed”, that “In various embodiments, the patterned high-k dielectric layer 104 and the patterned first oxide semiconductor layer 106 may be longer in length than the patterned gate electrode 102 as illustrated in FIG. 7A”, and that “However, in alternative embodiments, the patterned high-k dielectric layer 104 and the patterned first oxide semiconductor layer 106 may be the same length as or shorter than the patterned gate electrode 102 (emphasis added)”, (d) in addition, Applicants originally disclosed in paragraph [0073] of current application that “In various embodiments, the length Lchan of the channel region may be in the range of 15-150 nm, such as 25-100 nm, although longer or shorter channel regions may be formed”, and that “In various embodiments, the length LS/D of the active regions may be in the range of 15-150 nm, such as 25-100 nm, although longer or shorter active regions may be formed” describing Fig. 11 of current application, (e) therefore, it is clear that Applicants were noncommittal to the relative sizes of the patterned gate electrode 102, the patterned high-k dielectric layer 104 and the patterned first oxide semiconductor layer 106 in view of the sentences of paragraph [0066] of current application cited above, (f) furthermore, even though Applicants originally disclosed in paragraph [0073] of current application that the length Lchan of the channel region and the length LS/D of the active regions are in the same range in paragraph [0073] of current application, the length LS/D of the active regions is clearly much shorter than the length Lchan of the channel region as illustrated below,
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(g) in other words, when Applicants originally filed drawings of current application, Applicants did not actually pay attention to the relative sizes of the later sizes of the claimed component layers, and thus the limitations “a length of the bottom surface of the first outer portion in the first direction is less than one-half a width of the first portion of the patterned second oxide semiconductor layer in the first direction” recited on lines 23-25, and “a length of the bottom surface of the second outer portion in the first direction is less than one-half a width of the second portion of the patterned second oxide semiconductor layer in the first direction” recited on lines 30-32 solely based on the not-to-the scale drawing of Fig. 12A of current application fails to comply with the written description requirement, and (h) furthermore, Applicants originally disclosed in paragraph [0073] of current application that “In various embodiments, the ratio of a thickness tS/D of the source/drain regions to the thickness tchan of the channel region may be in the range of 150:2 to 15:8”, which clearly shows that Fig. 12A of current application is not to the scale in the vertical direction, either since Fig. 12A appears to show that the ratio of a thickness tS/D of the source/drain regions to the thickness tchan of the channel region is 2:1 as the thickness of the layer 106 is the same with the thickness of the layer 112 as illustrate below.
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(2) Further regarding claim 1, Applicants did not originally disclose that “a length of the bottom surface of the first outer portion in the first direction is less than one-half a width of the first portion of the patterned second oxide semiconductor layer in the first direction” as recited on lines 23-25, and “a length of the bottom surface of the second outer portion in the first direction is less than one-half a width of the second portion of the patterned second oxide semiconductor layer in the first direction” as recited on lines 30-32, because (a) the value “one-half” is an arbitrarily assigned value by Applicants after multiple prior art rejections since Applicants did not originally disclose any specific numerical value of the ratio between the claimed length and the claimed width, (b) as can be clearly seen in the illustration below, the claimed length of the bottom surface of the first outer portion in the first direction is less than 1/3 of the width of the first portion of the patterned second oxide semiconductor layer, see the four arrows with the same length illustrated below,
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(c) therefore, it is clear that Applicants simply arbitrarily assigned the relative size of the claimed length and the claimed width that Applicants did not originally disclose, and Applicants do not even claim that “a length of the bottom surface of the first outer portion in the first direction is less than” one-third “a width of the first portion of the patterned second oxide semiconductor layer in the first direction”, and “a length of the bottom surface of the second outer portion in the first direction is less than” one-third “a width of the second portion of the patterned second oxide semiconductor layer in the first direction”, which are more closely associated with what Applicants showed in the drawings as illustrated above, and (d) therefore, the two limitations cited above are directed to a configuration of the claimed transistor whose scope is much broader than what one may assume from the drawings of current application, rendering claim 1 noncompliant with the written description requirement.
(3) Regarding claims 21 and 31, Applicants did not originally disclose that “a length of the bottom surface of the first outer portion in the first direction is less than one-half a width of the first layer of the pair of second oxide semiconductor layers in the first direction” as recited on lines 25-27 of claim 21, “a length of the bottom surface of the second outer portion in the first direction is less than one-half a width of the second layer of the pair of second oxide semiconductor layers in the first direction” as recited on lines 33-34 of claim 21, “a length of the bottom surface of the first outer portion in the first direction is less than one-half a width of the first portion of the second oxide semiconductor layer in the first direction” as recited on lines 24-26 of claim 31, and “a length of the bottom surface of the second outer portion in the first direction is less than one-half a width of the second portion of the second oxide semiconductor layerin [sic] the first direction” as recited on lines 31-33 of claim 31 for the same reasons stated above. Claims 22-30 depend on claim 21, and claims 32-34 depend on claim 31, therefore, claims 22-30 and 32-34 also fail to comply with the written description requirement.
(4) Regarding claim 22, Applicants did not originally disclose that “a length of the first end portion of the metal layer is greater than the length of the bottom surface of the first outer portion of the first dielectric layer” recited on lines 4-5, and “a length of the second end portion of the metal layer is greater than the length of the bottom surface of the second outer portion of the first dielectric layer” recited on lines 7-8, because these limitation are solely derived from Fig. 12A of current application, which again is not drawn to the scale, and thus fail to comply with the written description requirement for the same reasons stated above. Claim 23 depends on claim 22, and therefore, claim 23 also fail to comply with the written description requirement.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 21-34 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
(1) Regarding claim 1, it is not clear how “a second outer portion” can include “a bottom surface extending in the first direction from a second outer sidewall of the dielectric layer to a second outer sidewall of the patterned gate electrode (emphasis added)” as recited on lines 26-29 when “a first outer portion” includes “a bottom surface extending in the first direction from a first outer sidewall of the dielectric layer to a first outer sidewall of the patterned gate electrode (emphasis added)” as recited on lines 19-22, because (a) it does not appear that the first and second outer portions can each include a bottom surface extending in the same first direction, and (b) rather, it appears that the bottom surface of the first outer portion of the dielectric layer and the bottom surface of the second outer portion of the dielectric layer should extend in opposite directions.
(2) Regarding claims 21 and 31, it is not clear how “a second outer portion” can include “a bottom surface extending in the first direction from a second outer sidewall of the first dielectric layer to a second outer sidewall of the metal layer (emphasis added)” as recited on lines 28-31 of claim 21 when “a first outer portion” includes “a bottom surface extending in the first direction from a first outer sidewall of the first dielectric layer to a first outer sidewall of the metal layer (emphasis added)” as recited on lines 21-23 of claim 21, and how “a second outer portion” can include “a bottom surface extending in the first direction from a second outer sidewall of the gate dielectric layer to a second outer sidewall of the gate electrode (emphasis added)” as recited on lines 27-30 of claim 31 when “a first outer portion” includes “a bottom surface extending in the first direction from a first outer sidewall of the gate dielectric layer to a first outer sidewall of the gate electrode (emphasis added)” as recited on lines 20-23 of claim 31 for the same reasons stated above. Claims 22-30 depend on claim 21, and claims 32-34 depend on claim 31, therefore, claims 22-30 and 32-34 are also indefinite.
Response to Arguments
Applicants’ arguments with respect to claims 1, 21 and 31 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicants’ arguments traversing the 35 USC 112(a) rejections included in the REMARKS filed March 5, 2026 are not persuasive for the following reasons: (a) Applicants’ arguments are primarily based on the allegations on pages 12-13 of the REMARKS based on the PTAB decision issued on July 27, 2022, (b) however, the PTAB decision and the newly added limitations recited in claims 1, 21 and 31 involving the arbitrarily assigned numerical value of “one-half” are totally distinct from each other in terms of the specificity of the claimed relative sizes, (c) in other words, the limitation “a height of the wing is greater than a width of the wing” considered for the PTAB decision and the limitations “a length of the bottom surface of the first outer portion in the first direction is less than one-half a width of the first portion of the patterned second oxide semiconductor layer in the first direction” recited on lines 23-25 of claim 1, and “a length of the bottom surface of the second outer portion in the first direction is less than one-half a width of the second portion of the patterned second oxide semiconductor layer in the first direction” as recited on lines 30-32 of claim 1 are very distinct from each other in terms of their specificity of the claimed relative sizes, (d) furthermore, the art associated with the PTAB decision and the art of current application are directed to totally distinct fields of endeavors, and the structure considered by the PTAB appears to be a macroscopic structure, while the structure of current application is a microscopic structure with totally different sets of parameters to be considered, (e) for example, current application is directed to a transistor, and therefore, the rationales of selecting the relative sizes of the gate electrode 102, the dielectric layer 104 and the channel layer 106, and the second oxide semiconductor layer 112 shown in Fig. 12A of current application would be totally different from the rationale of selecting the relative size of the height and width of the wing for the application considered by the PTAB, and therefore, Applicants’ arguments solely based on two distinct structures with very distinct overall sizes and very distinct device parameters in the REMARKS are not persuasive, (f) in other words, while the relative sizes of the component layers of current application would alter a threshold voltage, a current flow density, a mobility of electrical charges, etc., the relative size of the width and height of the wing in the application considered by the PTAB does not lead to such distinct characteristics of the apparently macroscopic structure, (g) furthermore, the numeral value of “one-half” is arbitrarily selected by Applicants without any basis, and as discussed above under 35 USC 112(a) rejections, a numeral value more closely aligned with the claimed relative size is one-third, and (h) finally, as the Examiner discussed above under 35 USC 112(a) rejections, Applicants were noncommittal to the relative sizes of the claimed component layers since Applicants simply list all the possible relative sizes of the claimed component layers rather than any specific ranges of the relative sizes of the claimed component layers.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C KIM whose telephone number is (571) 270-1620. The examiner can normally be reached 8:00 AM - 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached on (571) 270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C KIM/Primary Examiner, Art Unit 2815
/J.K./Primary Examiner, Art Unit 2815 July 8, 2026
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