Prosecution Insights
Last updated: April 19, 2026
Application No. 18/366,771

Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same

Non-Final OA §102§103
Filed
Aug 08, 2023
Examiner
KLEIN, JORDAN M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
3 (Non-Final)
85%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
94%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allow Rate
451 granted / 528 resolved
+17.4% vs TC avg
Moderate +8% lift
Without
With
+8.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
21 currently pending
Career history
549
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
48.8%
+8.8% vs TC avg
§102
33.2%
-6.8% vs TC avg
§112
13.6%
-26.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 528 resolved cases

Office Action

§102 §103
DETAILED ACTION This Office Action is in response to the applicant's amendment entered with the RCE filed 16 February 2026. In virtue of this communication, claims 1-11, 13-15, and 17-22 are currently presented in the instant application. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 8, 9, 11, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2015/0235922 A1; hereinafter Chen). With respect to claim 8, Chen teaches a device in at least Fig. 5 and paragraph 57 comprising: a first dielectric layer 52 over a substrate 20; a first interconnect 34 in the first dielectric layer 52; a second dielectric layer (54, 56) over the first dielectric layer 52 and the first interconnect 34; a conductive feature 14 in the first dielectric layer 52 and the second dielectric layer (54, 56), wherein an upper surface of the conductive feature 14 is level with an upper surface of the second dielectric layer (54, 56); a third dielectric layer 58 over the second dielectric layer (54, 56) and the conductive feature 14; a fourth dielectric layer 60 over the third dielectric layer 58; and a second interconnect (12, 40) in the fourth dielectric layer 60, the second interconnect (12, 40) extending through the fourth dielectric layer 60, the third dielectric layer 58, and the second dielectric layer (54, 56), the second interconnect (12, 40) physically contacts the first interconnect 34, wherein the second interconnect (12, 40) has a first width (width at 38) at an upper surface of the second dielectric layer (54, 56) and a second width (width at 36) at a lower surface of the second dielectric layer (54, 56), wherein the first width (width at 38) is greater than the second width (width at 36). With respect to claim 9, Chen teaches the device of claim 8, wherein the conductive feature 14 is a through via (see Fig. 5 and paragraphs 53, 56), wherein the conductive feature 14 extends into the substrate 20 (see Fig. 5). With respect to claim 11, Chen teaches the device of claim 8, further comprising: a third interconnect (44, 42 located over 14) in the fourth dielectric layer 60, wherein the third interconnect physically contacts the conductive feature 14. With respect to claim 21, Chen teaches the device of claim 11, wherein the second interconnect (12, 40) and the third interconnect (44, 42 over 14) are part of a single metallization layer (both are part of interconnect structure 40 in 60, see Fig. 5). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-7, 14, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2015/0235922 A1; hereinafter Chen). With respect to claim 1, Chen discloses a device in at least Fig. 5 and paragraph 57; comprising: a substrate 20; a first dielectric layer 52 over the substrate 20; a first interconnect 34 in the first dielectric layer 52; a second dielectric layer (54, 56) over the first dielectric layer 52 and the first interconnect 34; a conductive via 14 extending through the first dielectric layer 52, the second dielectric layer (54, 56) and the substrate 20, a topmost surface of the conductive via 14 being level with a topmost surface of the second dielectric layer 56; a third dielectric layer 58 over the second dielectric layer (54, 56) and the conductive via 14; a fourth dielectric layer 60 over the third dielectric layer 58; and a second interconnect (12, 40) in the fourth dielectric layer 60, the second interconnect comprising a first conductive layer (comprising 44, 42, 86, 98, 38, 36, 86), the first conductive layer being a single continuous conductive layer (single electrically conductive layer), the single continuous conductive layer extending through the fourth dielectric layer 60, the third dielectric layer 58, and the second dielectric layer (54, 56), the single continuous conductive layer physically contacting the first interconnect 34 (44, 42, 86, 98, 38, 36, 86 forms a continuous electrically conductive layer from the top of 60 to interface with 34). Chen does not explicitly mention the first conductive layer around the interconnect in Fig. 5 but Fig. 3B discloses a barrier layer 86 made of electrically conductive materials (see paragraph 34) and Fig. 3F discloses a cap layer 98 also made of electrically conductive material (see paragraph 44). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the single continuous conductive layer would include these additional layers as suggested by Chen as described above and while Chen does not explicitly detail the feature, one of ordinary skill would understand it is taught by the reference (see MPEP 2144 I). With respect to claim 2, Chen discloses the device of claim 1, wherein the second dielectric layer (54, 56) and the third dielectric layer 58 comprise a same material (both comprise etch stop materials). With respect to claim 3, Chen discloses the device of claim 1, wherein the second dielectric layer (54, 56) and the third dielectric layer 58 comprise different materials (note second dielectric layer comprises a dielectric that does not function as an etch stop material). With respect to claim 4, Chen discloses the device of claim 1, wherein the second interconnect (12, 40) narrows as the second interconnect extends through the second dielectric layer (54, 56) toward the first interconnect 34 (note narrow portion at 36). With respect to claim 5, Chen discloses the device of claim 1, further comprising a third interconnect (44, 42 located over 14) in the fourth dielectric layer 60, the third interconnect extending through the third dielectric layer 58 and physically contacting the conductive via 14. With respect to claim 6, Chen discloses the device of claim 5, wherein an upper surface of the third interconnect (44, 42 located over 14) and an upper surface of the second interconnect (12, 40) are level (see Fig. 5). With respect to claim 7, Chen discloses the device of claim 1, wherein a bottommost surface of the conductive via 14 is level with a surface (bottom surface of 20) of the substrate 20. With respect to claim 14, Chen discloses the device of claim 8. Regarding further wherein a thickness of the second dielectric layer is in a range between 200 Å and about 500 Å, Chen is silent. However, the instant specification provides no disclosure that the claimed thickness range is for a particular unobvious purpose, produces an unexpected result, or is otherwise a critical condition. Therefore, it would have been prima facie obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen to achieve Claim 14. The motivation to do so would have been to use routine experimentation to discover optimum or workable ranges for the thickness of the second dielectric layer. In addition, Examiner notes that, since Applicant's disclosure lacks evidence that the claimed thickness range produces an unexpected result, is for a particular unobvious purpose, or is otherwise a critical condition- the claimed thickness range is held to be prima facie obvious without a showing of such evidence (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969); Merck & Co. Inc. V. Biocraft Laboratories Inc., 874F.2d 804, 10 USPQ2d 1843 (Fed. Cir.), cert. denied, 493 U.S. 975 (1989); In re Kulling, 897 F.2d 1147, 14 USPQ2d 1056 (Fed. Cir. 1990); and In re Geisler, 116 F.3d 1465, 43 USPQ2d 1362 (Fed. Cir. 1997); See also MPEP § 2144.05 Section II and Section III). With respect to claim 22, Chen discloses the device of claim 1, wherein the single continuous conductive layer (single electrically conductive layer) extends from an upper surface of the fourth dielectric layer 60 to a bottom surface of the second dielectric layer (54, 56) (44, 42, 86, 98, 38, 36, 86 forms a continuous electrically conductive layer from the top of 60 to interface with 34). Allowable Subject Matter Claims 15 and 17-20 are allowed. Claims 10 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments entered with the RCE dated 02/16/2026 have been fully considered but they are not persuasive. Applicant's arguments amount to a general allegation that the claims define a patentable invention without specifically pointing out how the language of the claims patentably distinguishes them from the references. Applicant's arguments do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections. It is noted that in the amendment to claim 8, while subject matter from claim 12 was added, subject matter from previous claim 8 was removed. Claim 8 remains rejected. Inquiry Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.M.K/Examiner, Art Unit 2893 /SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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Prosecution Timeline

Aug 08, 2023
Application Filed
Jan 11, 2025
Non-Final Rejection — §102, §103
May 09, 2025
Response Filed
Dec 02, 2025
Final Rejection — §102, §103
Feb 04, 2026
Response after Non-Final Action
Feb 16, 2026
Request for Continued Examination
Feb 25, 2026
Response after Non-Final Action
Mar 06, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
85%
Grant Probability
94%
With Interview (+8.2%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 528 resolved cases by this examiner. Grant probability derived from career allow rate.

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