Prosecution Insights
Last updated: October 01, 2026
Application No. 18/366,776

REDUCED CROSS-TALK IN COLOR AND INFRARED IMAGE SENSOR

Non-Final OA §103§112
Filed
Aug 08, 2023
Priority
Mar 30, 2021 — divisional of 12/148,783
Examiner
KIM, JAHAE
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
4m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
35 granted / 48 resolved
+4.9% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
22 currently pending
Career history
75
Total Applications
across all art units

Statute-Specific Performance

§103
52.8%
+12.8% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
28.3%
-11.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 48 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Invention I in the reply filed on 4/22/2026 is acknowledged. Therefore, claims 1-18 and 21-22 have been fully considered in examination. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim 21 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 21 recites “a second absorption structure directly underlying the second image sensor element of the second pixel sensor, wherein the first absorption structure directly contacts the second absorption structure,” which is inconsistent with the specification and drawings. The specification does not describe or depict a second absorption structure underlying the second image sensor element 120b of the second pixel sensor 144b, nor does it describe such a second absorption structure directly contacting the first absorption structure underlying the first image sensor element 120a of the first pixel sensor 144a. Accordingly, this limitation lacks written description support in the specification as originally filed. The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 3, 9, and 21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 3, claim 1 recites that the first absorption structure has “opposing sidewalls” between which the first image sensor element is spaced. It is unclear whether “a sidewall of the first absorption structure,” in claim 3, which allegedly abuts a sidewall of the second absorption structure, refers to one of the previously-recited opposing sidewalls or to a different sidewall of the first absorption structure, rendering the geometric relationship between the first absorption structure and the second absorption structure unclear. Regarding claim 9, there is insufficient antecedent basis for the plural “the first image sensor elements” and “the second image sensor elements,” which follow the singular “a first image sensor element” and “a second image sensor element.” For examination purposes, these are interpreted as the first and second image sensor elements of the respective pixel sensors. Regarding claim 21, it is unclear how the singular “the first image sensor element” can “meet” at a center, and where “a center of the plurality of pixel sensors” is located, as this feature is not defined in the specification. For examination purposes, the limitation is interpreted as the first image sensor elements of the plurality of pixel sensors meeting at a common central region. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-2 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Soda (US 2014/0132812 A1). Regarding claim 1, Soda teaches an image sensor device (solid-state image sensor, FIG. 6B), comprising: a substrate having a front-side surface opposite a back-side surface (semiconductor layer 101 having a first face 1 and a second face 2); an interconnect structure disposed along the front-side surface of the substrate, wherein the interconnect structure comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure (wiring structure WS covers the semiconductor layer 101, wherein the wiring structure WS includes wiring layers 108, 109, 110, contact plugs 104, reflection portions 106, and light absorbing portions 107 in the interlayer insulating film 105, Para [0027-0028]); a first image sensor element disposed within the substrate and configured to generate electrical signals from an electromagnetic radiation within a first range of wavelengths (first photoelectric converter 102 on which light of a first wavelength range, Para [0049]); and the second image sensor element disposed within the substrate and configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths, wherein the second image sensor element is laterally adjacent to the first image sensor element (second photoelectric converter 102 on which light of a second wavelength range, Para [0049]); wherein the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure (first photoelectric converter 102 overlies the first reflection regions RR, including reflection portion 106 and light absorption portion 107, and is spaced laterally between opposing sidewalls of the first reflection regions RR, FIG. 6B). PNG media_image1.png 363 593 media_image1.png Greyscale Regarding claim 2, Soda teaches the image sensor device of claim 1, wherein when viewed from above, an area of the first absorption structure is greater than an area of the first image sensor element (first reflection regions RR extends laterally beyond the first photoelectric converter 102 on opposing sides and thus the area of the first reflection region PR is greater than the area of the first photoelectric converter 102, FIG. 6B). Regarding claim 5, Soda teaches the image sensor device of claim 1, wherein the first absorption structure comprises titanium nitride (the light absorbing portion 107 of the first reflection regions RR is made of an electrical conducting material such as titanium nitride (TiN), Para [0039]). Regarding claim 6, Soda teaches the image sensor device of claim 1, wherein a top surface of the first absorption structure is aligned with a top surface of a first layer of the plurality of conductive wires (first reflection regions RR and the wiring layer 108, which is first layer from the wiring layer 111, are arranged on the same level, Para [0033] and FIG. 6B). Regarding claim 7, Soda teaches the image sensor device of claim 1, wherein the first absorption structure and the plurality of conductive wires respectively comprise a conductive liner and a conductive body (first reflection regions RR comprises reflection portion 106 and light absorption portion 107. Plurality of wiring layer 108 comprise light absorption portions 107, Para [0035]). Regarding claim 8, Soda teaches the image sensor device of claim 1, wherein the first absorption structure is disposed between the plurality of conductive wires and the front-side surface of the substrate (first reflection regions RR is between the wiring layers 108 of FIG. 6B). Claims 4 and 9-18 is rejected under 35 U.S.C. 103 as being unpatentable over Soda (US 2014/0132812 A1) in view of Frey et al. (US 2020/0203401 A1, hereinafter “Frey”). Regarding claim 4, Soda teaches the image sensor device of claim 1, wherein the first absorption structure is configured to interact with the electromagnetic radiation within the first range of wavelengths (Para [0049] and FIG. 6B). But Soda does not specifically teach the first range of wavelengths comprises near infrared (NIR) radiation. However, Frey teaches the first range of wavelengths comprises near infrared (NIR) radiation (a band-pass filter transmitting infrared radiation disposed over the infrared pixel, and a band elimination filter blocking near-infrared radiation disposed over the visible-light pixels, FIG. 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the color filters of Soda to selectively pass and block IR and visible radiation as taught by Frey in order to improve spectral separation and further reduce cross-talk between the infrared and visible-light image sensor elements (Para [0088]), KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP § 2143(A)/(B). Regarding claim 9, Soda teaches an integrated chip (solid-state image sensor 100, FIG. 6B), comprising: a substrate comprising a front-side surface opposite a back-side surface (semiconductor layer 101 having a first face 1 and a second face 2, wherein light from an object is incident on the second face 2); a plurality of pixel devices disposed on the front-side surface of the substrate (a plurality of transistors, including a gate 103 of a transfer transistor, and gates of reset and amplification transistors, arranged on the first face 1 of the semiconductor layer 101, FIG. 6B); an interconnect structure disposed along the front-side surface of the substrate, wherein the interconnect structure comprises a plurality of conductive wires and a plurality of conductive vias disposed within an interconnect dielectric structure and electrically coupled to the plurality of pixel devices (wiring structure WS arranged on the side of the first face 1, comprising wiring layers 108, 109, and 110 within interlayer insulating films 105 and 119, and contact plugs 104 electrically coupling the wiring layer 108 to the gate 103, FIG. 6B); a plurality of pixel sensors disposed within the substrate, wherein the plurality of pixel sensors respectively comprise a first image sensor element and a second image sensor element, wherein the second image sensor element is configured to generate electrical signals from visible light (a first photoelectric converter 102 on which light of a first wavelength range is incident, and a second photoelectric converter 102 on which light of a second wavelength range, e.g., a green (G) or blue (B) visible wavelength range, shorter than the first wavelength range, is incident, third embodiment, FIG. 6B); and a plurality of absorption structures disposed within the interconnect dielectric structure and below the plurality of pixel sensors, wherein the first image sensor elements are respectively laterally spaced between opposing sidewalls of a corresponding absorption structure, and wherein the second image sensor elements are laterally offset from the plurality of absorption structures by a non-zero distance (the reflection portions 106 and light absorbing portions 107 are provided for only the first photoelectric converter (e.g., the longer-wavelength photoelectric converter), such that the first photoelectric converter is laterally spaced between opposing sidewalls of the light absorbing portion 107, and the photoelectric converters for which no reflection portion/light absorbing portion is provided are laterally offset from the absorption structures by a non-zero distance, FIG. 6B). Soda does not specifically teach the first image sensor element is configured to generate electrical signals from infrared (IR) radiation. However, Frey teaches a first image sensor element configured to generate electrical signals from infrared (IR) radiation (a photodetection region configured to detect infrared radiation, e.g., near-infrared radiation, FIG. 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the first image sensor element of Soda to generate electrical signals from IR radiation as taught by Frey, since the first wavelength range of Soda (the longer of the two wavelength ranges) is the wavelength range for which the reflection portion and light absorbing portion are provided to reduce cross-talk, and IR radiation represents a wavelength range longer than visible light for which such absorption is particularly advantageous (Para [0088]), KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP § 2143(A)/(B). Regarding claim 10, Soda in view of Frey teaches the integrated chip of claim 9, wherein the plurality of pixel sensors comprises a first pixel sensor and a second pixel sensor (reference symbols PU, PUR, PL, PC, PR, PDL, and PD denote the positions of the photoelectric converters 102 (pixels) in the imaging region, FIG. 7-10B), wherein the first image sensor element of the first pixel sensor is laterally adjacent to the first image sensor element of the second pixel sensor (array of the plurality of photoelectric converters 102, Para [0055]). Regarding claim 11, Soda in view of Frey teaches the integrated chip of claim 9, wherein the second image sensor element continuously extends from a first sidewall of the first image sensor element to a second sidewall of the first image sensor element, wherein the first sidewall is perpendicular to the second sidewall (FIG. 6B). Regarding claim 12, Soda in view of Frey teaches the integrated chip of claim 9, wherein the plurality of absorption structures are electrically coupled to the plurality of pixel devices by way of the plurality of conductive vias (each reflection portion 106 is formed as part of a wiring pattern for communicating an electric signal, e.g., connected to a gate, source, or drain of a transfer, reset, or amplification transistor by way of a contact plug 104, para [0035] of Soda). Regarding claim 13, Soda in view of Frey teaches the integrated chip of claim 9, wherein the plurality of absorption structures are spaced vertically between the plurality of pixel sensors and the plurality of conductive wires (the reflection portions 106/light absorbing portions 107 are formed in wiring layer 108, which is vertically between the photoelectric converters 102 of the semiconductor layer 101 and the additional conductive wires of wiring layers 109 and 110, FIG. 6B of Soda). Regarding claim 14, Soda in view of Frey teaches the integrated chip of claim 9, wherein the interconnect dielectric structure directly contacts a bottom surface of each absorption structure across an entirety of the bottom surface and directly contacts a top surface of each absorption structure across an entirety of the top surface (interlayer insulating film 119 is arranged between the first face 1 and the reflection portions 106/light absorbing portions 107, directly contacting the light incident surface 131 across its entirety, and interlayer insulating film 105 covers the reflection portions 106 and light absorbing portions 107 to form wiring layer 109, directly contacting the opposite surface across its entirety, FIG. 6B of Soda). Regarding claim 15, Soda in view of Frey teaches the integrated chip of claim 9, further comprising: an isolation structure disposed from the back-side surface of the substrate to a point below the back-side surface, wherein the isolation structure is disposed laterally between the first image sensor element and the second image sensor element of each pixel sensor (One pixel typically includes one photoelectric converter 102, and pixels or elements included in the pixels are electrically isolated from each other by an isolation portion, e.g., a trench-type isolation extending into the semiconductor layer 101, Para [0025] of Soda); and wherein the absorption structures respectively laterally extend between corresponding opposing sidewalls of the isolation structure (the light absorbing portion 107 is arranged around the entire perimeter of the reflection region RR within the pixel region 114, which is bounded by the isolation portion, Para [0025-0034] of Soda). Regarding claim 16, Soda in view of Frey teach the integrated chip of claim 15, wherein the isolation structure comprises a passivation layer and a trench layer, wherein the passivation layer is disposed between the trench layer and the substrate (isolation portion can include an insulator such as LOCOS (LOCal Oxidation of Silicon) or STI (Shallow Trench Isolation), Para [0025] of Soda). Soda does not specifically teach the shallow trench isolation layer comprises a conductive material. However, it was well known in the art to fill an isolation trench with a conductive material over lining passivation insulating layer. It would have been obvious to one of ordinary skill in the art before the affective filing date of the claimed invention to configure the shallow trench isolation structure to comprise a conductive material, since this is a simple substitution of one known trench-fill material to another to achieve the predictable result of electrical isolation, MPEP § 2144.03. Regarding claim 17, Soda in view of Frey teaches the integrated chip of claim 9, further comprising: a light filter array disposed over the front-side surface of the substrate, wherein the light filter array comprises a first light filter overlying the first image sensor element and a second light filter overlying the second image sensor element (a color filter layer can be arranged between the planarizing layer 112 and the microlenses 113). Soda does not specifically teach the first light filter is configured to pass IR radiation and block visible light, and the second light filter is configured to pass visible light and block IR radiation. However, Frey teaches a first light filter configured to pass IR radiation and block visible light overlying an infrared image sensor element, and a second light filter configured to pass visible light and block IR radiation overlying a visible-light image sensor element (a band-pass filter transmitting infrared radiation disposed over the infrared pixel, and a band elimination filter blocking near-infrared radiation disposed over the visible-light pixels, FIG. 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the color filters of Soda to selectively pass and block IR and visible radiation as taught by Frey in order to improve spectral separation and further reduce cross-talk between the infrared and visible-light image sensor elements (Para [0088]), KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007); MPEP § 2143(A)/(B). Regarding claim 18, Soda in view of Frey teaches the integrated chip of claim 17, wherein the second light filter comprises a color filter overlying a band pass filter (a colored filter overlying a band elimination/band-pass interference filter, FIG. 14 of Frey). Claims 3 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Soda (US 2014/0132812 A1) in view of Jang et al. (US 2022/0199670 A1, hereinafter “Jang”). Regarding claim 3, Soda teaches the image sensor device of claim 1, further comprising: a third image sensor element disposed within the substrate and configured to generate electrical signals from the electromagnetic radiation within the first range of wavelengths, wherein the third image sensor element is laterally adjacent to the first image sensor element (third photoelectric converter 102 is laterally adjacent to the first photoelectric converter 102, [0016] and FIG. 6B); and a second absorption structure underlying the third image sensor element (second reflection regions RR, including reflection portion 106 and light absorption portion 107, underlying the third photoelectric converter 102, FIG. 6B). But Soda does not specifically teach a sidewall of the second absorption structure abuts a sidewall of the first absorption structure. However, Jang teaches two adjacent electrically conductive structures disposed within a front-side bonding/interconnect region of a back-side illuminated image sensor, wherein a sidewall of one of the conductive structures directly contacts a sidewall of the other conductive structure (the upper shield structure SU directly contacts the lower shield structure SB, FIG. 3C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the second absorption structure of Soda to directly contact the first absorption structure as taught by Jang, since this represents the combination of prior art elements according to known methods to yield predictable results, namely, continuous and uniform coverage of the underlying image sensor elements by the absorption structures (Para [0074-0075]), MPEP § 2143(A). Regarding claim 21, Soda teaches an integrated chip (solid-state image sensor, FIG. 6B), comprising: a plurality of pixel sensors disposed within a substrate, wherein the plurality of pixel sensors respectively comprise a first image sensor element adjacent to a second image sensor element (array of the plurality of photoelectric converters 102, Para [0055]), wherein the first image sensor element of the pixel sensors meet at a center of the plurality of pixel sensors (reference symbols PU, PUR, PL, PC, PR, PDL, and PD denote the positions of the photoelectric converters 102 (pixels) in the imaging region, FIG. 7-10B), wherein the plurality of pixel sensors comprises a first pixel sensor adjacent to a second pixel sensor (array of the plurality of photoelectric converters 102, Para [0055]); a first absorption structure directly underlying the first image sensor element of the first pixel sensor (first reflection regions RR including reflection portion 106 and light absorption portion 107 overlies the first photoelectric converter 102); and a second absorption structure directly underlying the second image sensor element of the second pixel sensor (second reflection regions RR, including reflection portion 106 and light absorption portion 107, underlying the second photoelectric converter 102, FIG. 6B). Soda does not specifically teach the first absorption structure directly contacts the second absorption structure. However, Jang teaches two adjacent electrically conductive structures disposed within a front-side bonding/interconnect region of a back-side illuminated image sensor, wherein one of the conductive structures directly contacts the other conductive structure (the upper shield structure directly contacts the lower shield structure, FIG. 3C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to configure the reflection regions of Soda to directly contact the conductive structures as taught by Jang, since this represents the combination of prior art elements according to known methods to yield predictable results, namely, continuous and uniform coverage of the underlying image sensor elements by the absorption structures (Para [0074-0075]), MPEP § 2143(A). Regarding claim 22, Soda in view of Jang teaches the integrated chip of claim 21, further comprising: a grid structure overlying the substrate (grid pattern 315, FIG. 3C of Jang), wherein the first image sensor element of the first pixel sensor is spaced between a first pair of opposing sidewalls of the grid structure, wherein the first absorption structure directly underlies both sidewalls in the first pair of opposing sidewalls (Para [0052] and FIG. 3C). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAHAE KIM whose telephone number is (571)270-1844. The examiner can normally be reached M-F 9-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on (571) 271-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /JAHAE KIM/Examiner, Art Unit 2897
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Prosecution Timeline

Aug 08, 2023
Application Filed
Sep 15, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
92%
With Interview (+18.8%)
3y 6m (~4m remaining)
Median Time to Grant
Low
PTA Risk
Based on 48 resolved cases by this examiner. Grant probability derived from career allowance rate.

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