DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Regarding the objections to the drawings in the Office Action filed 5 March 2026, Applicant’s amendments in the reply filed 5 June 2026 are acknowledged and overcome the associated objections. As such, the associated objections are withdrawn.
Regarding the objections to the specification in the Office Action filed 5 March 2026, Applicant’s amendments in the reply filed 5 June 2026 are acknowledged and overcome the associated objections. As such, the associated objections are withdrawn.
Regarding the rejections to the claims under 35 U.S.C. 112(b) in the Office Action filed 5 March 2026, Applicant’s amendments in the reply filed 5 June 2026 are acknowledged and overcome the associated rejections. As such, the associated rejections are withdrawn.
Regarding the rejections to Claims 16 – 20 under 35 U.S.C. 103 in the Office Action filed 5 March 2026, Applicant’s amendments and arguments in the reply filed 5 June 2026 are acknowledged. However, the Applicant’s amendments have changed the scope of the claimed invention and, thus, necessitated a change in scope of the interpretation of the prior art. As such, Applicant’s arguments in this regard are moot in light of KITTL now being used to reject these claims rather than JANG in view of SEO.
Regarding the rejections to Claims 21 – 28 under 35 U.S.C. 103 in the Office Action filed 5 March 2026, Applicant’s amendments and arguments in the reply filed 5 June 2026 are acknowledged. However, the Applicant’s amendments have changed the scope of the claimed invention and, thus, necessitated a change in scope of the interpretation of the prior art. As such, Applicant’s arguments in this regard are moot in light of KITTL now being used to reject these claims rather than XIE in view of SEO.
Regarding the rejections to Claims 29 – 35 under 35 U.S.C. 103 in the Office Action filed 5 March 2026, Applicant’s amendments and arguments in the reply filed 5 June 2026 are acknowledged. However, the Applicant’s amendments have changed the scope of the claimed invention and, thus, necessitated a change in scope of the interpretation of the prior art. As such, Applicant’s arguments in this regard are moot in light of KITTL now being used to reject these claims rather than JANG in view of SEO.
Claim Objections
Claim 16 is objected to because of the following informalities: The amended language reads “wherein the epitaxial seed layer exposes sidewalls…” However, this appears to be a typographical error. For the purposes of examination, the amended language will be interpreted as “wherein forming the epitaxial seed layer exposes sidewalls…”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Examiner’s Note
For the prior art rejection to follow, consider the annotated figure provided below as well as the original figures of KITTL.
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Claim(s) 16 – 18, 21, 23 – 29, & 32 – 37 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by KITTL (US 20170271514 A1).
Regarding Claim 16,
KITTL discloses:
A method (Fig. 3A – 3N), comprising:
forming (Fig. 3A) semiconductor layers (303) one above another over a substrate (304);
performing (Fig. 3C) an etching process (Par. 30) to form a source/drain opening (307) in the semiconductor layers (303) and the substrate (304; Par. 30);
Note, after semiconductor layers 303 are etched, they are relabeled as 309.
forming (Fig. 3F – 3L) an epitaxial seed layer (315’) in the source/drain opening (307),
wherein forming (Fig. 3F – 3L) the epitaxial seed layer (315’) exposes (Fig. 3G & 3I) sidewalls of all of the semiconductor layers (309), and
wherein a bottom surface (BS1) of the epitaxial seed layer (315’) is at a position higher than a topmost surface of the substrate (304), and;
forming (Fig. 3F – 3M) a source/drain epitaxial structure (315) over the epitaxial seed layer (315’) and in contact (indirectly via 315’) with the semiconductor layers (309),
wherein the source/drain epitaxial structure (315) and the epitaxial seed layer (315’) are made of different materials (Par. 34) such that strain is created in the source/drain epitaxial structure (315); and
Note, as per Par. 36, 315 and 315’ may both be a silicon germanium alloy. Regardless, as per Par. 34, 315’ has a higher “defectivity” than 315. Therefore, under a broadest reasonable interpretation, 315 and 315’ are construed to be made of different materials.
Note, due to the difference in the aforementioned “defectivity”, there is a non-zero difference in the spacing of the atoms in the lattices of 315 and 315’. Therefore, there is non-zero lattice mismatch between 315 and 315’, which creates a non-zero strain in both 315 and 315’.
forming (Fig. 3N) a gate structure (323) over the semiconductor layers (309).
Regarding Claim 17,
KITTL discloses:
The method of claim 16,
wherein forming (Fig. 3F – 3L) the epitaxial seed layer (315’) comprises:
depositing an epitaxial material (Par. 33) in the source/drain opening (307); and
etching back (Par. 34) the epitaxial material to expose (Fig. 3G) the sidewalls of the semiconductor layers (309).
Regarding Claim 18,
KITTL discloses:
The method of claim 17,
wherein etching back the epitaxial material is performed until a bottommost one of the semiconductor layers (309) is exposed (Fig. G).
Regarding Claim 21,
KITTL discloses:
A method (Fig. 3A – 3N), comprising:
forming (Fig. 3A) semiconductor layers (303) one above another over a substrate (304);
performing (Fig. 3C – 3D) an etching process (Par. 30 – 31) to form a source/drain opening (307/311/312) in the semiconductor layers (303) and the substrate (304; Par. 30);
Note, after semiconductor layers 303 are etched, they are relabeled as 309.
forming (Fig. 3E) an isolation layer (314) in the source/drain opening (312 of 307/311/312);
forming (Fig. 3F – 3L) an epitaxial material (315’) in the source/drain opening (307 of 307/311/312) and (indirectly) over (portions of) the isolation layer (314),
wherein the epitaxial material (315’) has a concave bottom surface (BS1);
Note, concavity is determined by the sign of the second derivative of a function. As BS1 of 315’ clearly comprises a downward pointing corner point, the second derivative is infinite and positive at that point. Therefore, 315’ has a “concave up” bottom surface.
etching back (Par. 34) the epitaxial material (315’) such that a (portion of a) top surface (Fig. 3F: TS1) of the epitaxial material (315’) is lower than a top surface (Fig. 3F: TS2) of a bottommost one of the semiconductor layers (309);
Note, the final result of said “etching back” process step is shown in Fig. 3G. However, just prior to said “etching back” process step, the structure being formed in this method is at it appears in Fig. 3F. Further, the language of this claim does not require this limitation be satisfied as a final result of said “etching back” process step. That is, this limitation may be satisfied at any point during said “etching back” process step. Therefore, for some non-zero amount of time near the beginning of said “etching back” process step, the structure is substantially similar to how it appears in Fig. 3F, and the above limitation is satisfied.
forming (Fig. 3F – 3M) a source/drain epitaxial structure (315) in the source/drain opening (307) and over the epitaxial material (315’); and
forming (Fig. 3N) a gate structure (323) over the semiconductor layers (309).
Regarding Claim 23,
KITTL discloses:
The method of claim 21,
wherein an air gap (Fig. 3F: AG) is formed vertically between the epitaxial material (315’) and the isolation layer (314).
Note, portions of AG are higher than bottom portions of 315’ and lower than upper portions of 314. Therefore, while not vertically aligned, under a broadest reasonable interpretation, AG is formed vertically between 315’ and 314.
Regarding Claim 24,
KITTL discloses:
The method of claim 23, further comprising
forming (Fig. 3E) an inner spacer (313) between the bottommost one of the semiconductor layers (309) and the substrate (304),
wherein a sidewall of the inner spacer (313) is exposed to the air gap (Fig. 3F: AG).
Regarding Claim 25,
KITTL discloses:
The method of claim 21,
wherein the source/drain epitaxial structure (315) interfaces (electrically via 315’) with the bottommost one of the semiconductor layers (309).
(As seen in Fig. 3M)
Regarding Claim 26,
KITTL discloses:
The method of claim 25,
wherein the epitaxial material (315’) interfaces with the bottommost one of the semiconductor layers (309) and the source/drain epitaxial structure (315).
(As seen in Fig. 3M)
Regarding Claim 27,
KITTL discloses:
The method of claim 21,
wherein the epitaxial material (315’) has a concave (up) bottom surface (BS1) profile.
(As described for Claim 21)
Regarding Claim 28,
KITTL discloses:
The method of claim 21,
wherein after etching back (Fig. 3G) the epitaxial material (315’), the epitaxial material (315’) has a concave (down) top surface profile (As seen in Fig. 3H).
Note, see Claim 21 for an analogous explanation of said concavity for a corresponding concave up bottom surface profile.
Regarding Claim 29,
KITTL discloses:
A method (Fig. 3A – 3N), comprising:
forming (Fig. 3A) semiconductor layers (303) one above another over a substrate (304);
performing (Fig. 3C – 3D) an etching process (Par. 30 – 31) to form a source/drain opening (307/311/312) in the semiconductor layers (303) and the substrate (304; Par. 30);
Note, after semiconductor layers 303 are etched, they are relabeled as 309.
forming (Fig. 3E) an isolation layer (314) in the source/drain opening (312 of 307/311/312);
forming (Fig. 3F – 3L) an epitaxial seed layer (315’) in the source/drain opening (307 of 307/311/312),
wherein the epitaxial seed layer (315’) seals an air gap (Fig. 3F: AG), such that the air gap (AG) is vertically between the epitaxial seed layer (315’) and the isolation layer (314);
Note, portions of AG are higher than bottom portions of 315’ and lower than upper portions of 314. Therefore, while not vertically aligned, under a broadest reasonable interpretation, AG is vertically between 315’ and 314.
forming (Fig. 3F – 3M) a source/drain epitaxial structure (315) over the epitaxial seed layer (315’) and in contact (indirectly via 315’) with the semiconductor layers (309),
wherein a lattice constant of the epitaxial seed layer (315’) is different (Par. 34) from a lattice constant of the source/drain epitaxial structure (315); and
Note, as per Par. 36, 315 and 315’ may both be a silicon germanium alloy. Regardless, as per Par. 34, 315’ has a higher “defectivity” than 315. Therefore, there is a non-zero difference in the spacing of the atoms in the lattices of 315 and 315’. Therefore, at least a local lattice constant of 315’ is different from a local lattice constant of 315.
forming (Fig. 3N) a gate structure (323) over the semiconductor layers (309).
Regarding Claim 32,
KITTL discloses:
The method of claim 29,
wherein an entirety of the epitaxial seed layer (315’) is spaced apart from the isolation layer (314) through the air gap (AG).
(As seen in Fig. 3F)
Regarding Claim 33,
KITTL discloses:
The method of claim 29,
wherein the source/drain epitaxial structure (315) has a higher germanium concentration than the epitaxial seed layer (315’).
Note, under a broadest reasonable interpretation, a germanium concentration may be the ratio of the number of germanium atoms in the source/drain opening to the total volume of the source/drain opening. Therefore, at least at the end of the step portrayed in Fig. 3G where all or substantially all—Par. 34—of 315’ has been etched away, 315 clearly comprises more germanium atoms in the total volume of the source/drain opening than 315’. As such, at least at this point in the method, 315 has a higher germanium concentration than 315’.
Regarding Claim 34,
KITTL discloses:
The method of claim 29,
wherein (a portion of a) a top surface (Fig. 3F: TS1) of the epitaxial seed layer (315’) is lower than a top surface (Fig. 3F: TS2) of a bottommost one of the semiconductor layers (309).
Regarding Claim 35,
KITTL discloses:
The method of claim 29,
wherein a bottom surface (Fig. 3F: BS1) of the epitaxial seed layer (315’) is higher than a top surface of the substrate (304).
Regarding Claim 36,
KITTL discloses:
The method of claim 29, further comprising
forming (Fig. 3E) an inner spacer (313) between a bottommost one of the semiconductor layers (309) and the substrate (304),
wherein the inner spacer (313) is exposed to the air gap (Fig. 3F: AG).
Regarding Claim 37,
KITTL discloses:
The method of claim 29,
wherein the epitaxial seed layer (315’) has a concave (up) bottom surface and a concave (down) top surface.
Note, for an explanation of the concavities, see Claim 21.
Allowable Subject Matter
Claims 19 – 20 & 22 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is KITTL (US 20170271514 A1).
KITTL discloses:
A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a substrate. The method includes deep etching portions of the stack to form electrode recesses for a source electrode and a drain electrode, forming conductive passivation layers in the electrode recesses, and epitaxially growing the source and drain electrodes in the electrode recesses. Each conductive passivation layer extends at least partially along a side of one of the electrode recesses. Portions of the substrate at lower ends of the electrode recesses are uncovered by the conductive passivation layers. The source and drain electrodes are grown from the substrate and the conductive passivation layers substantially inhibit the source and drain electrodes from being grown from the channel layers.
Regarding Claim 19 and its dependent claim, Claim 20,
There is no teaching or prior art to provide:
The method of claim 16,
wherein prior to forming the epitaxial seed layer the method further comprises:
forming an epitaxial layer in a bottom portion of the source/drain opening; and
forming an isolation layer over the epitaxial layer.
Regarding Claim 22,
There is no teaching or prior art to provide:
The method of claim 21, further comprising,
prior to forming the isolation layer, forming an epitaxial layer in the source/drain opening.
Missing elements in the closest prior art gives rise to the innovation in the current invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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