DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II—Claims 16 – 20—and Species II—Fig. 11—in the reply filed on 2 December 2025 is acknowledged.
Applicant’s cancelation of Claims 1 – 15 in the reply filed on 2 December 2025 is acknowledged.
Applicant’s addition of Claims 21 – 35 in the reply filed on 2 December 2025 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on:
8 August 2023
16 October 2024
12 May 2025
have been considered by the examiner.
Drawings
Figures 5 – 10 of the drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the process of making the air gap and the concave surfaces of the epitaxial material must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: GAA-FET SOURCE/DRAINS WITH AIR GAPS AND ETCHED BACK SEED LAYERS
The disclosure is objected to because of the following informalities:
Par. 28 teaches “Reference is made to Fig. 8. A contact etch stop layer (CESL) 155 is formed covering the source/drain epitaxial structures 140. Afterwards, an interlayer dielectric (ILD) layer 152 is formed over the CESL 155.” However, this is inconsistent with Fig. 8 where 155 is formed over 152.
This error is carried forward in the specification. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 34 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 34 recites the limitation "the semiconductor". There is insufficient antecedent basis for this limitation in the claim.
For the purposes of examination, this limitation will be interpreted as “the semiconductor layers”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16, 19, 20, 29 – 32, & 35 are rejected under 35 U.S.C. 103 as being unpatentable over JANG (US 20200220015 A1) in view of SEO (US 20190214314 A1).
Regarding Claim 16,
JANG discloses:
A method (Fig. 14A – 14L), comprising:
forming semiconductor layers (Fig. 14A: 120/141/120/142/120/143; Par. 108) one above another (as plainly seen in Fig. 14A) over a substrate (Fig. 14A: 105);
performing [a material removal process] (Par. 116 – 117) to form a source/drain opening (Fig. 14D: RC; Par. 124) in the semiconductor layers and the substrate (as plainly seen in Fig. 14D);
forming an epitaxial seed layer (Fig. 14I: 152d; Par. 81) in the source/drain opening (as plainly seen in Fig. 14I);
forming a source/drain epitaxial structure (Fig. 14J: 154d; Par. 81) over the epitaxial seed layer (as plainly seen in Fig. 14J) and in contact with the semiconductor layers (Fig. 14J: 154d is in electrical contact with 141, 142, & 143 of the semiconductor layers via 152d),
wherein the source/drain epitaxial structure and the epitaxial seed layer are made of different materials (Par. 85: “152d may be [a silicon arsenide] epitaxial layer, and…154d may be [a silicon phosphide] epitaxial layer”) such that strain is created in the source/drain epitaxial structure (Par. 85: “154d may be epitaxially grown from…152d”. As there is a lattice mismatch between silicon arsenide and silicon phosphide, this creates a strain in 154d);
and forming a gate structure (Fig. 14L: 160a; Par. 87) over the semiconductor layers (as plainly seen in Fig. 14L).
JANG, however, does not disclose:
performing an etching process to form a source/drain opening…
SEO, though, discloses for a method of making a similar device:
performing an etching process (Fig. 3; Par. 38) to form a source/drain opening (Fig. 3: 304; Par. 38)…
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the removal process of JANG according to the etching process of SEO, as these inventions are from the same field of endeavor, and the etching process of SEO is known in the art to provide a means to remove material to form a source/drain opening in the fabrication of such devices as evidenced by the use of said etching process by SEO, and because the selection of a known process based on its suitability for its intended use is supported by a prima facie case of obviousness, MPEP 2144.07.
Regarding Claim 19,
JANG does not disclose:
The method of claim 16,
wherein prior to forming the epitaxial seed layer, the method further comprises:
forming an epitaxial layer in a bottom portion of the source/drain opening;
and forming an isolation layer over the epitaxial layer.
SEO, though, discloses for the method of making the similar device of SEO:
wherein prior to forming the epitaxial seed layer (Fig. 12: the cleaned surfaces of the “exposed tips of the active channel nanosheets” just prior to epitaxial growth of the source/drain epitaxial structure 1202; Par. 51), the method further comprises:
forming an epitaxial layer (Fig. 6: 602; Par. 42) in a bottom portion (as plainly seen in Fig. 6) of the source/drain opening (Fig. 6: 304; Par. 38);
and forming an isolation layer (Fig. 7 – 8: 806; Par. 43) over the epitaxial layer (as plainly seen in Fig. 7).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of JANG with that of SEO to enable forming an epitaxial layer in a bottom portion of the source/drain opening, and forming an isolation layer over the epitaxial layer in JANG according to the teachings of SEO, for the further advantage of preventing source-to-drain shorts between adjacent source and drain regions (SEO, Par. 38).
Regarding Claim 20,
JANG does not disclose:
The method of claim 19,
wherein an air gap is formed vertically between the epitaxial seed layer and the isolation layer.
SEO, though, discloses for the method of making the similar device of SEO:
wherein an air gap is formed (Fig. 12: gap between 1202 and 806; Par. 51) vertically between the epitaxial seed layer (as described in Claim 19) and the isolation layer (as plainly seen in Fig. 12).
Regarding Claim 29,
JANG discloses:
A method (Fig. 14A – 14L), comprising:
forming semiconductor layers (Fig. 14A: 120/141/120/142/120/143; Par. 108) one above another (as plainly seen in Fig. 14A) over a substrate (Fig. 14A: 105);
performing [a material removal process] (Par. 116 – 117) to form a source/drain opening (Fig. 14D: RC; Par. 124) in the semiconductor layers and the substrate (as plainly seen in Fig. 14D);
forming an epitaxial seed layer (Fig. 14I: 152d; Par. 81) in the source/drain opening (as plainly seen in Fig. 14I);
forming a source/drain epitaxial structure (Fig. 14J: 154d; Par. 81) over the epitaxial seed layer (as plainly seen in Fig. 14J) and in contact with the semiconductor layers (Fig. 14J: 154d is in electrical contact with 141, 142, & 143 of the semiconductor layers via 152d),
wherein a lattice constant of the epitaxial seed layer is different from a lattice constant of the source/drain epitaxial structure (Par. 85: “152d may be [a silicon arsenide] epitaxial layer, and…154d may be [a silicon phosphide] epitaxial layer”, and silicon arsenide has a different lattice constant than silicon phosphide);
and forming a gate structure (Fig. 14L: 160a; Par. 87) over the semiconductor layers (as plainly seen in Fig. 14L).
JANG, however, does not disclose:
performing an etching process to form a source/drain opening…
SEO, though, discloses for a method of making a similar device:
performing an etching process (Fig. 3; Par. 38) to form a source/drain opening (Fig. 3: 304; Par. 38)…
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to perform the removal process of JANG according to the etching process of SEO, as these inventions are from the same field of endeavor, and the etching process of SEO is known in the art to provide a means to remove material to form a source/drain opening in the fabrication of such devices as evidenced by the use of said etching process by SEO, and because the selection of a known process based on its suitability for its intended use is supported by a prima facie case of obviousness, MPEP 2144.07.
Regarding Claim 30,
JANG does not disclose:
The method of claim 29,
further comprising, prior to forming the epitaxial seed layer, forming an isolation layer in the source/ drain opening.
SEO, though, discloses for the method of making the similar device of SEO:
further comprising, prior to forming the epitaxial seed layer (Fig. 12: the cleaned surfaces of the “exposed tips of the active channel nanosheets” just prior to epitaxial growth of the source/drain epitaxial structure 1202; Par. 51), forming an isolation layer (Fig. 7 – 8: 806; Par. 43) in the source/ drain opening (as plainly seen in Fig. 8).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of JANG with that of SEO to enable forming an epitaxial layer in a bottom portion of the source/drain opening, and forming an isolation layer over the epitaxial layer in JANG according to the teachings of SEO, for the further advantage of preventing source-to-drain shorts between adjacent source and drain regions (SEO, Par. 38).
Regarding Claim 31,
JANG does not disclose:
The method of claim 30,
wherein an air gap is formed vertically between the epitaxial seed layer and the isolation layer.
SEO, though, discloses for the method of making the similar device of SEO:
wherein an air gap is formed (Fig. 12: gap between 1202 and 806; Par. 51) vertically between the epitaxial seed layer (as described in Claim 30) and the isolation layer (as plainly seen in Fig. 12).
Regarding Claim 32,
JANG does not disclose:
The method of claim 31,
wherein an entirety of the epitaxial seed layer is spaced apart from the isolation layer through the air gap.
SEO, though, discloses for the method of making the similar device of SEO:
wherein an entirety of the epitaxial seed layer (Fig. 12: the entirety of each cleaned surfaces of the “exposed tips of the active channel nanosheets” just prior to epitaxial growth of the source/drain epitaxial structure 1202; Par. 51) is spaced apart from the isolation layer through the air gap (Fig. 12: the entirety of each tip of the “active channel nanosheets”—and, thus, the entirety of each epitaxial seed layer—is spaced apart from 806 through 1202 and the air gap).
Regarding Claim 35,
JANG discloses:
The method of claim 29,
wherein a bottom surface of the epitaxial seed layer is higher than atop surface of the substrate (Fig. 14I: each surface of 152d is higher than the top surface of 105).
Claims 17 & 18 are rejected under 35 U.S.C. 103 as being unpatentable over JANG in view of SEO and in further view of KITTL (US 20170271514 A1).
Regarding Claim 17,
JANG discloses:
The method of claim 16,
wherein forming the epitaxial seed layer (Fig. 14G – 14I) comprises:
depositing an epitaxial material (Fig. 14G: 152S; Par. 123 & Fig. 14H: 152; Par. 125) in the source/drain opening (as plainly seen in Fig. 14G – 14H);
and etching back the epitaxial material (Fig. 14I; Par. 126 – 127)…
JANG and SEO, however, do not disclose:
etching back the epitaxial material to expose sidewalls of the semiconductor layers.
KITTL, though, discloses for a method of making a similar device:
etching back the epitaxial material (Fig. 3F – 3G: 315’ and/or 316’; Par. 33 – 34) to expose sidewalls (Fig. 3G: 317 and/or 318) of the semiconductor layers (as plainly seen in Fig. 3G).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the combination of JANG and SEO with that of KITTL, to enable the etching back the epitaxial material of the combination of JANG and SEO according to the teachings of KITTL, for the further advantage of controlling defect density of the source/drain epitaxial structure (KITTL Par. 34).
Regarding Claim 18,
JANG and SEO do not disclose:
The method of claim 17,
wherein etching back the epitaxial material is performed until a bottommost one of the semiconductor layers is exposed.
KITTL, though, discloses for the method of making the similar device of KITTL:
wherein etching back the epitaxial material is performed until a bottommost one of the semiconductor layers (Fig. 3G: 309; Par. 34) is exposed (as plainly seen in Fig. 3G).
Claims 33 & 34 are rejected under 35 U.S.C. 103 as being unpatentable over JANG in view of SEO and in further view of XIE (US 20220406664 A1).
Regarding Claim 33,
JANG and SEO do not disclose:
The method of claim 29,
wherein the source/drain epitaxial structure has a higher germanium concentration than the epitaxial seed layer.
XIE, though, discloses for a method of making a similar device:
wherein the source/drain epitaxial structure (Fig. 10: 144, which may be boron doped silicon germanium, Par. 46) has a higher germanium concentration than the epitaxial seed layer (Fig. 10: 128, which may be boron doped silicon, Par. 38).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of JANG with those of XIE to enable the source/drain epitaxial structure to have a higher germanium concentration than the epitaxial seed layer in JANG according to the teachings of XIE for the further advantage of protecting the device during gate replacement (XIE Par. 3) and reduce device resistance (XIE Par. 47).
Regarding Claim 34,
JANG and SEO do not disclose:
The method of claim 29,
wherein a top surface of the epitaxial seed layer is lower than a top surface of a bottommost one of the semiconductor layers.
XIE, though, discloses for the method of making the similar device of XIE:
wherein a top surface of the epitaxial seed layer is lower than a top surface of a bottommost one of the semiconductor layers (Fig. 9, right side: the bottommost top surface of 128, Par. 38, is lower than the top surface of the bottommost 108, Par. 29).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the epitaxial seed layer design of JANG with that of XIE, as these inventions are from the same field of endeavor, and the epitaxial seed layer design of XIE is known in the art to provide a means to reduce device resistance, XIE Par. 47.
Claims 21 – 23, 25, 26, & 28 are rejected under 35 U.S.C. 103 as being unpatentable over XIE in view of SEO.
Regarding Claim 21,
XIE discloses:
A method (Fig. 1 – 13), comprising:
forming semiconductor layers (Fig. 1: 108s and 106s; Par. 29) one above another (as seen in Fig. 1) over a substrate (Fig. 1: 102);
performing an etching process (Fig. 1; Par. 33) to form a source/drain opening (Fig. 1: 120; Par. 37) in the semiconductor layers (as plainly seen in Fig. 1)…;
forming an isolation layer (Fig. 1: 104; Par. 27) in the source/drain opening (as plainly seen in Fig. 1);
forming an epitaxial material (Fig. 3: 128; Par. 37) in the source/ drain opening and over the isolation layer (as plainly seen in Fig. 3);
etching back the epitaxial material (Par. 45) such that a top surface of the epitaxial material is lower than a top surface of a bottommost one of the semiconductor layers (Fig. 9, right side: 128 is etched back such that the bottommost top surface of 128 is lower than the top surface of the bottommost 108);
forming a source/drain epitaxial structure (Fig. 10: 144; Par. 46) in the source/ drain opening and over the epitaxial material (as plainly seen in Fig. 10);
and forming a gate structure (Fig. 10: 136/138, Par. 43) over the semiconductor layers (as plainly seen in Fig. 10).
XIE, however, does not disclose:
performing an etching process to form a source/drain opening in the semiconductor layers and the substrate;
SEO, though, discloses for a method of making a similar device:
performing an etching process (Fig. 3; Par. 38) to form a source/drain opening (Fig. 3: 304, Par. 38) in the semiconductor layers (Fig. 1 & 3: “active channel” nanosheets and “sacrificial” nanosheets; Par. 32 – 33) and the substrate (Fig. 3: 102);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine process of XIE with that of SEO, as these inventions are from the same field of endeavor, and the process of SEO is known in the art to provide a means to “[prevent] epitaxial growth on the substrate beneath the [source/drain epitaxial structure]”, SEO Par. 51, which “can undesirably lead to source-to-drain shorts between adjacent source and drain regions”, SEO Par. 38.
Regarding Claim 22,
XIE does not disclose:
The method of claim 21,
further comprising, prior to forming the isolation layer, forming an epitaxial layer in the source/ drain opening.
SEO, though, discloses for the method of making the similar device of SEO:
further comprising, prior to forming the isolation layer (Fig. 7 – 8: 806; Par. 43), forming an epitaxial layer (Fig. 6: 602; Par. 42) in the source/ drain opening (as plainly seen in Fig. 6).
Further, the motivation to combine XIE and SEO here is the same as for Claim 21.
Regarding Claim 23,
XIE does not disclose:
The method of claim 21,
wherein an air gap is formed vertically between the epitaxial material and the isolation layer.
SEO, though, discloses for the method of making the similar device of SEO:
wherein an air gap is formed (Fig. 12: gap between 1202 and 806; Par. 51) vertically between the epitaxial material (Fig. 12: the cleaned surfaces of the “exposed tips of the active channel nanosheets” just prior to epitaxial growth of the source/drain epitaxial structure 1202; Par. 51) and the isolation layer (as plainly seen in Fig. 12).
Further, the motivation to combine XIE and SEO here is the same as for Claim 21.
Regarding Claim 25,
XIE discloses:
The method of claim 21,
wherein the source/drain epitaxial structure interfaces with the bottommost one of the semiconductor layers (Fig. 10, right side: 144 interfaces with the bottommost 108).
Regarding Claim 26,
XIE discloses:
The method of claim 25,
wherein the epitaxial material interfaces with the bottommost one of the semiconductor layers and the source/drain epitaxial structure (Fig. 10, right side: 128 interfaces with the bottommost 108 at its bottommost corners and 144 at its bottom surface).
Regarding Claim 28,
XIE discloses:
The method of claim 21,
wherein after etching back the epitaxial material, the epitaxial material has a concave top surface profile (Fig. 9: after etching back, 128 has a concave up top surface profile).
Claims 24, 27 are rejected under 35 U.S.C. 103 as being unpatentable over XIE in view of SEO and in further view of REZNICEK (US 20190109052 A1).
Regarding Claim 24,
XIE discloses:
The method of claim 23,
further comprising forming an inner spacer (Fig. 7: 116; Par. 27) between the bottommost one of the semiconductor layers and the substrate (Fig. 7: 116 between bottommost 108 and 102),
SEO also discloses for the method of making the similar device of SEO:
further comprising forming an inner spacer (Fig. 19: 502; Par. 40) between the bottommost one of the semiconductor layers and the substrate (Fig. 19: 502 between the bottommost “active channel nanosheet” and 102),
XIE and SEO, however, do not disclose:
wherein a sidewall of the inner spacer is exposed to the air gap.
REZNICEK, though, discloses for a method of making a similar device:
wherein a sidewall of the inner spacer (Fig. 8: bottommost 20S; Par. 47) is exposed to the air gap (Fig. 8: bottommost 20S is exposed to 28; Par. 52).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the air gap geometry of XIE in view of SEO with that of REZNICEK, as these inventions are from the same field of endeavor, and the air gap geometry of REZNICEK is known in the art to provide a means to prevent parasitic transistor formation, REZNICEK Par. 67, which degrades the performance of the device.
Regarding Claim 27,
XIE and SEO do not disclose:
The method of claim 21,
wherein the epitaxial material has a concave bottom surface profile.
REZNICEK, though, discloses for a method of making a similar device:
wherein the [source/drain epitaxial structure] (Fig. 8: 26; Par. 51) has a concave bottom surface profile (Fig. 8: 26 has a concave up bottom surface profile).
REZNICEK, however, does not disclose:
wherein the epitaxial material has a concave bottom surface profile.
Regardless, XIE in view of SEO in further view of REZNICEK satisfies the limitations of this claim, as the method of XIE would provide the epitaxial material in place of a bottommost portion of the source/drain epitaxial structure in REZNICEK Fig. 8, including its bottom surface. In doing so, the epitaxial material in such a combination would have a concave up bottom surface profile.
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the air gap geometry of XIE in view of SEO with that of REZNICEK, as these inventions are from the same field of endeavor, and the air gap geometry of REZNICEK is known in the art to provide a means to prevent parasitic transistor formation, REZNICEK Par. 67, which degrades the performance of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kenneth S. Stephenson whose telephone number is (571)272-6686. The examiner can normally be reached Monday through Friday, 9 A.M. to 5 P.M. (EST)..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571) 272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898