Prosecution Insights
Last updated: April 19, 2026
Application No. 18/367,064

SEMICONDUCTOR DEVICE WITH ASSISTANCE FEATURES AND METHOD FOR FABRICATING THE SAME

Final Rejection §103
Filed
Sep 12, 2023
Examiner
NADAV, ORI
Art Unit
2811
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Nanya Technology Corporation
OA Round
4 (Final)
60%
Grant Probability
Moderate
5-6
OA Rounds
3y 11m
To Grant
81%
With Interview

Examiner Intelligence

Grants 60% of resolved cases
60%
Career Allow Rate
417 granted / 693 resolved
-7.8% vs TC avg
Strong +21% interview lift
Without
With
+20.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 11m
Avg Prosecution
67 currently pending
Career history
760
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
52.6%
+12.6% vs TC avg
§102
14.2%
-25.8% vs TC avg
§112
29.5%
-10.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 693 resolved cases

Office Action

§103
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA DETAILED ACTION Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-8, 11-12 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2014/0175659) in view of Skotnicki et al. (2002/0163027).Regarding claim 1, Lee et al. teach in figures 2A-2K and related text a display device comprising: a method for fabricating a semiconductor device, comprising: providing a substrate 21; forming a first dielectric layer 25 on and in direct contact with a top surface of the substrate 21; forming a first opening and a second opening in the first dielectric layer 25 to expose a top surface of the substrate at each of bottoms of the first opening and the second opening (not depicted but described in respect to figure 2A), wherein the first opening and the second opening are positioned side-by-side; forming a layer of conductive material 28A (see figure 2D) to partially fill (see element 28 in figure 2E) the first opening to form a first recess within the first opening, fill the second opening, and cover a top surface of the first dielectric layer (as depicted in figure 2D); wherein the top surface of the first dielectric layer 25 is exposed to turn the layer of conductive material into a first contact 28 in the first opening and a second contact in the second opening (another 28); and wherein the first contact 28 and the second contact (another 28) are formed within the first opening and the second opening respectively and are positioned below the top surface of the first dielectric layer 25, wherein the first recess of the first contact 28 has a top opening formed (see figure 2E) at the top surface of the first dielectric layer 25; and forming a first assistance feature 33 on the first contact (see figure 2K) by completely filling the first recess with the first assistance feature and forming a second assistance feature (another 33) on the second contact, wherein the first assistance 33 feature has a bottom portion filled in the first recess and a capping portion formed on the top surface of the first dielectric layer (not depicted in figure 2K but described in related text); wherein the bottom portion of the first assistance feature is positioned below the top surface of the first dielectric layer while the capping portion of the first assistance feature is positioned above the top surface of the first dielectric layer (before it is polished); wherein the first assistance feature and the second assistance feature comprise conductive material; wherein the layer of conductive material comprises conductive material; Lee et al. do not explicitly state performing a planarization process and do not teach that the first assistance feature and the second assistance feature comprise germanium or silicon germanium and the layer of conductive material is doped with n-type dopants or p-type dopants. Skotnicki et al. teach in related text (see paragraphs [0012] and [0069]) performing a planarization process and layer of conductive material comprise germanium or silicon germanium wherein the layer of conductive material is doped with n-type dopants or p-type dopants. Lee et al. and Noh et al. are analogous art because they are directed to conductive materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to perform a planarization process and to form the first assistance feature and the second assistance feature comprise germanium or silicon germanium and the layer of conductive material is doped with n-type dopants or p-type dopants, as taught by Skotnicki et al., in Lee et al.’s device, in order to improve the contact resistance of the device and in order to simplify the processing steps of making the device by using one material for both layers, respectively. Regarding the claimed limitations of using specific materials, it is noted that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979. It is further held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claim 2, Lee et al. do not teach that the layer of conductive material is formed by low-pressure chemical vapor deposition. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the layer of conductive material by low-pressure chemical vapor deposition in Lee et al.’s device, in order to simplify the processing steps of making the device by using conventional processing step. Claim 3, Lee et al. do not teach that the process temperature of forming the first assistance feature and the second assistance feature is between about 300 oC and about 800 oC. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the process temperature of forming the first assistance feature and the second assistance feature is between about 300 oC and about 800 oC in Lee et al.’s device, in order to simplify the processing steps of making the device by using conventional processing step. Claim 4, Lee et al. do not teach that the process pressure of forming the first assistance feature and the second assistance feature is between about 1 Torr and about 300 Torr. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first assistance feature and the second assistance feature is between about 1 Torr and about 300 Torr in Lee et al.’s device, in order to simplify the processing steps of making the device by using conventional processing step. Claim 5, Lee et al. teach that the reactive gas of forming the first assistance feature and the second assistance feature comprises a germanium precursor and/or hydrogen gas. Claim 6, Lee et al. teach that the semiconductor device of wherein the germanium precursor comprises germane, digermane, isobutylgermane, chlorogermane, or dichlorogermane. Claim 7, Lee et al. teach that the first contact and the second contact comprise silicon and/or germanium with substantially no oxygen and nitrogen. Claim 8, Lee et al. each that the conductive material comprises polycrystalline silicon, polycrystalline germanium, or polycrystalline silicon germanium. Regarding claim 11, Lee et al. teach in figure 2D and related text that a width of the first contact (the width located not directly above the first contact) at the top surface of the first dielectric layer is larger than a width of the second contact (directly above the second contact) at the top surface of the first dielectric layer. Regarding claim 12, Lee et al. teach in figure 2K and related text that the layer of conductive material 28A (see figure 2D) partially fills the second opening (while it is being filled, see also figure 2E) to form a second recess (being part of the first recess) of the second contact within the second opening, wherein a width of the second recess at the top surface of the first dielectric layer is less (arbitrarily chosen) than a width of the first recess at the top surface of the first dielectric layer, wherein the second recess of the first contact has a top opening formed at the top surface of the first dielectric layer, wherein the top opening of the first recess is larger than the top opening of the second recess (since the second recess is being part of the first recess) Regarding claim 15, Lee et al. teach in figure 2K and related text that a thickness of the capping portion of the first assistance feature is equal to a thickness of the top portion of the second assistance feature. Claims 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2014/0175659) and Skotnicki et al. (2002/0163027), as applied to claim 1 above, and further in view of Lee et al. (10,593,676). Regarding claim 9, Lee et al. (2014/0175659) and Skotnicki et al. teach substantially the entire claimed structure, as applied to claim 1, except the first recess, having a vase-like cross-sectional profile, has an upper portion downwardly extended from the top surface of the first dielectric layer, a neck portion extended from the upper portion and a lower portion extended from the upper portion, wherein a horizontal distance of the neck portion of the first recess is decreased toward the neck portion thereof while a horizontal distance of the lower portion of the first recess is increased from the neck portion till a until the bottom of the first recess. Lee et al. (10,593,676) teach in figure 1A and related text a first recess, having a vase-like cross-sectional profile 110, has an upper portion downwardly extended from the top surface of the first dielectric layer and a lower portion extended from the upper portion, wherein a horizontal distance of the upper portion of the first recess is decreased toward the lower portion thereof while a horizontal distance of the lower portion of the first recess is increased until the bottom of the first recess. Lee et al. (2014/0175659), Lee et al. (10,593,676) and Skotnicki et al. are analogous art because they are directed to conductive materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. (2014/0175659) because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the first recess, having a vase-like cross-sectional profile, has an upper portion downwardly extended from the top surface of the first dielectric layer and a lower portion extended from the upper portion, wherein a horizontal distance of the upper portion of the first recess is decreased toward the lower portion thereof while a horizontal distance of the lower portion of the first recess is increased till a until the bottom of the first recess, as taught by Lee et al. (10,593,676), in Lee et al. (2014/0175659)’s device, in order to improve the balance of yield and critical dimensions of the device. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2014/0175659) and Skotnicki et al. (2002/0163027), as applied to the claims above, and further in view of Fischer et al. (2012/0068273). Regarding claim 13, Lee et al. and Skotnicki et al. teach substantially the entire claimed structure, as applied to claim 1, except a depth of the second recess from the top surface of the first dielectric layer to the bottom of the second recess is less than a depth of the first recess from the top surface of the first dielectric layer to the bottom of the first recess. Fischer et al. et al. teach in figure 12 and related text a depth of the second recess 868 from the top surface of the first dielectric layer to the bottom of the second recess is less than a depth of the first recess (another 868) from the top surface of the first dielectric layer to the bottom of the first recess. Lee et al., Fischer et al. and Skotnicki et al. are analogous art because they are directed to conductive materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. (2014/0175659) because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a depth of the second recess from the top surface of the first dielectric layer to the bottom of the second recess is less than a depth of the first recess from the top surface of the first dielectric layer to the bottom of the first recess, as taught by Fischer et al., in Lee et al.’s device, in order to use the device in a CMOS application. Claims 10 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2014/0175659) and Skotnicki et al. (2002/0163027), as applied to the claims above, and further in view of Ma et al. (2022/0172749). Regarding claim 10, Lee et al. and Skotnicki et al. teach substantially the entire claimed structure, as applied to claim 1, except a width of the first contact at the top surface of the first dielectric layer is different from a width of the second contact at the top surface of the first dielectric layer, and wherein the width of the first contact at the top surface of the first dielectric layer is equal to a width of the first opening, wherein the width of the second contact at the top surface of the first dielectric layer is equal to a width of the second opening, such that the width of the first opening is different from the width of the second opening. Ma et al. teach in figure 8 and related text that a width of the first contact 34 at the top surface of the first dielectric layer is different from a width of the second contact 36 at the top surface of the first dielectric layer, and wherein the width of the first contact at the top surface of the first dielectric layer is equal to a width of the first opening, wherein the width of the second contact at the top surface of the first dielectric layer is equal to a width of the second opening, such that the width of the first opening is different from the width of the second opening. Lee et al., Ma et al. and Skotnicki et al. are analogous art because they are directed to conductive materials and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. (2014/0175659) because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form a width of the first contact at the top surface of the first dielectric layer is different from a width of the second contact at the top surface of the first dielectric layer, and wherein the width of the first contact at the top surface of the first dielectric layer is equal to a width of the first opening, wherein the width of the second contact at the top surface of the first dielectric layer is equal to a width of the second opening, such that the width of the first opening is different from the width of the second opening, as taught by Ma et al., in Lee et al.’s device, in order to adjust the contact resistance of the device according to the requirements of the application in hand. Regarding claim 14, Lee et al. teach in figure 2K and related text that the second recess is partially filled by the second assistance feature, wherein second assistance feature has a bottom portion filled in the second recess and a top portion formed on the top surface of the first dielectric layer, wherein an air gap 29 is formed within the second recess below the bottom portion of the second assistance feature. Lee et al. do not teach that the air gap is formed within the second contact and enclosed by the second contact and the bottom portion of the second assistance feature. Ma et al. teach in figure 8 and related text an air gap 40 formed within the second contact and enclosed by the second contact and the bottom portion of a second assistance feature. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form the air gap within the second contact and enclosed by the second contact and the bottom portion of the second assistance feature in prior art’s device in order to adjust the contact resistance of the device according to the requirements. Response to Arguments Applicant’s arguments with respect to the claim(s) have been considered but are moot because the new ground of rejection due to the new numerals and the explanation in the rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ORI NADAV whose telephone number is 571-272-1660. The examiner can normally be reached between the hours of 7 AM to 4 PM (Eastern Standard Time) Monday through Friday. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached on 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). O.N. /ORI NADAV/ 1/28/2026 PRIMARY EXAMINER TECHNOLOGY CENTER 2800
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Prosecution Timeline

Sep 12, 2023
Application Filed
May 15, 2025
Non-Final Rejection — §103
Jun 10, 2025
Response Filed
Aug 04, 2025
Final Rejection — §103
Aug 27, 2025
Request for Continued Examination
Aug 29, 2025
Response after Non-Final Action
Nov 04, 2025
Non-Final Rejection — §103
Jan 13, 2026
Response Filed
Jan 28, 2026
Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
60%
Grant Probability
81%
With Interview (+20.6%)
3y 11m
Median Time to Grant
High
PTA Risk
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