DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, 8-10, 12, 14, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Said et al. (US 2021/0233881 A1 hereinafter referred to as “Said”).
With respect to claim 1, Said discloses, in Figs.1A-9B, a method, comprising: providing a first substrate (908) having a first bonding layer (988, 971); providing a second substrate (708) having a second bonding layer (788, 771) (see Par.[0040] wherein referring to the step of Figs.1A-1F, the first semiconductor die 900 includes a first substrate 908, first semiconductor devices 920 overlying the first substrate 908, first dielectric material layers (290, 960, 971) overlying the first semiconductor devices, and first metal interconnect structures 980 embedded in the first dielectric material layers (290, 960, 971); see Par.[0050] wherein the first metallic fill material layer 988 includes a metallic material that can be bonded by metal-to-metal bonding; see Par.[0066] wherein referring to Figs.2A-2C, the second semiconductor die 700 includes a second substrate 708, second semiconductor devices 720 overlying the second substrate 708, second dielectric material layers (760, 771) overlying the second semiconductor devices 720, and second metal interconnect structures 780 embedded in the second dielectric material layers (760, 771); see Par.[0070] wherein second bonding pads 788 can be formed in each second pad cavity by performing the processing steps of FIGS. 1C and 1D; each second bonding pad 788 can include a second metallic liner 788A and a second metallic fill material portion 788B); coupling a metal-containing precursor (992) to the first bonding layer (988) (see Par.[0057]-[0061] wherein referring to Fig.1G, a first metal-containing precursor layer 992 can be formed on the first recessed dielectric surface of the first pad-level dielectric layer 971; the first metal-containing precursor layer 992 may, or may not, be formed on the sidewalls of the first bonding pads 988 depending on whether the first SAM layers 991 are present on the sidewalls of the first bonding pads 988 or not; the first metal-containing precursor layer 992 includes a metal-containing precursor material that forms a metal-organic framework (MOF) material that can be activated by chemical treatment upon exposure to a vapor of a linking compound (i.e., a linker precursor)); activating the metal-containing precursor (972) on the first bonding layer (988) (see Par.[0062]-[0065] wherein referring to FIG. 1H, a first metal-organic framework (MOF) dielectric layer 972 can be formed by reacting the first metal-containing precursor layer 992 with a first vapor of a first linking compound; the first MOF dielectric layer 972 can laterally surround the first bonding pads 988; for example, the first semiconductor die 900 can be placed in a vacuum-tight reaction chamber; an oxidation process can be performed to convert the material of the first metal-containing precursor layer 992 into a metal oxide material in case the first metal-containing precursor layer 992 includes an elemental metal, a metal nitride, or a metal carbide); and chemically reacting the activated metal-containing precursor on the first bonding layer with the second bonding layer to form an interface between the first substrate and the second substrate (see Par.[0082]-[0086] wherein referring to the step of Fig.3A, the first semiconductor die 900 and the second semiconductor die 700 are oriented such that the first MOF dielectric layer 972 faces the second MOF dielectric layer 772; the second semiconductor die 700 and the first semiconductor die 900 are brought into contact such that a surface of the second MOF dielectric layer 772 contacts a surface of the first MOF dielectric layer 972, and each of the second bonding pads 788 faces, and has an areal overlap in a plan view with, a respective one of the first bonding pads 988; step of Fig.3B illustrates magnified views of two exemplary configurations, in which a respective mating pair of a first bonding pad 988 and a second bonding pad 788 is shown at the processing step of FIG. 3A; the first SAM layer 991 and the second SAM layer 791 may include a monolayer of an alkane thiol having a chemical formula of CH.sub.3(CH.sub.2).sub.n-1SH. Such an alkane thiol is known to selectively attach to copper surfaces without being attached to silicon oxide surfaces; the first SAM layer 991 may include an alkane thiol compound having a first end (i.e., a first SH head group) with affinity to the material of the first bonding pads 988 and without affinity to the material of the first pad-level dielectric layer 971, and having a second end (i.e., a first tail/terminal/functional group); further, the bonding chemical reaction includes the first tail group A and the second tail group B can be selected such that first tail group A can be selectively bonded to the second group B upon alignment of the first bonding pads 988 to the second bonding pads 788; for example, a self-assembly material may include a thiol (e.g., sulfur containing) head group configured to bond to a copper bonding pad, a CH.sub.2 backbone, and a methyl (CH.sub.3) or a hydroxide tail group configured to bind to another similar or different tail group of the corresponding SAM bonded to the opposing corresponding bonding pad).
With respect to claim 2, Said discloses, in Figs.1A-9B, the method, wherein the metal-containing precursor comprises a metal-organic compound (see Par.[0058]-[0060] wherein the first metal-containing precursor layer 992 includes a metal-containing precursor material that forms a metal-organic framework (MOF) material upon exposure to a vapor of a linking compound (i.e., a linker precursor)).
With respect to claim 3, Said discloses, in Figs.1A-9B, the method, wherein the first bonding layer and the second bonding layer are each terminated with a hydroxyl group such that coupling the metal-containing precursor comprises chemically reacting the metal-containing precursor with the hydroxyl group to form a metal oxide bond (see Par.[0086] wherein the first tail group A and the second tail group B can be selected such that first tail group A can be selectively bonded to the second group B upon alignment of the first bonding pads 988 to the second bonding pads 788; for example, a self-assembly material may include a thiol (e.g., sulfur containing) head group configured to bond to a copper bonding pad, a CH.sub.2 backbone, and a methyl (CH.sub.3) or a hydroxide (i.e.; ion of hydroxyl group OH) tail group configured to bind to another similar or different tail group of the corresponding SAM bonded to the opposing corresponding bonding pad).
With respect to claim 4, Said discloses, in Figs.1A-9B, the method, further comprising: coupling the metal-containing precursor to the second bonding layer; and activating the metal-containing precursor on the second bonding layer, such that the method comprises chemically reacting the activated metal-containing precursor on the first bonding layer with the activated metal-containing precursor on the second bonding layer to form the interface (see Par.[0062]-[0065] wherein referring to FIG. 1H, a first metal-organic framework (MOF) dielectric layer 972 can be formed by reacting the first metal-containing precursor layer 992 with a first vapor of a first linking compound; the first MOF dielectric layer 972 can laterally surround the first bonding pads 988; for example, the first semiconductor die 900 can be placed in a vacuum-tight reaction chamber; an oxidation process can be performed to convert the material of the first metal-containing precursor layer 992 into a metal oxide material in case the first metal-containing precursor layer 992 includes an elemental metal, a metal nitride, or a metal carbide).
With respect to claim 5, Said discloses, in Figs.1A-9B, the method, wherein the first bonding layer (988, 971) comprises a first dielectric layer (971) adjacent and protruding from a first metal layer and the second bonding layer (788, 771) comprises a second dielectric layer (771) adjacent and protruding from a second metal layer, the method further comprising making physical contact between the first dielectric layer (971) and the second dielectric layer (771) before chemically reacting the activated metal-containing precursor (see Par.[0040] wherein referring to the step of Figs.1A-1F, the first semiconductor die 900 includes a first substrate 908, first semiconductor devices 920 overlying the first substrate 908, first dielectric material layers (290, 960, 971) overlying the first semiconductor devices, and first metal interconnect structures 980 embedded in the first dielectric material layers (290, 960, 971); see Par.[0050] wherein the first metallic fill material layer 988 includes a metallic material that can be bonded by metal-to-metal bonding; see Par.[0066] wherein referring to Figs.2A-2C, the second semiconductor die 700 includes a second substrate 708, second semiconductor devices 720 overlying the second substrate 708, second dielectric material layers (760, 771) overlying the second semiconductor devices 720, and second metal interconnect structures 780 embedded in the second dielectric material layers (760, 771); see Par.[0070] wherein second bonding pads 788 can be formed in each second pad cavity by performing the processing steps of FIGS. 1C and 1D; each second bonding pad 788 can include a second metallic liner 788A and a second metallic fill material portion 788B; see Fig.4 wherein the contact bonding between dielectric bonding layers).
With respect to claim 7, Said discloses, in Figs.1A-9B, the method, further comprising annealing the interface after chemically reacting the activated metal-containing precursor (see Par.[0094] wherein Referring to FIG. 7B, the processing steps of FIG. 4 can be performed to induce metal-to-metal bonding between the first bonding pads 988 and the second bonding pads 788; the first metal-containing precursor layer 992 may be spaced from the second metal-containing precursor layer 792 during the bonding process; the anneal temperature may be selected based on the composition of the second bonding pads 788 and the first bonding pads 988; for example, if the second bonding pads 788 and the first bonding pads 988 include metal fill portions that consist essentially of copper, the anneal temperature may be in a range from 150 degrees Celsius to 400 degrees Celsius; the molecules of the first SAM layer 991 and the second SAM layer 791 may decompose during the anneal process, and may be evaporated or may be incorporated into the first bonding pads 988 and the second bonding pads 788 as impurity atoms).
With respect to claim 9, Said discloses, in Figs.1A-9B, the method, wherein applying the metal-containing precursor comprises implementing an atomic layer deposition process (see Par.[0050] wherein the first metallic fill material layer 988L can be deposited, for example, by a sputtering, CVD, ALD, electroless plating and/or electroplating).
With respect to claim 10, Said discloses, in Figs.1A-9B, a method, comprising: forming a first bonding surface (988, 971) on a first substrate (908), the first bonding surface including a first metal-organic precursor (992); forming a second bonding surface (788, 771) on a second substrate (708), the second bonding surface (788, 771) including a second metal-organic precursor (792) (see Par.[0040] wherein referring to the step of Figs.1A-1F, the first semiconductor die 900 includes a first substrate 908, first semiconductor devices 920 overlying the first substrate 908, first dielectric material layers (290, 960, 971) overlying the first semiconductor devices, and first metal interconnect structures 980 embedded in the first dielectric material layers (290, 960, 971); see Par.[0050] wherein the first metallic fill material layer 988 includes a metallic material that can be bonded by metal-to-metal bonding; see Par.[0066] wherein referring to Figs.2A-2C, the second semiconductor die 700 includes a second substrate 708, second semiconductor devices 720 overlying the second substrate 708, second dielectric material layers (760, 771) overlying the second semiconductor devices 720, and second metal interconnect structures 780 embedded in the second dielectric material layers (760, 771); see Par.[0070] wherein second bonding pads 788 can be formed in each second pad cavity by performing the processing steps of FIGS. 1C and 1D; each second bonding pad 788 can include a second metallic liner 788A and a second metallic fill material portion 788B; see Par.[0057]-[0061] wherein referring to Fig.1G, a first metal-containing precursor layer 992 can be formed on the first recessed dielectric surface of the first pad-level dielectric layer 971; the first metal-containing precursor layer 992 may, or may not, be formed on the sidewalls of the first bonding pads 988 depending on whether the first SAM layers 991 are present on the sidewalls of the first bonding pads 988 or not; the first metal-containing precursor layer 992 includes a metal-containing precursor material that forms a metal-organic framework (MOF) material that can be activated by chemical treatment upon exposure to a vapor of a linking compound (i.e., a linker precursor)); activating the first metal-organic precursor (992) and the second metal-organic precursor (792) (see Par.[0062]-[0065] wherein referring to FIG. 1H, a first metal-organic framework (MOF) dielectric layer 972 can be formed by reacting the first metal-containing precursor layer 992 with a first vapor of a first linking compound; the first MOF dielectric layer 972 can laterally surround the first bonding pads 988; for example, the first semiconductor die 900 can be placed in a vacuum-tight reaction chamber; an oxidation process can be performed to convert the material of the first metal-containing precursor layer 992 into a metal oxide material in case the first metal-containing precursor layer 992 includes an elemental metal, a metal nitride, or a metal carbide); reacting the activated first metal-organic precursor with the activated second metal-organic precursor to form an interface between the first bonding surface and the second bonding surface (see Par.[0082]-[0086] wherein referring to the step of Fig.3A, the first semiconductor die 900 and the second semiconductor die 700 are oriented such that the first MOF dielectric layer 972 faces the second MOF dielectric layer 772; the second semiconductor die 700 and the first semiconductor die 900 are brought into contact such that a surface of the second MOF dielectric layer 772 contacts a surface of the first MOF dielectric layer 972, and each of the second bonding pads 788 faces, and has an a real overlap in a plan view with, a respective one of the first bonding pads 988; step of Fig.3B illustrates magnified views of two exemplary configurations, in which a respective mating pair of a first bonding pad 988 and a second bonding pad 788 is shown at the processing step of FIG. 3A); and annealing the interface to bond the first substrate to the second substrate (see Par.[0094] wherein Referring to FIG. 7B, the processing steps of FIG. 4 can be performed to induce metal-to-metal bonding between the first bonding pads 988 and the second bonding pads 788; the first metal-containing precursor layer 992 may be spaced from the second metal-containing precursor layer 792 during the bonding process; the anneal temperature may be selected based on the composition of the second bonding pads 788 and the first bonding pads 988; for example, if the second bonding pads 788 and the first bonding pads 988 include metal fill portions that consist essentially of copper, the anneal temperature may be in a range from 150 degrees Celsius to 400 degrees Celsius; the molecules of the first SAM layer 991 and the second SAM layer 791 may decompose during the anneal process, and may be evaporated or may be incorporated into the first bonding pads 988 and the second bonding pads 788 as impurity atoms).
With respect to claim 12, Said discloses, in Figs.1A-9B, the method, wherein forming the first bonding surface and the second bonding surface comprises depositing the first metal-organic precursor and the second metal-organic precursor over the first substrate and the second substrate, respectively, using an atomic layer deposition process (see Par.[0050] wherein the first metallic fill material layer 988L can be deposited, for example, by a sputtering, CVD, ALD, electroless plating and/or electroplating).
With respect to claim 14, Said discloses, in Figs.1A-9B, the method, wherein the first substrate comprises a first dielectric layer (971) adjacent and protruding from a first metal layer (988) and the second substrate comprises a second dielectric layer (771) adjacent and protruding from a second metal layer (788), and wherein forming the first bonding surface and forming the second bonding surface respectively comprise: coupling the first metal-organic precursor to the first dielectric layer and the first metal layer; and coupling the second organic precursor to the second dielectric layer and the second metal layer (see Par.[0040] wherein referring to the step of Figs.1A-1F, the first semiconductor die 900 includes a first substrate 908, first semiconductor devices 920 overlying the first substrate 908, first dielectric material layers (290, 960, 971) overlying the first semiconductor devices, and first metal interconnect structures 980 embedded in the first dielectric material layers (290, 960, 971); see Par.[0050] wherein the first metallic fill material layer 988 includes a metallic material that can be bonded by metal-to-metal bonding; see Par.[0066] wherein referring to Figs.2A-2C, the second semiconductor die 700 includes a second substrate 708, second semiconductor devices 720 overlying the second substrate 708, second dielectric material layers (760, 771) overlying the second semiconductor devices 720, and second metal interconnect structures 780 embedded in the second dielectric material layers (760, 771); see Par.[0070] wherein second bonding pads 788 can be formed in each second pad cavity by performing the processing steps of FIGS. 1C and 1D; each second bonding pad 788 can include a second metallic liner 788A and a second metallic fill material portion 788B; see Fig.4 wherein the contact bonding between dielectric bonding layers).
With respect to claim 16, Said discloses, in Figs.1A-9B, the method, wherein annealing the interface causes the first metal layer and the second metal layer to extend across the interface and physically contact one another (see Fig.4).
Claims 1-4, 7, 17, 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guha et al. (US 2018/0056248 A1 hereinafter referred to as “Guha”).
With respect to claim 1, Guha discloses, in Figs.1-5H, a method, comprising: providing a first substrate (106A) having a first bonding layer (104A, 102); providing a second substrate (106B) having a second bonding layer (104B, 102) (see Par.[0026]-[0029] wherein a first polymeric layer 102 upon which is disposed a first bonding layer 104A and a first activation layer 106A; the first polymeric layer 102 is in direct contact with the first bonding layer 104A, which is in direct contact with the first activation layer 106A; disposed on an opposing surface of the first polymeric layer 102 is a second bonding layer 104B and a second activation layer 106B; the first polymeric layer 102 is also in direct contact with the second bonding layer 104B, which is in direct contact with the second activation layer 106B; see Par.[0064] wherein the membrane 100 depicted in the FIG. 3 is the membrane depicted in the FIG. 1, it is also possible to use the membrane depicted in the FIG. 2 in the purification vessel 200); coupling a metal-containing precursor to the first bonding layer (104) (see Par.[0069] wherein the dopamine bonding layer 104 was prepared using dopamine hydrochloride as follows; CuO nanoparticles were prepared using drop-by-drop addition of NaOH in Cu(NO3).sub.2.2H.sub.2O (Strem Chemicals) precursor solution in ultrapure water (Barnstead Nanopure, Model 7146, 18.2 MΩ-cm) (Supplementary information); the membranes were represented as 8 ppm CuO/PDA or 80 ppm CuO/PDA according to the precursor concentrations); activating the metal-containing precursor on the first bonding layer (104) (see Par.[0067] wherein a membrane that comprises a bonding layer that comprises dopamine upon which is disposed an activation layer that comprises copper oxide (cupric oxide) CuO nanoparticles; see Par.[0069] wherein an activated layer of CuO nanoparticles is disposed on the polydopamine layer); and chemically reacting the activated metal-containing precursor on the first bonding layer (104A) with the second bonding layer (104B) to form an interface between the first substrate (106A) and the second substrate (106B) (see Par.[0049]-[0050] wherein the bonding layer 104 is an activation layer that comprises catalytic nanoparticles that facilitate the conversion of impurities present in the water to a gas with or without addition of an additional chemical in the feed stream; the nanoparticles are operative to convert chemical impurities (present naturally in the water naturally or manually added to the water) to gas bubbles; see Par.[0069] wherein CuO nanoparticles were prepared using drop-by-drop addition of NaOH in Cu(NO3).sub.2.2H.sub.2O (Strem Chemicals) precursor solution in ultrapure water (Barnstead Nanopure, Model 7146, 18.2 MΩ-cm) (Supplementary information)).
With respect to claim 2, Guha discloses, in Figs.1-5H, the method, wherein the metal-containing precursor (104, 102) comprises a metal-organic compound (see Par.[0044]-[0045] wherein the bonding layer 104 are polydopamine, amine functionalized polymers listed above in formula (1) and the associated description, carboxylic acid functionalized polymers and copolymers, or the like, or a combination thereof; and the acid functionality in the carboxylated olefin copolymer is not neutralized with a metal ion; see Par.[0053]-[0054] wherein the semiconductor structure of claim 17, wherein the first metal oxide moiety and the second metal oxide moiety each comprise at least one material selected from aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, zinc oxide, and tin oxide).
With respect to claim 3, Guha discloses, in Figs.1-5H, the method, wherein the first bonding layer and the second bonding layer are each terminated with a hydroxyl group such that coupling the metal-containing precursor comprises chemically reacting the metal-containing precursor with the hydroxyl group to form a metal oxide bond (see Par.[0032] wherein examples of thermosetting polymers include epoxy polymers, unsaturated polyester polymers, polyimide polymers, bismaleimide polymers, bismaleimide triazine polymers, cyanate ester polymers, vinyl polymers, benzoxazine polymers, benzocyclobutene polymers, acrylics, alkyds, phenol-formaldehyde polymers, novolacs, resoles, melamine-formaldehyde polymers, urea-formaldehyde polymers, hydroxymethylfurans, isocyanates, unsaturated polyesterimides, or the like, or a combination comprising at least one of the foregoing thermosetting polymers; see Par.[0037]-[0039] wherein R.sub.1 is an amine functionalized C.sub.3 alkyl chain and two or more of R.sub.2 through R.sub.6 are hydroxyl groups, with the remainder being hydrogen atoms).
With respect to claim 4, Guha discloses, in Figs.1-5H, the method, further comprising: coupling the metal-containing precursor to the second bonding layer; and activating the metal-containing precursor on the second bonding layer, such that the method comprises chemically reacting the activated metal-containing precursor on the first bonding layer with the activated metal-containing precursor on the second bonding layer to form the interface (see Par.[0069] wherein the dopamine bonding layer 104 was prepared using dopamine hydrochloride as follows; CuO nanoparticles were prepared using drop-by-drop addition of NaOH in Cu(NO3).sub.2.2H.sub.2O (Strem Chemicals) precursor solution in ultrapure water (Barnstead Nanopure, Model 7146, 18.2 MΩ-cm) (Supplementary information); the membranes were represented as 8 ppm CuO/PDA or 80 ppm CuO/PDA according to the precursor concentrations; see Par.[0049]-[0050] wherein the bonding layer 104 is an activation layer that comprises catalytic nanoparticles that facilitate the conversion of impurities present in the water to a gas with or without addition of an additional chemical in the feed stream; the nanoparticles are operative to convert chemical impurities (present naturally in the water naturally or manually added to the water) to gas bubbles; see Par.[0069] wherein CuO nanoparticles were prepared using drop-by-drop addition of NaOH in Cu(NO3).sub.2.2H.sub.2O (Strem Chemicals) precursor solution in ultrapure water (Barnstead Nanopure, Model 7146, 18.2 MΩ-cm) (Supplementary information)).
With respect to claim 7, Guha discloses, in Figs.1-5H, the method, further comprising annealing the interface after chemically reacting the activated metal-containing precursor (see Par.[0069] wherein the dopamine bonding layer 104 was prepared using dopamine hydrochloride as follows; CuO nanoparticles were prepared using drop-by-drop addition of NaOH in Cu(NO3).sub.2.2H.sub.2O (Strem Chemicals) precursor solution in ultrapure water (Barnstead Nanopure, Model 7146, 18.2 MΩ-cm) (Supplementary information); the membranes were represented as 8 ppm CuO/PDA or 80 ppm CuO/PDA according to the precursor concentrations; see Par.[0049]-[0050] wherein the bonding layer 104 is an activation layer that comprises catalytic nanoparticles that facilitate the conversion of impurities present in the water to a gas with or without addition of an additional chemical in the feed stream; the nanoparticles are operative to convert chemical impurities (present naturally in the water naturally or manually added to the water) to gas bubbles; see Par.[0069] wherein CuO nanoparticles were prepared using drop-by-drop addition of NaOH in Cu(NO3).sub.2.2H.sub.2O (Strem Chemicals) precursor solution in ultrapure water (Barnstead Nanopure, Model 7146, 18.2 MΩ-cm) (Supplementary information)).
With respect to claim 17, Guha discloses, in Figs.1-5H, a semiconductor structure, comprising: a first substrate (106A) having a first surface; a second substrate (106B) having a second surface (see Par.[0026]-[0029] wherein a first polymeric layer 102 upon which is disposed a first bonding layer 104A and a first activation layer 106A; the first polymeric layer 102 is in direct contact with the first bonding layer 104A, which is in direct contact with the first activation layer 106A; disposed on an opposing surface of the first polymeric layer 102 is a second bonding layer 104B and a second activation layer 106B; the first polymeric layer 102 is also in direct contact with the second bonding layer 104B, which is in direct contact with the second activation layer 106B; see Par.[0064] wherein the membrane 100 depicted in the FIG. 3 is the membrane depicted in the FIG. 1, it is also possible to use the membrane depicted in the FIG. 2 in the purification vessel 200); and an interfacial layer covalently coupled to the first surface and the second surface by a first metal oxide moiety and a second metal oxide moiety, respectively (see Par.[0044]-[0045] wherein the bonding layer 104 are polydopamine, amine functionalized polymers listed above in formula (1) and the associated description, carboxylic acid functionalized polymers and copolymers, or the like, or a combination thereof; and the acid functionality in the carboxylated olefin copolymer is not neutralized with a metal ion; see Par.[0057] wherein peroxides may be organic and inorganic peroxides; inorganic peroxides are divided into ionic and covalent peroxides; the ionic peroxides mostly contain the peroxides of the alkali and alkaline earth metals whereas the covalent peroxides are represented by such compounds as hydrogen peroxide and peroxymonosulfuric acid (H.sub.2SO.sub.5); the purely ionic character of alkali metal peroxides, peroxides of transition metals have a more covalent character; see Par.[0026] wherein he first polymeric layer 102 is in direct contact with the bonding layer 104, which is in direct contact with the activation layer 106. The bonding layer 104 facilitates the attachment of the activation moieties to membrane 100).
With respect to claim 19, Guha discloses, in Figs.1-5H, the semiconductor structure, wherein the first metal oxide moiety and the second oxide moiety are covalently coupled by an oxygen-containing linkage (see Par.[0035] wherein the first polymeric layer 102 may comprise a blend of a non-amine containing organic polymer with polydopamine and/or an amine functionalized polymer; the non-amine containing organic polymer is preferably hydrophillic but not soluble in aqueous media. Examples of non-amine containing organic polymers that can be blended with the polydopamine or an amine functionalized polymer are polyvinyl alcohol and copolymer, polyamides (listed above) and copolymers, polyvinylpyrrolidone and copolymers, polyacrylic acid and copolymers, poly(meth)acrylates and copolymers, poly(2-oxazoline) and copolymers, polyethyleneimine and copolymers, polyalkylene oxides (e.g., polyethylene oxide, polypropylene oxide, or the like) and copolymers, or the like, or a combination thereof).
With respect to claim 20, Guha discloses, in Figs.1-5H, the semiconductor structure, wherein the first metal oxide moiety and the second metal oxide moiety each comprise at least one material selected from aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, zinc oxide, and tin oxide (see Par.[0053]-[0054] wherein the semiconductor structure of claim 17, wherein the first metal oxide moiety and the second metal oxide moiety each comprise at least one material selected from aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, zinc oxide, and tin oxide).
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Tapily et al. (US 2024/0071984 A1 hereinafter referred to as “Tapily”).
The applied reference has a common of Tokyo Electron Limited with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
With respect to claim 1, Tapily discloses, in Figs.1-10, a method, comprising: providing a first substrate (212) having a first bonding layer (210, 206); providing a second substrate (312) having a second bonding layer (210, 306) (see Par.[0044] wherein the semiconductor device 200 can include a first wafer 202 (e.g., top/bottom wafer or die, sometimes referred to as a first substrate) and a second wafer 204 (e.g., bottom/top wafer or die, sometimes referred to as a second substrate); each wafer 202, 204 can include a semiconductor base portion 212, 312, such as silicon, germanium, a combination thereof, or the like; a dielectric layer 206 is formed over the base portion 212, 312 of the wafers 202, 204; at least a portion of an interconnect structure 208 is disposed within the dielectric layer 206; a bonding layer 210 is formed over the dielectric layer 206; see Par.[0056] wherein the first wafer 202 can include the first substrate including at least the dielectric layer 306, semiconductor base portion 312, and interconnect structure 308, and the second wafer 204 can include the second substrate including at least the dielectric layer 206, semiconductor base portion 212, and interconnect structure 208; see Par.[0058] wherein first and second bonding layers can form the singular bonding layer 210 shown in FIG. 4B); coupling a metal-containing precursor to the first bonding layer (210, 206) (see Par.[0070] wherein an aluminum oxide (Al.sub.2O.sub.3) bonding layer can be formed with a pre-curser comprising TMA (AL.sub.2(CH.sub.3).sub.6) over the first dielectric layer of the semiconductor device 200 of FIG. 2B, and others; the deposition chamber 740 can apply the dielectric by one or more processes described with reference to FIG. 2B, and others; for example, the deposition chamber 740 can apply a vapor comprising a plurality of precursors to form the dielectric (e.g., CVD), or a physical vapor deposition process such as sputtering or evaporation); activating the metal-containing precursor on the first bonding layer (210, 206) (see Par.[0052]-[0054] wherein the surface of one or more materials (e.g., dielectric layer 206, interconnect structure 208, or bonding layer 210) can be treated using at least one suitable surface treatment process or technique, such as a plasma activation procedure; for example, the surface of the bonding layer 210 can be activated by plasma activation); and chemically reacting the activated metal-containing precursor on the first bonding layer (210, 206) with the second bonding layer (306, 210) to form an interface between the first substrate (212) and the second substrate (312) (see Par.[0070]-[0074] wherein the deposition chamber 740 can apply the dielectric to a wafer to form the first dielectric layer, or to form a bonding layer comprising a dielectric (e.g., aluminum oxide (Al.sub.2O.sub.3) or other dielectrics described herein (e.g., for the dielectric layer 206 or the first bonding layer 210 of FIG. 2B, among others); an aluminum oxide (Al.sub.2O.sub.3) bonding layer can be formed with a pre-curser comprising TMA (AL.sub.2(CH.sub.3).sub.6) over the first dielectric layer of the semiconductor device 200 of FIG. 2B, and others one or more bonding layers processed by the post treatment chamber 745 can be interfaced to another wafer (e.g., another wafer which has been processed by the post treatment chamber 745); the bond between respective wafers can be based on the chemical bonding energy therebetween).
With respect to claim 2, Tapily discloses, in Figs.1-10, the method, wherein the metal-containing precursor comprises a metal-organic compound (see Par.[0048] wherein the bonding layer 210 can be formed with one or more materials selected from a group such as Si.sub.aO.sub.bC.sub.cN.sub.d (where a,b,c,d vary from 0 to 1); for example, the bonding layer 210 can be or include silicon oxide (SiO.sub.2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), or combinations thereof, among other types of metal oxide materials (e.g., can be AlCON.sub.x, or another aluminum dielectric, or another non-aluminum based dielectric)).
With respect to claim 3, Tapily discloses, in Figs.1-10, the method, wherein the first bonding layer (210, 206) and the second bonding layer (306, 210) are each terminated with a hydroxyl group such that coupling the metal-containing precursor comprises chemically reacting the metal-containing precursor with the hydroxyl group to form a metal oxide bond (see Par.[0055] wherein as shown in at least FIG. 3B, hydroxide (OH) can be introduced to the top surface of the bonding layer 210 via the DI water rinsing process; therefore, the substrate (e.g., the first or second substrates of the wafers 202, 204) can be rinsed with DI water to hydrophilize the bonding layer 210 of the respective wafers 202, 204. By introducing hydroxide to the surface of the bonding layer 210, the bonding or coupling capabilities between the bonding layer 210 of two wafers 202, 204 can be enhanced (e.g., for preparing the bonding layer 210 for interconnection); see Par.[0069] wherein a particle remover chamber 725 can remove various particles, contaminants, or the like from a surface of a wafer. For example, the particle remover chamber 725 can remove environmental contaminants from inside or outside the EFEM 705, or reactants or other detritus from various EFEM 705 operations; for example, the particle remover chamber 725 can apply an oxidizer such as aluminum hydroxide (NH.sub.4O.sub.4) or hydrogen peroxide (H.sub.2O.sub.2) in a solution comprising DI water).
With respect to claim 4, Tapily discloses, in Figs.1-10, the method, further comprising: coupling the metal-containing precursor to the second bonding layer; and activating the metal-containing precursor on the second bonding layer, such that the method comprises chemically reacting the activated metal-containing precursor on the first bonding layer with the activated metal-containing precursor on the second bonding layer to form the interface (see Par.[0052]-[0054] wherein the surface of one or more materials (e.g., dielectric layer 206, interconnect structure 208, or bonding layer 210) can be treated using at least one suitable surface treatment process or technique, such as a plasma activation procedure; for example, the surface of the bonding layer 210 can be activated by plasma activation; see Par.[0070]-[0074] wherein the deposition chamber 740 can apply the dielectric to a wafer to form the first dielectric layer, or to form a bonding layer comprising a dielectric (e.g., aluminum oxide (Al.sub.2O.sub.3) or other dielectrics described herein (e.g., for the dielectric layer 206 or the first bonding layer 210 of FIG. 2B, among others); an aluminum oxide (Al.sub.2O.sub.3) bonding layer can be formed with a pre-curser comprising TMA (AL.sub.2(CH.sub.3).sub.6) over the first dielectric layer of the semiconductor device 200 of FIG. 2B, and others one or more bonding layers processed by the post treatment chamber 745 can be interfaced to another wafer (e.g., another wafer which has been processed by the post treatment chamber 745); the bond between respective wafers can be based on the chemical bonding energy therebetween).
With respect to claim 5, Tapily discloses, in Figs.1-10, the method, wherein the first bonding layer comprises a first dielectric layer (206) adjacent and protruding from a first metal layer and the second bonding layer (306) comprises a second dielectric layer adjacent and protruding from a second metal layer, the method further comprising making physical contact between the first dielectric layer and the second dielectric layer before chemically reacting the activated metal-containing precursor (see Par.[0044] wherein the semiconductor device 200 can include a first wafer 202 (e.g., top/bottom wafer or die, sometimes referred to as a first substrate) and a second wafer 204 (e.g., bottom/top wafer or die, sometimes referred to as a second substrate); each wafer 202, 204 can include a semiconductor base portion 212, 312, such as silicon, germanium, a combination thereof, or the like; a dielectric layer 206 is formed over the base portion 212, 312 of the wafers 202, 204; at least a portion of an interconnect structure 208 is disposed within the dielectric layer 206; a bonding layer 210 is formed over the dielectric layer 206; see Par.[0056] wherein the first wafer 202 can include the first substrate including at least the dielectric layer 306, semiconductor base portion 312, and interconnect structure 308, and the second wafer 204 can include the second substrate including at least the dielectric layer 206, semiconductor base portion 212, and interconnect structure 208; see Par.[0058] wherein first and second bonding layers can form the singular bonding layer 210 shown in FIG. 4B).
With respect to claim 6, Tapily discloses, in Figs.1-10, the method, wherein coupling the metal-containing precursor results in a first amount of the metal-containing precursor coupled to the first dielectric layer and a second amount of the metal-containing precursor coupled to the first metal layer, the second amount being less than the first amount (see Par.[0058] wherein the pressure applied may comprise a pressure of less than about 30 MPa, and the heat applied may comprise an anneal process at a temperature of about 100 to 500 degrees C., as examples, although alternatively, other amounts of pressure and heat may be used for the hybrid bonding process; the hybrid bonding process may be performed in a N.sub.2 environment, an Ar environment, a He environment, an (about 4 to 10% H.sub.2)/(about 90 to 96% inert gas or N.sub.2) environment, an inert-mixing gas environment, combinations thereof, or other types of environments. Hence, the first and second wafers 202, 204 (e.g., first and second substrates) can be coupled based on the physically contacting at least the bonding layers).
With respect to claim 7, Tapily discloses, in Figs.1-10, the method, further comprising annealing the interface after chemically reacting the activated metal-containing precursor (see Par.[0041] wherein by coupling the wafers, a channel can be formed extending from the top surfaces of the respective interconnect structures; therefore, the first and second substrates can be heated/annealed, thereby expanding and physically connecting the interconnect structures of the two wafers; see Par.[0058], [0062], [0074]-[0076] wherein by applying heat or pressure (e.g., during physical contact between the first and second bonding layers of the respective wafers 202, 204), the first and second bonding layers can be coupled/bonded/interconnected; the pressure applied may comprise a pressure of less than about 30 MPa, and the heat applied may comprise an anneal process at a temperature of about 100 to 500 degrees C., as examples, although alternatively, other amounts of pressure and heat may be used for the hybrid bonding process).
With respect to claim 8, Tapily discloses, in Figs.1-10, the method, wherein activating the metal-containing precursor comprises applying at least one of H20, 02 plasma, and 03 plasma, to the metal-containing precursor (see Par.[0068]-[0069] wherein the etch chamber 720 can include one or more etch chambers 720 for wet etches, and one or more etch chambers 720 for dry (e.g., plasma) etches; the particle remover chamber 725 can apply an oxidizer such as aluminum hydroxide (NH.sub.4O.sub.4) or hydrogen peroxide (H.sub.2O.sub.2) in a solution comprising DI water; see Par.[0071] wherein a high density plasma configured to interact with the surface of the semiconductor device can be applied to increase the bonding energy between two wafers; the plasma can be a microwave plasma having a frequency between about 1 GHz, and 100 GHz; for example, the plasma can oscillate or be energized by a source of about 2.45 GHz; the plasma can include water such as DI water (H.sub.2O), dihydrogen (H.sub.2), dinitrogen (N.sub.2), combinations thereof, and the like).
With respect to claim 9, Tapily discloses, in Figs.1-10, the method, wherein applying the metal-containing precursor comprises implementing an atomic layer deposition process (see Par.[0080]-[0081] wherein additional agents or reagents can be deposited (e.g., three, four, or more alternated agents/reagents), or can be deposited in a non-regular repeating pattern; the ALD process can be a gas or plasma phase ALD process; the ALD process can be or include a solution based ALD process in which one or more agent or reagent is delivered to or from the ALD chamber 910 in solution (e.g., a solution comprising DI water); the ALD process can include the application of heat, light, or other energy; according to a position or function of one or more load ports 710 or wafer handlers 715, various positioning of the illustrated portions can be beneficial; for example, the alignment and bonding chamber 760, DI water rinse chamber 755, annealing chamber 770, inspection chamber 775, SAM chamber 905, or ALD chamber 910 van be laterally disposed).
With respect to claim 10, Tapily discloses, in Figs.1-10, a method, comprising: forming a first bonding surface (210) on a first substrate (212), the first bonding surface (210) including a first metal-organic precursor; forming a second bonding surface (210) on a second substrate (312), the second bonding surface (210) including a second metal-organic precursor (see Par.[0044] wherein the semiconductor device 200 can include a first wafer 202 (e.g., top/bottom wafer or die, sometimes referred to as a first substrate) and a second wafer 204 (e.g., bottom/top wafer or die, sometimes referred to as a second substrate); each wafer 202, 204 can include a semiconductor base portion 212, 312, such as silicon, germanium, a combination thereof, or the like; a dielectric layer 206 is formed over the base portion 212, 312 of the wafers 202, 204; at least a portion of an interconnect structure 208 is disposed within the dielectric layer 206; a bonding layer 210 is formed over the dielectric layer 206; see Par.[0056] wherein the first wafer 202 can include the first substrate including at least the dielectric layer 306, semiconductor base portion 312, and interconnect structure 308, and the second wafer 204 can include the second substrate including at least the dielectric layer 206, semiconductor base portion 212, and interconnect structure 208; see Par.[0058] wherein first and second bonding layers can form the singular bonding layer 210 shown in FIG. 4B; see Par.[0070] wherein an aluminum oxide (Al.sub.2O.sub.3) bonding layer can be formed with a pre-curser comprising TMA (AL.sub.2(CH.sub.3).sub.6) over the first dielectric layer of the semiconductor device 200 of FIG. 2B, and others; the deposition chamber 740 can apply the dielectric by one or more processes described with reference to FIG. 2B, and others; for example, the deposition chamber 740 can apply a vapor comprising a plurality of precursors to form the dielectric (e.g., CVD), or a physical vapor deposition process such as sputtering or evaporation); activating the first metal-organic precursor and the second metal-organic precursor (see Par.[0052]-[0054] wherein the surface of one or more materials (e.g., dielectric layer 206, interconnect structure 208, or bonding layer 210) can be treated using at least one suitable surface treatment process or technique, such as a plasma activation procedure; for example, the surface of the bonding layer 210 can be activated by plasma activation); reacting the activated first metal-organic precursor with the activated second metal-organic precursor to form an interface between the first bonding surface and the second bonding surface; and annealing the interface to bond the first substrate to the second substrate (see Par.[0070]-[0074] wherein the deposition chamber 740 can apply the dielectric to a wafer to form the first dielectric layer, or to form a bonding layer comprising a dielectric (e.g., aluminum oxide (Al.sub.2O.sub.3) or other dielectrics described herein (e.g., for the dielectric layer 206 or the first bonding layer 210 of FIG. 2B, among others); an aluminum oxide (Al.sub.2O.sub.3) bonding layer can be formed with a pre-curser comprising TMA (AL.sub.2(CH.sub.3).sub.6) over the first dielectric layer of the semiconductor device 200 of FIG. 2B, and others one or more bonding layers processed by the post treatment chamber 745 can be interfaced to another wafer (e.g., another wafer which has been processed by the post treatment chamber 745); the bond between respective wafers can be based on the chemical bonding energy therebetween).
With respect to claim 11, Tapily discloses, in Figs.1-10, the method, wherein activating the metal-containing precursor comprises applying at least one of H20, 02, and 03 to oxidize each of the first metal-organic precursor and the second metal-organic precursor, thereby forming a hydroxylated metal oxide moiety coupled to each of the first bonding surface and the second bonding surface (see Par.[0055] wherein as shown in at least FIG. 3B, hydroxide (OH) can be introduced to the top surface of the bonding layer 210 via the DI water rinsing process; therefore, the substrate (e.g., the first or second substrates of the wafers 202, 204) can be rinsed with DI water to hydrophilize the bonding layer 210 of the respective wafers 202, 204. By introducing hydroxide to the surface of the bonding layer 210, the bonding or coupling capabilities between the bonding layer 210 of two wafers 202, 204 can be enhanced (e.g., for preparing the bonding layer 210 for interconnection); see Par.[0069] wherein a particle remover chamber 725 can remove various particles, contaminants, or the like from a surface of a wafer. For example, the particle remover chamber 725 can remove environmental contaminants from inside or outside the EFEM 705, or reactants or other detritus from various EFEM 705 operations; for example, the particle remover chamber 725 can apply an oxidizer such as aluminum hydroxide (NH.sub.4O.sub.4) or hydrogen peroxide (H.sub.2O.sub.2) in a solution comprising DI water; see Par.[0068]-[0069] wherein the etch chamber 720 can include one or more etch chambers 720 for wet etches, and one or more etch chambers 720 for dry (e.g., plasma) etches; the particle remover chamber 725 can apply an oxidizer such as aluminum hydroxide (NH.sub.4O.sub.4) or hydrogen peroxide (H.sub.2O.sub.2) in a solution comprising DI water; see Par.[0071] wherein a high density plasma configured to interact with the surface of the semiconductor device can be applied to increase the bonding energy between two wafers; the plasma can be a microwave plasma having a frequency between about 1 GHz, and 100 GHz; for example, the plasma can oscillate or be energized by a source of about 2.45 GHz; the plasma can include water such as DI water (H.sub.2O), dihydrogen (H.sub.2), dinitrogen (N.sub.2), combinations thereof, and the like).
With respect to claim 12, Tapily discloses, in Figs.1-10, the method, wherein forming the first bonding surface and the second bonding surface comprises depositing the first metal-organic precursor and the second metal-organic precursor over the first substrate and the second substrate, respectively, using an atomic layer deposition process (see Par.[0080]-[0081] wherein additional agents or reagents can be deposited (e.g., three, four, or more alternated agents/reagents), or can be deposited in a non-regular repeating pattern; the ALD process can be a gas or plasma phase ALD process; the ALD process can be or include a solution based ALD process in which one or more agent or reagent is delivered to or from the ALD chamber 910 in solution (e.g., a solution comprising DI water); the ALD process can include the application of heat, light, or other energy; according to a position or function of one or more load ports 710 or wafer handlers 715, various positioning of the illustrated portions can be beneficial; for example, the alignment and bonding chamber 760, DI water rinse chamber 755, annealing chamber 770, inspection chamber 775, SAM chamber 905, or ALD chamber 910 van be laterally disposed).
With respect to claim 13, Tapily discloses, in Figs.1-10, the method, wherein the activated first metal-organic precursor comprises a first metal oxide moiety covalently coupled to a first bonding layer over the first substrate and the activated second metal-organic precursor comprises a second metal oxide covalently coupled to a second bonding layer over the second substrate, and wherein reacting the activated first metal-organic precursor with the activated second metal-organic precursor forms an oxygen-containing linkage between the first metal oxide moiety and the second metal oxide moiety (see Par.[0053] wherein a bonding layer can be about 5 nm thick, and can maintain a smooth surface such that the plasma activation increases a bonding energy (e.g., because the increase in activation or energy of dangling bonds such as hydroxyl groups for van der Waals or covalent bonds exceeds any losses due to increased surface roughness); see Par.[0048] wherein the bonding layer 210 can be or include moiety material: silicon oxide (SiO.sub.2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), or combinations thereof, among other types of metal oxide materials (e.g., can be AlCON.sub.x, or another aluminum dielectric, or another non-aluminum based dielectric)).
With respect to claim 14, Tapily discloses, in Figs.1-10, the method, wherein the first substrate comprises a first dielectric layer adjacent and protruding from a first metal layer and the second substrate comprises a second dielectric layer adjacent and protruding from a second metal layer, and wherein forming the first bonding surface and forming the second bonding surface respectively comprise: coupling the first metal-organic precursor to the first dielectric layer (206) and the first metal layer; and coupling the second organic precursor to the second dielectric layer (306) and the second metal layer (see Par.[0044] wherein the semiconductor device 200 can include a first wafer 202 (e.g., top/bottom wafer or die, sometimes referred to as a first substrate) and a second wafer 204 (e.g., bottom/top wafer or die, sometimes referred to as a second substrate); each wafer 202, 204 can include a semiconductor base portion 212, 312, such as silicon, germanium, a combination thereof, or the like; a dielectric layer 206 is formed over the base portion 212, 312 of the wafers 202, 204; at least a portion of an interconnect structure 208 is disposed within the dielectric layer 206; a bonding layer 210 is formed over the dielectric layer 206; see Par.[0056] wherein the first wafer 202 can include the first substrate including at least the dielectric layer 306, semiconductor base portion 312, and interconnect structure 308, and the second wafer 204 can include the second substrate including at least the dielectric layer 206, semiconductor base portion 212, and interconnect structure 208).
With respect to claim 15, Tapily discloses, in Figs.1-10, the method, wherein coupling the first metal-organic precursor and coupling the second organic precursor reduces hydrophilicity of the first dielectric layer and the second dielectric layer, respectively (see Par.[0054]-[0055] wherein the second wafer 204 can be activated according to a same process as the first wafer 202; thus, the respective wafers can include increased bond strengths (e.g., hydrophilic bonds) therebetween, or between the respective wafers and an intermediary such as a water layer that may be present between the wafers at one or more portions of the bonding or associated processes; as shown in at least FIG. 3B, hydroxide (OH) can be introduced to the top surface of the bonding layer 210 via the DI water rinsing process.; therefore, the substrate (e.g., the first or second substrates of the wafers 202, 204) can be rinsed with DI water to hydrophilize the bonding layer 210 of the respective wafers 202, 204. By introducing hydroxide to the surface of the bonding layer 210, the bonding or coupling capabilities between the bonding layer 210 of two wafers 202, 204 can be enhanced (e.g., for preparing the bonding layer 210 for interconnection)).
With respect to claim 16, Tapily discloses, in Figs.1-10, the method, wherein annealing the interface causes the first metal layer and the second metal layer to extend across the interface and physically contact one another (see Par.[0046] wherein interconnect structures (e.g., formed of conductive materials, such as Cu, Al, W, Ti, TiN, Ta, TaN, or multiple layers or combinations thereof) may be embedded in one or more dielectric layers (e.g., formed of low-k dielectric materials, such as SiO.sub.2), which are sometimes referred to as metallization layers, e.g., 206; alternatively stated, each dielectric layer 206 can include a number of metal lines and a number of metal vias embedded therein).
With respect to claim 17, Tapily discloses, in Figs.1-10, a semiconductor structure, comprising: a first substrate (212) having a first surface; a second substrate (312) having a second surface (see Par.[0044] wherein the semiconductor device 200 can include a first wafer 202 (e.g., top/bottom wafer or die, sometimes referred to as a first substrate) and a second wafer 204 (e.g., bottom/top wafer or die, sometimes referred to as a second substrate); each wafer 202, 204 can include a semiconductor base portion 212, 312, such as silicon, germanium, a combination thereof, or the like; a dielectric layer 206 is formed over the base portion 212, 312 of the wafers 202, 204; at least a portion of an interconnect structure 208 is disposed within the dielectric layer 206; a bonding layer 210 is formed over the dielectric layer 206; see Par.[0056] wherein the first wafer 202 can include the first substrate including at least the dielectric layer 306, semiconductor base portion 312, and interconnect structure 308, and the second wafer 204 can include the second substrate including at least the dielectric layer 206, semiconductor base portion 212, and interconnect structure 208; see Par.[0058] wherein first and second bonding layers can form the singular bonding layer 210 shown in FIG. 4B); and an interfacial layer covalently coupled to the first surface and the second surface by a first metal oxide moiety and a second metal oxide moiety, respectively (see Par.[0053] wherein a bonding layer can be about 5 nm thick, and can maintain a smooth surface such that the plasma activation increases a bonding energy (e.g., because the increase in activation or energy of dangling bonds such as hydroxyl groups for van der Waals or covalent bonds exceeds any losses due to increased surface roughness); see Par.[0048] wherein the bonding layer 210 can be or include moiety material: silicon oxide (SiO.sub.2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), or combinations thereof, among other types of metal oxide materials (e.g., can be AlCON.sub.x, or another aluminum dielectric, or another non-aluminum based dielectric)).
With respect to claim 18, Tapily discloses, in Figs.1-10, the semiconductor structure, wherein the first surface comprises a first dielectric layer and a first metal layer and the second surface comprises a second dielectric layer and a second metal layer, and wherein the interfacial layer extends between the first dielectric layer and the second dielectric layer and between the first metal layer and the second metal layer (see Par.[0044] wherein the semiconductor device 200 can include a first wafer 202 (e.g., top/bottom wafer or die, sometimes referred to as a first substrate) and a second wafer 204 (e.g., bottom/top wafer or die, sometimes referred to as a second substrate); each wafer 202, 204 can include a semiconductor base portion 212, 312, such as silicon, germanium, a combination thereof, or the like; a dielectric layer 206 is formed over the base portion 212, 312 of the wafers 202, 204; at least a portion of an interconnect structure 208 is disposed within the dielectric layer 206; a bonding layer 210 is formed over the dielectric layer 206; see Par.[0056] wherein the first wafer 202 can include the first substrate including at least the dielectric layer 306, semiconductor base portion 312, and interconnect structure 308, and the second wafer 204 can include the second substrate including at least the dielectric layer 206, semiconductor base portion 212, and interconnect structure 208; see Par.[0058] wherein first and second bonding layers can form the singular bonding layer 210 shown in FIG. 4B).
With respect to claim 19, Tapily discloses, in Figs.1-10, the semiconductor structure, wherein the first metal oxide moiety and the second oxide moiety are covalently coupled by an oxygen-containing linkage (see Par.[0053] wherein a bonding layer can be about 5 nm thick, and can maintain a smooth surface such that the plasma activation increases a bonding energy (e.g., because the increase in activation or energy of dangling bonds such as hydroxyl groups for van der Waals or covalent bonds exceeds any losses due to increased surface roughness); see Par.[0048] wherein the bonding layer 210 can be or include moiety material: silicon oxide (SiO.sub.2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), or combinations thereof, among other types of metal oxide materials (e.g., can be AlCON.sub.x, or another aluminum dielectric, or another non-aluminum based dielectric)).
With respect to claim 20, Tapily discloses, in Figs.1-10, the semiconductor structure of claim 17, wherein the first metal oxide moiety and the second metal oxide moiety each comprise at least one material selected from aluminum oxide, titanium oxide, silicon oxide, hafnium oxide, zinc oxide, and tin oxide (see Par.[0053] wherein a bonding layer can be about 5 nm thick, and can maintain a smooth surface such that the plasma activation increases a bonding energy (e.g., because the increase in activation or energy of dangling bonds such as hydroxyl groups for van der Waals or covalent bonds exceeds any losses due to increased surface roughness); see Par.[0048] wherein the bonding layer 210 can be or include moiety material: silicon oxide (SiO.sub.2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), aluminum oxide (Al.sub.2O.sub.3), hafnium oxide (HfO.sub.2), or combinations thereof, among other types of metal oxide materials (e.g., can be AlCON.sub.x, or another aluminum dielectric, or another non-aluminum based dielectric)).
Response to Arguments
Applicant’s arguments with respect to claims 1, 10, 14 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818