DETAILED ACTION
This office action is in response to amendment filed 8/18/2026.
Claims 1-11 are pending. Claims 7-11 have been withdrawn. Claims 1 and 7 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 reciting “wherein the second pads are made of the same metal material in the first pads” renders the claim indefinite. Firstly, “the same metal material” lacks antecedent basis. Furthermore, it unclear how could the seconds pads be made of “the same metal material” that is in the first pads. I.e. the metal material that is in the first pads cannot be also in the second pads.
Claim 1 reciting “the semiconductor chips” renders the claim indefinite due to lack of antecedent basis. Amended claim 1 recites “a semiconductor chip” in line 8. There is no antecedent basis for a plurality of “semiconductor chips”.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. US 2021/0028145 A1 (Yu) in view of Chiu US 2022/0310580 A1 (Chiu).
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In re claim 1, as best understood, Yu discloses (e.g. FIGs. 8A-8D) a method for manufacturing a fan-out packaging unit 10L (¶ 33), comprising:
forming a first rewiring layer 140 (including 142 and 144 except the topmost layer of 142 that includes the top vias 144b, see annotated FIG. 8C above) on a supporting substrate C, wherein the first rewiring layer 140 has a first surface (top surface in FIG. 8C) and a second surface (bottom surface in FIG. 8C) opposite to the first (top) surface, wherein the second (bottom) surface of the first wiring layer 140 faces the supporting substrate C; wherein the first rewiring layer 140 comprises at least one inorganic dielectric layer 142 (e.g. silicon oxide, ¶ 19) and at least one first metal wiring layer 144;
providing a semiconductor chip 110 having a connection surface (bottom surface in FIG. 8C);
forming a first bonding layer (topmost layer of 142 that includes the top vias 144b, see annotated FIG. 8C above) on the first surface of the rewiring layer, wherein forming the first bonding layer includes forming a first passivation layer (topmost layer of 142 in FIG. 8C), disposing via holes (topmost vias 144b) in the first passivation layer, and filling a metal material 144b in the via holes to form first pads (topmost 144b);
forming a second bonding layer (112+114) on the connection (bottom) surface of the semiconductor chip 110, wherein forming the second bonding layer 112+114 includes forming a second passivation layer 114 and disposing second pads 112 in the second passivation layer 114, wherein the second pads 112 are made of “the same material in the first pads” 144b (as best understood, both 112 and 144 can be made of Cu, ¶ 17,19);
forming a hybrid bonding structure (¶ 17) by attaching the first bonding layer (topmost layer of 142 that includes the top vias 144b) and the second bonding layer 112+114 so as to electrically couple “the semiconductor chips” 110 to the first (top) surface of the first rewiring layer 140, wherein the first passivation layer (topmost layer of 142 in FIG. 8C) and the second passivation layer 114 are directly bonded and the first pads 144b and the second pads 122 are aligned and directly bonded using no solder in the hybrid bonding structure (hybrid bonding, ¶ 17);
forming a plastic layer 130 (¶ 18) on the first (top) surface of the first rewiring layer 140 to form a packaging layer on “the semiconductor chips 110”; and
forming a second rewiring layer 160,190,200 over the second (bottom) surface of the first rewiring layer 140, wherein the second rewiring layer has a first (top in FIG. 8C) surface and a second (bottom in FIG. 8C) surface opposite to the first (top) surface, wherein the second rewiring layer 160,190,200 comprises a second metal wiring layer 160,194,204 exposed from the first (top) surface of the second rewiring layer, and wherein the second metal wiring layer 160,194,204 is electrically connected to the second (bottom) surface of the first rewiring layer 140.
Yu discloses the first passivation layer (topmost layer of 142 in FIG. 8C) and the second passivation layer 114 are directly bonded and are both made of inorganic dielectric (¶ 17, 19). Yu does not explicitly disclose the inorganic passivation layers are hydrophilically bonded.
However, Chiu discloses (e.g. FIG. 11) hybrid bonding between a first circuit layer 103 and a second circuit layer 103 (¶ 83-85), wherein the dielectric layers of the circuit layers are formed of inorganic material silicon oxide or silicon nitride, and are bonded based on “hydrophilic bonding mechanism” and hydrophilic surface modifications may be applied to the dielectric layers (¶ 86) to ensure strong bonding interface.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yu’s hybrid bonding structure by applying hydrophilic surface modifications to the first passivation layer 142 and second passivation layer 114 to hydrophilically bond the dielectric layers as taught by Chiu for improving bonding interface.
In re claim 2, Yu discloses (e.g. FIG. 8C) wherein the first rewiring layer 140 comprises two or more inorganic first dielectric layers 142 (including plural dielectric layers above/below each metal lines 144a) and two or more first metal wiring layers 144a, wherein the two or more metal wiring layers 144a are arranged alternately with the two or more inorganic first dielectric layers 142 (plural layers above/below each metal lines 144a).
In re claim 5, Yu discloses (e.g. FIG. 8C) wherein a material of the at least one inorganic dielectric layer 142 comprises one of silicon nitride and silicon oxynitride (silicon oxide, ¶ 19), and wherein a material of the at least one first metal wiring layer 144 comprises one or more of copper, aluminum, nickel, gold, silver, and titanium (¶ 19).
In re claim 6, Yu discloses (e.g. FIG. 8D) wherein forming the second rewiring layer 200 comprises:
forming openings (openings in which UBM 208 are provided) on the second surface (bottom surface in FIG. 8C, top surface in FIG. 8D) of the second rewiring layer 200 to expose the second metal wiring layer 204;
forming a sub-bump metal layer 208 over the openings; and
forming solder balls 210 inside the openings by a ball planting reflow process (¶ 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chiu as applied to claim 1 above, and further in view of Chen US 2013/0252383 A1.
In re claim 3, Yu discloses the supporting substrate C may be a glass carrier (¶ 15), where glass silica teaches silicon-based substrate. Yu further discloses removing the carrier C from the final package (FIGs. 8C-8D). Yu does not explicitly disclose the removal of the supporting substrate comprising: thinning the supporting substrate by applying a mechanical grinding process, and then removing the thinned supporting substrate by applying a chemical-mechanical polishing process.
Chen discloses (e.g. FIGs. 2A-2K) a method for manufacturing a package comprises forming rewiring layer 2a on a supporting substrate 20 that is subsequently removed, wherein the removal of the supporting substrate 20 comprising: thinning the supporting substrate 20 by applying a mechanical grinding process (grinding process to reduce the thickness, ¶ 64), and then removing the thinned supporting substrate 20 by applying a chemical-mechanical polishing process (CMP process to remove the remaining portion, ¶ 64), wherein the supporting substrate is a silicon-based substrate (¶ 40).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to remove the supporting substrate C from Yu’s package by mechanical grinding and CMP as taught by Chen to provide a lost cost process to remove the supporting substrate quickly as is well-known in the art.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu in view of Chiu as applied to claim 1 above, and further in view of Bao et al. US 2022/0310480 A2 (Bao).
In re claim 4, Yu discloses the via holes occupied by vias 144b disposed in the first passivation layer corresponding to the topmost dielectric layer 142 and vias 144b of layer 140 in FIG. 8C.
Yu does not explicitly disclose the via holes are formed by a photolithography process and an etching process.
However, Bao discloses (e.g. FIGs. 1-13) a method for manufacturing a package comprising forming a first rewiring layer 124 on a supporting substrate 102, forming a hybrid bonding structure (¶ 67) between the first rewiring layer 124 and semiconductor chips 50 comprising forming a bonding layer 118+120 that includes a first passivation layer 118, via holes (openings that are filled by 120B) disposed in the first passivation layer 118, and metal material filled in the via holes to form first pads 120B (¶ 27) wherein the via holes (openings in 118) are formed by a photolithography process and an etching process (¶ 21,22,27, where metallization 120 is formed same as 108 which include openings formed by etching through patterned mask).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yu’s bonding layer composed of vias 144b in passivation layer 142 by forming via holes in the passivation layer 142 by a photolithography process and an etching process and filling the via-holes with metal material to form the first pads 144b as taught by Bao to form fine metal patterns to facilitate hybrid bonding between the chips and the first rewiring layer as taught Bao (¶ 67-68).
Response to Arguments
Applicant's arguments filed 8/18/2026 have been fully considered but they are not persuasive.
Regarding Yu US 2021/0028145, Applicant the part of metal line 144b and dielectric 142 of the RDL 140 that is mapped to the “first bonding layer” are not separate from the RDL and does not teach the claimed bonding layer, and fails to teach the claimed hybrid bonding (Remark, pages 10-15).
This is not persuasive. Yu explicitly teaches hybrid bonding between RDL 140 and chip 110 (¶ 17). No specific “first bonding layer” has been claimed that would structurally distinguish over a connecting portion of Yu’s RDL 140 that is hybrid bonded with the chip 110. For example, as shown in annotated FIG. 8C above, the topmost layer of the dielectric 142 teaches the claimed “first passivation layer” and the topmost metal via 144b teaches the claimed “first pads”. No specific “first passivation layer” and “first pads” have been claimed that would structurally distinguish over Yu’s dielectric 142 and metal via 144b.
Regarding Bao US 2022/0310480, Applicant argues Bao does not teach first and second bonding layers comprising passivation layers and pads, there are no vias holes formed in the first passivation layer, and the second rewiring layer is not connected to the first rewiring in the claimed manner (Remark, pages 16-18).
This is not persuasive. Bao teaches first passivation layer 118 on the rewiring layer and second passivation layer 68 on the chip (FIG. 3), the first pads 120B are formed in the first passivation layer 120B, and the second pads 66 are formed in the second passivation layer 68 (FIG. 1). Furthermore, Bao teaches the metallization 120, including pads 120B, “is formed in the openings extending through the dielectric layer 118” (¶ 27). Thus, pads 120B are formed by filling metal material in via holes corresponding to the openings in the dielectric layer 118. The vias 126 in the molding layer 134 are not relied on for teaching the claimed via holes. Rather, the metallization 120 filling the openings of the dielectric layer 118 teaches the claimed filling a metal material in the via holes which forms the first pads 120B.
Bao teaches the claimed hybrid bonding connection structure as the first pads 120B and the second pads 66 are hybrid bonded to each other (¶ 67). Furthermore, Bao is not relied upon for teaching the second rewiring layer or its connection to the first wiring layer.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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