DETAILED ACTION
Response to Arguments
This office action is in response to amendment filed 4/13/2026.
Claims 1-11 are pending. Claims 7-11 have been withdrawn. Claims 1, 4, and 7 have been amended.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. US 2021/0028145 A1 (Yu).
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In re claim 1, Yu discloses (e.g. FIGs. 1A-1F) a method for manufacturing a fan-out packaging unit 10 (¶ 33), comprising:
forming a first rewiring layer 140 (including 142 and 144 except the bottommost layer of 142 that includes the bottom vias 144b) on a supporting substrate C, wherein the first rewiring layer 140 has a first surface (bottom surface) and a second surface (top surface) opposite to the first (bottom) surface, wherein the first rewiring layer 140 comprises at least one inorganic dielectric layer 142 (e.g. silicon oxide, ¶ 19) and at least one first metal wiring layer 144;
forming a hybrid bonding structure (¶ 17) between the first (bottom) surface of the first rewiring layer 140 (bottom surface of dielectric 142 above the lowermost vias 144b) and semiconductor chips 110,120 to electrically couple the semiconductor chips 110,120 to the first (bottom) surface of the first rewiring layer 140;
wherein forming the hybrid bonding structure comprises forming a first bonding layer (bottommost layer of 142 including vias 144b on the side of 140 closest to chips 110,120) on the first (bottom) surface of the first rewiring layer 140, wherein the first bonding layer includes a first passivation layer, via holes (occupied by metal vias 144b) disposed in the first passivation layer, and metal material (metal vias) filled in the via holes to form first pads 144b;
forming a plastic layer 130 (¶ 18) on the first (bottom) surface of the first rewiring layer to form a packaging layer on the semiconductor chips 110,120; and
forming a second rewiring layer 150+160 or 190 or 200 over the second (top) surface of the first rewiring layer 140, wherein the second rewiring layer has a first (bottom) surface and a second (top) surface opposite to the first (bottom) surface, wherein the second rewiring layer 150+160 or 190 or 200 comprises a second metal wiring layer 160 or 194 or 204 exposed from the first (bottom) surface of the second rewiring layer, and wherein the second metal wiring layer 160 or 194 or 204 is electrically connected to the second (top) surface of the first rewiring layer 140.
In re claim 2, Yu discloses (e.g. FIG. 1A) wherein the first rewiring layer 140 comprises two or more inorganic first dielectric layers 142 (including plural dielectric layers above/below each metal lines 144a) and two or more first metal wiring layers 144a, wherein the two or more metal wiring layers 144a are arranged alternately with the two or more inorganic first dielectric layers 142 (plural layers above/below each metal lines 144a).
In re claim 5, Yu discloses (e.g. FIG. 1A) wherein a material of the at least one inorganic dielectric layer 142 comprises one of silicon nitride and silicon oxynitride (silicon oxide, ¶ 19), and wherein a material of the at least one first metal wiring layer 144 comprises one or more of copper, aluminum, nickel, gold, silver, and titanium (¶ 19).
In re claim 6, Yu discloses (e.g. FIG. 1F) wherein forming the second rewiring layer 200 comprises:
forming openings (openings in which UBM 208 are provided) on the second (top) surface of the second rewiring layer 200 to expose the second metal wiring layer 204;
forming a sub-bump metal layer 208 over the openings; and
forming solder balls 210 inside the openings by a ball planting reflow process (¶ 31).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 1 above, and further in view of Chen US 2013/0252383 A1.
In re claim 3, Yu discloses the supporting substrate C may be a glass carrier (¶ 15), where glass silica teaches silicon-based substrate. Yu further discloses removing the carrier C from the final package (FIGs. 1E-1F). Yu does not explicitly disclose the removal of the supporting substrate comprising: thinning the supporting substrate by applying a mechanical grinding process, and then removing the thinned supporting substrate by applying a chemical-mechanical polishing process.
Chen discloses (e.g. FIGs. 2A-2K) a method for manufacturing a package comprises forming rewiring layer 2a on a supporting substrate 20 that is subsequently removed, wherein the removal of the supporting substrate 20 comprising: thinning the supporting substrate 20 by applying a mechanical grinding process (grinding process to reduce the thickness, ¶ 64), and then removing the thinned supporting substrate 20 by applying a chemical-mechanical polishing process (CMP process to remove the remaining portion, ¶ 64), wherein the supporting substrate is a silicon-based substrate (¶ 40).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to remove the supporting substrate C from Yu’s package by mechanical grinding and CMP as taught by Chen to provide a lost cost process to remove the supporting substrate quickly as is well-known in the art.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claim 1 above, and further in view of Bao et al. US 2022/0310480 A2 (Bao).
In re claim 4, Yu discloses the via holes occupied by vias 144b disposed in the first passivation layer corresponding to the bottommost dielectric layer 142 and vias 144b of layer 140.
Yu does not explicitly disclose the via holes are formed by a photolithography process and an etching process.
However, Bao discloses (e.g. FIGs. 1-13) a method for manufacturing a package comprising forming a first rewiring layer 124 on a supporting substrate 102, forming a hybrid bonding structure (¶ 67) between the first rewiring layer 124 and semiconductor chips 50 comprising forming a bonding layer 118+120 that includes a first passivation layer 118, via holes (openings that are filled by 120B) disposed in the first passivation layer 118, and metal material filled in the via holes to form first pads 120B (¶ 27) wherein the via holes (openings in 118) are formed by a photolithography process and an etching process (¶ 21,22,27, where metallization 120 is formed same as 108 which include openings formed by etching through patterned mask).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form Yu’s bonding layer composed of vias 144b in passivation layer 142 by forming via holes in the passivation layer 142 by a photolithography process and an etching process and filling the via-holes with metal material to form the first pads 144b as taught by Bao to form fine metal patterns to facilitate hybrid bonding between the chips and the first rewiring layer as taught Bao (¶ 67-68).
Response to Arguments
Applicant's arguments filed 4/13/2026 have been fully considered but they are not persuasive.
Applicant’s argument against Chen et al. US 10,522,449 and Yu et al. 10,026,716 (Remark, pages 9-13) are not persuasive since these documents were neither cited by Examiner nor relied upon in the rejections.
Regarding Yu US 2021/0028145, Applicant argues 190 and 200 are not directly connected to 142,144 and fails to teach the claimed “hybrid bonding structure” (Remark, pages 13-14).
This is no persuasive. Claim 1 recites hybrid bonding structure between the first wiring layer and the chips. No specific hybrid or direct bonding between the first wiring layer and the second wiring layer is recited in the claim.
Yu teaches first wiring layer 140 is directly bonded to chips 110,120. Yu further teaches first wiring layer 140 is directly bonded to second wiring layer 150.
No specific hybrid bonding structure has been claimed that would distinguish over prior art interpretation as detailed above.
Regarding arguments against Chen US 2013/0252383 and Bao US 2022/0310480 (Remark, pages 14-17) for not teaching the hybrid bonding structure is not persuasive. These references are not relied upon for teaching hybrid bonding structure.
Applicant further argues Bao does not teach via holes filled with metal in Bao’s first rewiring layer 118 because vias 126 are formed above 118 (Remark, page 15).
This is not persuasive. Metal vias correspond to element 120B in dielectric layer 118, the metal via 120B is filled into via holes in layer 118.
Applicant further argues Bao does not teach the second rewiring layer is connected to the first rewiring (Remark, page 15).
This is not persuasive. Bao is not relied upon for teaching the second rewiring layer.
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
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