DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group II as stated in the reply filed on 01/07/2026 is acknowledged. Claims 1-12 have been cancelled and claims 13-32 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 17, 18, 21, 24-26, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over CHIEN et al. (US 20210336130 A1), hereinafter “Chien,” in view of PENG et al. (US 20200365802 A1), hereinafter “Peng,” and WANG et al. (US 20230320229 A1), hereinafter “Wang.”
Re: Independent Claim 13, Chien discloses a manufacturing method of a semiconductor structure (Abstract: method of manufacturing a semiconductor device), comprising:
forming an IMD layer on a conductive layer wherein the IMD layer has a first etch rate (Fig. 3: layer 141 may be silicon oxide which has a first etch rate, i.e., IMD layer, on metal lines 121, i.e., conductive layer; ¶0025: In some embodiments, two or more of the barrier layers 141 through 143 are chosen to have different materials having different etching selectivity properties and are arranged in a stack for improving the etching performance. For example, in some embodiments, the barrier layer 141 is formed of silicon oxide…);
forming an etching slowing layer material on the IMD layer (Fig. 3: layer 142 may be aluminum oxide; ¶0025: …the barrier layer 142 is aluminum oxide.), wherein the etching slowing layer material has a second etch rate (Fig. 3: layer 142 may be aluminum oxide which has a second etch rate; ¶0025: In some embodiments, two or more of the barrier layers 141 through 143 are chosen to have different materials having different etching selectivity properties and are arranged in a stack for improving the etching performance.), …
forming a lower electrode material on the etching slowing layer material (See Figs. 4-7; Fig. 7 shows a lower electrode 132 which is on the etching slowing layer material 142);
forming a MTJ layer structure on the lower electrode material (Fig. 8: MTJ layer 135L; ¶0041: an MTJ layer 135L is deposited in a form of multiple material stacks (not illustrated in FIG. 8) over the bottom electrode layer 131L); and
forming a plurality of recesses to penetrate the MTJ layer structure (See Figs. 12 and 13: Fig. 12 shows the MTJ layer structure prior to recesses formation and Fig. 13 shows recesses formed to penetrate the MTJ layer structure), the lower electrode material (Fig. 4: recesses 132H for lower electrode), and the etching slowing layer material to form a plurality of protrusions (Fig. 4: recesses 132H are formed through the etching slowing layer material 142 which may be aluminum oxide),
…
However, Chien does not clearly disclose wherein the second etch rate is less than the first etch rate;
wherein each protrusion comprises an etching slowing layer formed on the IMD layer, a lower electrode passing through the IMD layer and the etching slowing layer, and a MTJ layer formed on the lower electrode.
In a similar field of endeavor, Peng discloses wherein the second etch rate is less than the first etch rate (¶0013: the protective layer 130 is an aluminum-based layer (Al-based layer). For example, the protective layer 130 is made from AlOx, AlN, AlNyOx, other suitable material, or the combination thereof; ¶0037: In some embodiments where the ILD layer 240 is silicon oxide; ¶0038: protective layer 130 may has a higher etch resistance to the etching process than that of the ILD layer 240 and the dielectric layer 140… an etch rate of the protective layer 130 is slower than that of at least one of the ILD layer 240 and the dielectric layer 140; In other words, Peng discloses aluminum based layer have a second, or slower, etch rate than a silicon oxide layer which has a first, or faster, etch rate.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have chosen different materials having different etching selectivity properties which are arranged in a stack in order to improve etching performance (See Chien, ¶0025).
However, the combination of Chien in view of Peng does not clearly disclose wherein each protrusion comprises an etching slowing layer formed on the IMD layer, a lower electrode passing through the IMD layer and the etching slowing layer, and a MTJ layer formed on the lower electrode.
In a similar field of endeavor, Wang discloses wherein each protrusion comprises an etching slowing layer formed on the IMD layer (Fig. 2 shows a protrusion reaching the IMD layer 30, which would include the etching slowing layer as taught by Chien above; ¶0019: as shown in FIG. 2 , one or more etching process is conducted by using the patterned mask 54 as mask to remove part of the cap layers 40, 42, part of the MTJ stack 38, and part of the IMD layer 30), a lower electrode passing through the IMD layer and the etching slowing layer (Fig. 2: lower electrode 36 passes through IMD layer 30, which would include the etching slowing layer as taught by Chien above), and a MTJ layer formed on the lower electrode (Fig. 2: MTJ stack 38 formed on lower electrode 36).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Re: Claim 17, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 13.
Chien also discloses wherein further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143, which may be SiON, i.e., CMP stop layer material on layer 142, which may be AlOx, i.e., etching slowing layer);
However, Chien does not specifically disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer materials, and the CMP stop layer material is fully removed.
Wang further discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (Fig. 1 shows layer 30, which incorporates Chiens etching slowing layer material as taught above, i.e., layer 142, before forming of recesses; Fig. 2: shows layer 30 which incorporates Chiens etching slowing layer as taught above, after protrusions are formed.), the recesses further penetrate the CMP stop layer materials, and the CMP stop layer material is fully removed (Fig. 2 shows layer 30 after recess protrusions. The only layer remaining is layer 30. Chiens layer 143, as taught above, would be fully removed after the etching process as disclosed in Wang.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Re: Claim 18, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 13.
Wang further discloses wherein in forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (See Figs. 1 and 2), the etching slowing layer forms a lateral surface which is a curved-surface (Fig. 2 shows layer 30 which incorporates layer 142, which may be AlOx, i.e., etching slowing layer, as taught by Chien above and has a lateral surface which is curved.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Re: Independent Claim 21, Chien discloses a manufacturing method of a semiconductor structure (Abstract: method of manufacturing a semiconductor device), comprising:
forming an IMD layer on a conductive layer, wherein the IMD layer has a first etch rate (Fig. 3: layer 141 may be silicon oxide which has a first etch rate, i.e., IMD layer, on metal lines 121, i.e., conductive layer; ¶0025: In some embodiments, two or more of the barrier layers 141 through 143 are chosen to have different materials having different etching selectivity properties and are arranged in a stack for improving the etching performance. For example, in some embodiments, the barrier layer 141 is formed of silicon oxide…);
forming an etching slowing layer material on the IMD layer (Fig. 3: layer 142 may be aluminum oxide; ¶0025: …the barrier layer 142 is aluminum oxide.), wherein the etching slowing layer material has a second etch rate (Fig. 3: layer 142 may be aluminum oxide which has a second etch rate; ¶0025: In some embodiments, two or more of the barrier layers 141 through 143 are chosen to have different materials having different etching selectivity properties and are arranged in a stack for improving the etching performance.), …
forming a through hole to penetrate the etching slowing layer material and the IMD layer (Fig. 4 shows a through hole 132H which penetrates layer 142, which may be AlOx, i.e., etching slowing layer material, and layer 141, which may be SiO, i.e., IMD layer; ¶0037: In FIG. 4, a photoresist layer (not shown) is patterned over the layer stack 140 to expose one or more BEVA holes 132H of the MRAM structure 100_1A.);
forming a lower electrode material on the etching slowing layer material (Fig. 6 shows BEVA material 132 on layer 142, i.e., etching slowing layer material; ¶0038: as shown in FIG. 6, deposition of BEVA material 132 is conducted to be disposed over the lining layer 161 and the layer stack 140. The BEVA material 132 may be composed of conductive materials such as metal.), comprising:
forming a first lower electrode material within the through hole (Fig. 6: lining layer 161, i.e., first lower electrode material); and
forming a second lower electrode material on the first lower electrode material (Fig. 6: BEVA material 132, i.e., second lower electrode material, on lining layer 161, i.e., first lower electrode material);
forming a MTJ layer structure on the lower electrode material (Fig. 8: MTJ layer 135L; ¶0041: MTJ layer 135L is deposited in a form of multiple material stacks); and
However, Chien does not specifically disclose
…wherein the second etch rate is less than the first etch rate;
forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions,
wherein each protrusion comprises an etching slowing layer formed on the IMD layer, a lower electrode passing through the IMD layer and the etching slowing layer, and a MTJ layer formed on the lower electrode.
In a similar field of endeavor, Peng discloses … wherein the second etch rate is less than the first etch rate (¶0013: the protective layer 130 is an aluminum-based layer (Al-based layer). For example, the protective layer 130 is made from AlOx, AlN, AlNyOx, other suitable material, or the combination thereof; ¶0037: In some embodiments where the ILD layer 240 is silicon oxide; ¶0038: protective layer 130 may has a higher etch resistance to the etching process than that of the ILD layer 240 and the dielectric layer 140… an etch rate of the protective layer 130 is slower than that of at least one of the ILD layer 240 and the dielectric layer 140; In other words, Peng discloses aluminum based layer have a second, or slower, etch rate than a silicon oxide layer which has a first, or faster, etch rate.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have chosen different materials having different etching selectivity properties which are arranged in a stack in order to improve etching performance (See Chien, ¶0025).
However, Chien and Peng do not specifically disclose forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions,
wherein each protrusion comprises an etching slowing layer formed on the IMD layer, a lower electrode passing through the IMD layer and the etching slowing layer, and a MTJ layer formed on the lower electrode.
In a similar field of endeavor, Wang discloses forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (See Figs. 1 and 2),
wherein each protrusion comprises an etching slowing layer formed on the IMD layer (Fig. 2 shows a protrusion reaching the IMD layer 30, which would include the etching slowing layer as taught by Chien above; ¶0019: as shown in FIG. 2 , one or more etching process is conducted by using the patterned mask 54 as mask to remove part of the cap layers 40, 42, part of the MTJ stack 38, and part of the IMD layer 30), a lower electrode passing through the IMD layer and the etching slowing layer (Fig. 2: lower electrode 36 passes through IMD layer 30, which would include the etching slowing layer as taught by Chien above), and a MTJ layer formed on the lower electrode (Fig. 2: MTJ stack 38 formed on lower electrode 36).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Re: Claim 24, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 21.
Chien also discloses further comprising:
planarizing the first lower electrode material to form a lower electrode layer in the through hole (Fig. 7 shows lower electrode 132 after CMP; ¶0039: In FIG. 7, the lining layer 161 and the deposited BEVA material 132 are then etched back to level with a top surface of the IMD layer 125. A multi-step chemical mechanical polishing (CMP) may be carried out to form a flat top surface of the BEVA 132 and the lining layer 161.).
Re: Claim 25, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 21.
Chien also discloses wherein further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143, which may be SiON, i.e., CMP stop layer material on layer 142, which may be AlOx, i.e., etching slowing layer);
However, Chien does not specifically disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer materials, and the CMP stop layer material is fully removed.
Wang further discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (Fig. 1 shows layer 30, which incorporates Chiens etching slowing layer material as taught above, i.e., layer 142, before forming of recesses; Fig. 2: shows layer 30 which incorporates Chiens etching slowing layer as taught above, after protrusions are formed.), the recesses further penetrate the CMP stop layer materials, and the CMP stop layer material is fully removed (Fig. 2 shows layer 30 after recess protrusions. The only layer remaining is layer 30. Chiens layer 143, as taught above, would be fully removed after the etching process as disclosed in Wang.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Re: Claim 26, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 21.
Wang further discloses wherein in forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (See Figs. 1 and 2), the etching slowing layer forms a lateral surface which is a curved-surface (Fig. 2 shows layer 30 which incorporates layer 142, which may be AlOx, i.e., etching slowing layer, as taught by Chien above and has a lateral surface which is curved.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Re: Independent Claim 29, Chien discloses a manufacturing method of a semiconductor structure (Abstract: method of manufacturing a semiconductor device), comprising:
forming an IMD layer on a conductive layer, wherein the IMD layer has a first etch rate (Fig. 3: layer 141 may be silicon oxide which has a first etch rate, i.e., IMD layer, on metal lines 121, i.e., conductive layer; ¶0025: In some embodiments, two or more of the barrier layers 141 through 143 are chosen to have different materials having different etching selectivity properties and are arranged in a stack for improving the etching performance. For example, in some embodiments, the barrier layer 141 is formed of silicon oxide…);
forming an etching slowing layer material on the IMD layer (Fig. 3: layer 142 may be aluminum oxide; ¶0025: …the barrier layer 142 is aluminum oxide.), wherein the etching slowing layer material has a second etch rate (Fig. 3: layer 142 may be aluminum oxide which has a second etch rate; ¶0025: In some embodiments, two or more of the barrier layers 141 through 143 are chosen to have different materials having different etching selectivity properties and are arranged in a stack for improving the etching performance.), …
forming a lower electrode material on the etching slowing layer material (See Figs. 4-7; Fig. 7 shows a lower electrode 132 which is on the etching slowing layer material 142);
forming a MTJ layer structure on the lower electrode material (Fig. 8: MTJ layer 135L; ¶0041: an MTJ layer 135L is deposited in a form of multiple material stacks (not illustrated in FIG. 8) over the bottom electrode layer 131L);
forming an upper electrode on the MTJ layer structure (Fig. 8: 133L; ¶0043: A first top electrode layer 133L is deposited over the MTJ layer 135L); and
forming a plurality of recesses to penetrate the MTJ layer structure (See Figs. 12 and 13: Fig. 12 shows the MTJ layer structure prior to recesses formation and Fig. 13 shows recesses formed to penetrate the MTJ layer structure), the lower electrode material (Fig. 4: recesses 132H for lower electrode), and the etching slowing layer material to form a plurality of protrusions (Fig. 4: recesses 132H are formed through the etching slowing layer material 142 which may be aluminum oxide), …
However, Chien does not clearly disclose
… wherein the second etch rate is less than the first etch rate;
… wherein each protrusion comprises an etching slowing layer formed on the IMD layer, a lower electrode passing through the IMD layer and the etching slowing layer, and a MTJ layer formed on the lower electrode.
In a similar field of endeavor, Peng discloses … wherein the second etch rate is less than the first etch rate (¶0013: the protective layer 130 is an aluminum-based layer (Al-based layer). For example, the protective layer 130 is made from AlOx, AlN, AlNyOx, other suitable material, or the combination thereof; ¶0037: In some embodiments where the ILD layer 240 is silicon oxide; ¶0038: protective layer 130 may has a higher etch resistance to the etching process than that of the ILD layer 240 and the dielectric layer 140… an etch rate of the protective layer 130 is slower than that of at least one of the ILD layer 240 and the dielectric layer 140; In other words, Peng discloses aluminum based layer have a second, or slower, etch rate than a silicon oxide layer which has a first, or faster, etch rate.);
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to have chosen different materials having different etching selectivity properties which are arranged in a stack in order to improve etching performance (See Chien, ¶0025).
However, the combination of Chien in view of Peng does not clearly disclose … wherein each protrusion comprises an etching slowing layer formed on the IMD layer, a lower electrode passing through the IMD layer and the etching slowing layer, and a MTJ layer formed on the lower electrode.
In a similar field of endeavor, Wang discloses … wherein each protrusion comprises an etching slowing layer formed on the IMD layer (Fig. 2 shows a protrusion reaching the IMD layer 30, which would include the etching slowing layer as taught by Chien above; ¶0019: as shown in FIG. 2 , one or more etching process is conducted by using the patterned mask 54 as mask to remove part of the cap layers 40, 42, part of the MTJ stack 38, and part of the IMD layer 30), a lower electrode passing through the IMD layer and the etching slowing layer (Fig. 2: lower electrode 36 passes through IMD layer 30, which would include the etching slowing layer as taught by Chien above), and a MTJ layer formed on the lower electrode (Fig. 2: MTJ stack 38 formed on lower electrode 36).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
Claims 14-16, 19, 20, 22, 23, 27, 28, and 30-32 are rejected under 35 U.S.C. 103 as being unpatentable over CHIEN et al. (US 20210336130 A1) in view of PENG et al. (US 20200365802 A1), WANG et al. (US 20230320229 A1), and CHUANG et al. (US 20220157886 A1), hereinafter “Chuang.”
Re: Claim 14, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 13.
Chien also discloses further comprising:
forming a CMP stop layer material on the etching slowing material (¶0025: In some embodiments, the barrier layer 143 is formed of silicon oxide, silicon nitride, silicon oxynitride);
However, the combination of Chien, Peng, and Wang does not clearly disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form the protrusions, the recesses further penetrate the CMP stop layer material, and each protrusion further comprises a CMP stop layer formed on the etching slowing layer.
In a similar field of endeavor, Chuang discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form the protrusions, the recesses further penetrate the CMP stop layer material (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer), and
each protrusion further comprises a CMP stop layer formed on the etching slowing layer (Fig. 8: polish layer 160, i.e., CMP stop layer; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other words, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 15, the combination of Chien, Peng, Wang, and Chuang discloses the semiconductor method as claimed in claim 14.
Chien also discloses further comprising:
forming a hard mask, wherein the hard mask has an opening (See Figs. 3 and 4; ¶0037: In FIG. 4, a photoresist layer (not shown) is patterned over the layer stack 140 to expose one or more BEVA holes 132H of the MRAM structure 100_1A.);
forming a through hole to penetrate the CMP stop layer material through the opening of the hard mask (Fig. 4: through hole 132H penetrates layer 143 which may be silicon oxynitride, i.e., CMP stop layer; ¶0037: FIG. 4, two BEVA holes 132H are formed in the layer stack 140 by a suitable dry etch operation.); and
forming a spacer layer to cover a lateral surface of the etching slowing layer material (Fig. 5: lining layer 161, i.e., spacer layer; ¶0038: lining layer 161 is blanket-formed over the BEVA holes 132H in the memory region 100A and over the layer stack 140 in the logic region 100B.).
Re: Claim 16, the combination of Chien, Peng, Wang, and Chuang discloses the semiconductor method as claimed in claim 14.
Chien also discloses further comprising:
forming a through hole to penetrate the CMP stop layer material and the etching slowing layer material (Fig. 4: through hole 132H penetrates layer 143 which may be silicon oxynitride, i.e., CMP stop layer and layer 142, which may be AlOx, i.e., etching slowing layer; ¶0037: FIG. 4, two BEVA holes 132H are formed in the layer stack 140 by a suitable dry etch operation.); and
forming a lower electrode layer to fill the through hole (Fig. 6: as shown in FIG. 6, deposition of BEVA material 132 is conducted to be disposed over the lining layer 161 and the layer stack 140).
Re: Claim 19, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 13.
Chien also discloses further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143 may be SiON, i.e., CMP stop layer material);
However, Chien does not disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer material, and the CMP stop layer forms a lateral surface which is a curved-surface.
Wang further discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer material (See Figs. 1 and 2; Fig. 1 shows layer 30, which incorporates Chien’s structure including etching slowing layer, i.e., layer 142 and layer 143 which may be SiON, i.e., CMP stop layer material, as taught above; Fig. 2 shows the recesses formed), …
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
However, the combination of Chien, Peng and Wang does not specifically show … the recesses further penetrate the CMP stop layer material, and the CMP stop layer forms a lateral surface which is a curved-surface.
Chuang further discloses … the recesses further penetrate the CMP stop layer material, and the CMP stop layer forms a lateral surface which is a curved-surface (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer; Fig. 8: polish layer 160, i.e., CMP stop layer, forms a lateral surface which is a curved; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other word, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 20, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 13.
Chien discloses further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143 may be SiON, i.e., CMP stop layer material);
However, Chien does not specifically disclose wherein in forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer material, each of the CMP stop layer and the etching slowing layer forms a lateral surface, and the lateral surface of the etching slowing layer and the lateral surface of the CMP stop layer are connected to each other.
Wang further disclose wherein in forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (See Figs. 1 and 2; Fig. 1 shows layer 30, which incorporates Chien’s structure including etching slowing layer, i.e., layer 142 and layer 143 which may be SiON, i.e., CMP stop layer material, as taught above; Fig. 2 shows the recesses formed), …
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
However, the combination of Chien, Peng and Wang does not specifically disclose the recesses further penetrate the CMP stop layer material, each of the CMP stop layer and the etching slowing layer forms a lateral surface, and the lateral surface of the etching slowing layer and the lateral surface of the CMP stop layer are connected to each other.
Chuang further discloses the recesses further penetrate the CMP stop layer material (Fig. 8 shows recess penetrate polish layer 160, i.e., CMP stop layer), each of the CMP stop layer and the etching slowing layer forms a lateral surface (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer; Fig. 8: polish layer 160, i.e., CMP stop layer, forms a lateral surface which is a curved; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other words, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.), and the lateral surface of the etching slowing layer and the lateral surface of the CMP stop layer are connected to each other (Fig. 8 shows polish layer 160 and layer 150 which are connected to each other).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 22, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 21.
Chien further discloses further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143, which may be SiON, i.e., CMP stop layer material on layer 142, which may be AlOx, i.e., etching slowing layer);
However, the combination of Chien, Peng, and Wang does not clearly disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form the protrusions, the recesses further penetrate the CMP stop layer material, and each protrusion further comprises a CMP stop layer formed on the etching slowing layer.
In a similar field of endeavor, Chuang discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form the protrusions, the recesses further penetrate the CMP stop layer material (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer), and
each protrusion further comprises a CMP stop layer formed on the etching slowing layer (Fig. 8: polish layer 160, i.e., CMP stop layer; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other words, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 23, the combination of Chien, Peng, Wang, and Chuang discloses the semiconductor method as claimed in claim 22.
Chien also discloses further comprising:
forming a hard mask, wherein the hard mask has an opening (See Figs. 3 and 4; ¶0037: In FIG. 4, a photoresist layer (not shown) is patterned over the layer stack 140 to expose one or more BEVA holes 132H of the MRAM structure 100_1A.);
wherein in forming the through hole to penetrate the etching slowing layer material and the IMD layer, the through hole penetrates the CMP stop layer material (See Figs. 3 and 4), the etching slowing layer material and the IMD layer through the opening of the hard mask (Fig. 4: through hole 132H penetrates layer 143 which may be silicon oxynitride, i.e., CMP stop layer; ¶0037: FIG. 4, two BEVA holes 132H are formed in the layer stack 140 by a suitable dry etch operation.);
the semiconductor method further comprises: forming a spacer layer to cover a lateral surface of the etching slowing layer material (Fig. 5: lining layer 161, i.e., spacer layer; ¶0038: lining layer 161 is blanket-formed over the BEVA holes 132H in the memory region 100A and over the layer stack 140 in the logic region 100B.).
Re: Claim 27, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 21.
Chien also discloses further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143 may be SiON, i.e., CMP stop layer material);
However, Chien does not disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer material, and the CMP stop layer forms a lateral surface which is a curved-surface.
Wang further discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer material (See Figs. 1 and 2; Fig. 1 shows layer 30, which incorporates Chien’s structure including etching slowing layer, i.e., layer 142 and layer 143 which may be SiON, i.e., CMP stop layer material, as taught above; Fig. 2 shows the recesses formed),…
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
However, the combination of Chien, Peng and Wang does not specifically show … and the CMP stop layer forms a lateral surface which is a curved-surface.
Chuang further discloses … and the CMP stop layer forms a lateral surface which is a curved-surface (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer; Fig. 8: polish layer 160, i.e., CMP stop layer, forms a lateral surface which is a curved; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other words, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 28, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 21.
Chien discloses further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143 may be SiON, i.e., CMP stop layer material);
However, Chien does not specifically disclose wherein in forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions, the recesses further penetrate the CMP stop layer material, each of the CMP stop layer and the etching slowing layer forms a lateral surface, and the lateral surface of the etching slowing layer and the lateral surface of the CMP stop layer are connected to each other.
Wang further discloses wherein in forming a plurality of recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form a plurality of protrusions (See Figs. 1 and 2; Fig. 1 shows layer 30, which incorporates Chien’s structure including etching slowing layer, i.e., layer 142 and layer 143 which may be SiON, i.e., CMP stop layer material, as taught above; Fig. 2 shows the recesses formed),…
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application. One of ordinary skill would have been motivated to modify Chien’s MRAM process, which already uses an aluminum oxide etch-slowing barrier for improved etch control) by integrating Wang’s ULK dielectric management and selective etching techniques around the resulting MTJ protrusions to address known problem of etch-induced damage to low-k materials (See Wang, ¶¶0005-0006).
However, the combination of Chien, Peng and Wang does not specifically disclose … the recesses further penetrate the CMP stop layer material, each of the CMP stop layer and the etching slowing layer forms a lateral surface, and the lateral surface of the etching slowing layer and the lateral surface of the CMP stop layer are connected to each other.
Chuang further discloses … the recesses further penetrate the CMP stop layer material (Fig. 8 shows recess penetrate polish layer 160, i.e., CMP stop layer), each of the CMP stop layer and the etching slowing layer forms a lateral surface (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer; Fig. 8: polish layer 160, i.e., CMP stop layer, forms a lateral surface which is a curved; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other words, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.), and the lateral surface of the etching slowing layer and the lateral surface of the CMP stop layer are connected to each other (Fig. 8 shows polish layer 160 and layer 150 which are connected to each other).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 30, the combination of Chien, Peng, and Wang discloses the semiconductor method as claimed in claim 29.
Chien also discloses further comprising:
forming a CMP stop layer material on the etching slowing material (Fig. 4: layer 143, which may be SiON, i.e., CMP stop layer material on layer 142, which may be AlOx, i.e., etching slowing layer);
However, the combination of Chien, Peng, and Wang does not clearly disclose wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form the protrusions, the recesses further penetrate the CMP stop layer material, and each protrusion further comprises a CMP stop layer formed on the etching slowing layer.
In a similar field of endeavor, Chuang discloses wherein in forming the recesses to penetrate the MTJ layer structure, the lower electrode material, and the etching slowing layer material to form the protrusions, the recesses further penetrate the CMP stop layer material (Fig. 7 shows polish layer 160, i.e., CMP stop layer material; Fig. 8 shows forming of recesses which penetrate the polish layer, i.e., CMP stop layer), and
each protrusion further comprises a CMP stop layer formed on the etching slowing layer (Fig. 8: polish layer 160, i.e., CMP stop layer; ¶0015: In some embodiments, the dielectric layer 150 may include a carbon atomic concentration greater than that of the polish stop layer 160, such that the dielectric layer 150 may have a higher etch resistance to the subsequent ion-beam etching (IBE) process than that of the polish stop layer 160. In other words, an etch rate of the dielectric layer 150 is slower than that of the polish stop layer 160 during the IBE process.).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the current application to further modify the combined teachings of Chien, Peng, and Wang by incorporating the polish stop layer taught by Chuang to achieve precise control over the chemical mechanical polishing process when planarizing the bottom electrode via while protecting the underlying dielectric layers and maintaining planarity across logic and memory areas (See Chuang, ¶0016).
Re: Claim 31, the combination of Chien, Peng, Wang, and Chuang discloses the semiconductor method as claimed in claim 30.
Chien also discloses further comprising:
forming a hard mask, wherein the hard mask has an opening (See Figs. 3 and 4; ¶0037: In FIG. 4, a photoresist layer (not shown) is patterned over the layer stack 140 to expose one or more BEVA holes 132H of the MRAM structure 100_1A.);
forming a through hole to penetrate the CMP stop layer material through the opening of the hard mask (Fig. 4: through hole 132H penetrates layer 143 which may be silicon oxynitride, i.e., CMP stop layer; ¶0037: FIG. 4, two BEVA holes 132H are formed in the layer stack 140 by a suitable dry etch operation.); and
forming a spacer layer to cover a lateral surface of the etching slowing layer material (Fig. 5: lining layer 161, i.e., spacer layer; ¶0038: lining layer 161 is blanket-formed over the BEVA holes 132H in the memory region 100A and over the layer stack 140 in the logic region 100B.).
Re: Claim 32, the combination of Chien, Peng, Wang, and Chuang discloses the semiconductor method as claimed in claim 30.
Chien also discloses further comprising:
forming a through hole to penetrate the CMP stop layer material and the etching slowing layer material (Fig. 4: through hole 132H penetrates layer 143 which may be silicon oxynitride, i.e., CMP stop layer and layer 142, which may be AlOx, i.e., etching slowing layer; ¶0037: FIG. 4, two BEVA holes 132H are formed in the layer stack 140 by a suitable dry etch operation.); and
forming a lower electrode layer to fill the through hole (Fig. 6: as shown in FIG. 6, deposition of BEVA material 132 is conducted to be disposed over the lining layer 161 and the layer stack 140).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
IGARISHI et al. (US 20240074327 A1) – Figs. 3, 13, 14, and 22 disclose structure relevant to the current claims.
CHIU et al. (US 20200106000 A1) – Figs. 7-10 disclose structure relevant to the current claims.
LI et al. (US 20210005662 A1) – Figs. 1-5 disclose structure relevant to the current claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM ADROVEL whose telephone number is (571)272-3048. The examiner can normally be reached 7:30 AM - 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEONARD CHANG can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM ADROVEL/Examiner, Art Unit 2898
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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