Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 4 March, 2026 was filed after the mailing date of the non-final rejection on 23 January, 2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments: Title
Applicant’s arguments, see page 7, lines 22-29, filed 24 March 2026, with respect to the title have been fully considered and are persuasive. The objection of the title has been withdrawn.
Response to Arguments Drawings
Applicant’s arguments, see page 7, lines 7-20, filed 24 March 2026, with respect to the drawings have been fully considered and are persuasive. The objections to all Figures 1-6 have been withdrawn.
Response to Arguments Claim Rejections under 35 U.S.C. § 112
Applicant’s arguments, see page 8, lines 1-6, filed 24 March 2024, with respect to claims 6 and 14 have been fully considered and are persuasive. Both the objections and rejections of claims 6 and 14 have been withdrawn.
Applicant’s arguments, see lines 1-11, page 8, filed 24 March 2026, with respect to former claim 8 have been fully considered and are persuasive. The rejection of former claim 8 has been withdrawn.
Examiner’s Noter: The withdrawal of the rejection only applies to the 35 USC § 112(b) rejection.
Response to Arguments Claim Rejections under 35 U.S.C. § 102 and § 103
Applicant's arguments filed 24 March 2026 have been fully considered but they are not persuasive. Kim does disclose a potential negative side effect of using silicic acid the benefits of increased etch selectivity would warrant experimentation to determine optimal concentrations. Merely noting a potential difficulty with an embodiment does not constitute teaching away, See MPEP 2123 II.
Claim Rejections – USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 9, 10 13, 14 and 15, are rejected under 35 U.S.C. 103 as being anticipated by Kim et. al. (U.S. 20200071614), hereinafter referred to as Kim.
Regarding claim 1, Kim teaches an etching method of a semiconductor structure (para. 178), comprising:
providing a substrate with a gate structure disposed thereon (Kim, para. 181), an oxide layer and a first nitride layer are disposed beside the gate structure (Kim, para. 3); and performing an etching step to remove the first nitride layer and keep the oxide layer (Kim, para. 74), wherein in the etching step, the etching selectivity ratio of etching a nitride material to etching an oxide material is greater than 300 (Kim, Para. 37), wherein the etching step comprises etching with a phosphoric acid solution (Kim, Para. 60) containing silicic acid (Kim, para. 61).
Kim does not explicitly teach the concentration of the silicic acid contained in the phosphoric acid solution is higher than 3.5ppm
However, Kim acknowledges that dissolving silicic acid in phosphoric acid can improve the etch selectivity ratio of silicon nitride relative to silicon oxide—an effect that is highly desirable for precise semiconductor processing (Kim, Para. 61). However, it also warns that excessive silicic acid concentration may lead to undesirable effects such as precipitate formation and abnormal oxide growth. Thus, the concentration of silicic acid is not merely a process parameter but a result-effective variable:
If too low, selectivity is insufficient and oxide damage may occur.
If too high, precipitates form and abnormal oxide growth may result.
Within the optimal window, selectivity is maximized and side effects are minimized, enabling reliable, simplified processing.
Because the prior art recognizes that silicic acid concentration in phosphoric acid solutions directly affects etch selectivity and also cautions about excessive concentrations leading to undesirable effects, the concentration is a result-effective variable. Therefore, it would have been obvious for one of ordinary skill in the art to optimize this variable through routine experimentation. The selection of a concentration higher than 3.5 ppm would be a predictable result of such optimization, absent evidence of unexpected results or criticality associated specifically with the 3.5 ppm threshold (See MPEP 2144.05 II).
Regarding claim 9, Kim teaches the etching method of the semiconductor structure according to claim 7, wherein the temperature of the phosphoric acid solution is between 150 and 160 degrees Celsius (Kim, Para. 60 and Para. 197).
Regarding claim 10, Kim teaches the method for etching a semiconductor structure according to claim 7, but does not explicitly state wherein after the etching step, the etching selectivity of the phosphoric acid solution for etching the nitride material and etching the oxide material gradually increases.
Kim does teach that in order to improve the etch selectivity ratio of the silicon nitride layer with respect to the silicon oxide layer, a silicon nitride layer etching composition in which a silicic acid is dissolved in the phosphoric acid may be used (Kim, Para. 61). Kim additionally teaches that the etching composition containing phosphoric acid is continuously concentrated by evaporation of water at high temperature (Kim, Para. 60). In addition to concentrating the phosphoric acid component, the silicic acid will likewise be concentrated, causing increased etching selectivity.
Regarding claim 13, Kim teaches the etching method of the semiconductor structure according to claim 7, wherein the rate of etching the nitride material by the phosphoric acid solution is more than 45 angstroms per minute (Kim, Table 3).
Regarding claim 14, Kim teaches the etching method of the semiconductor structure according to claim 7, wherein the rate of etching the oxide material by the phosphoric acid solution is below 0.15 angstrom per minute (Kim, Table 3).
Regarding claim 15, Kim teaches the method for etching a semiconductor structure according to claim 1, but does not teach wherein after the etching step, the surface of the substrate next to the gate structure is lowered, and the lowered height is within 30 angstroms.
Kim acknowledges that the substrate may be formed of various materials such as silicon, quartz, glass, silicon wafer, polymer, metal, and metal oxide, but the material of the substrate is not limited thereto (Kim, para. 188). The etchant being used has been selected for a high etch selectivity, especially with regards to silicon oxide. This increased selectivity also resulted in reduced exposures and reduced etching times which further limit the damage to the substrate.
Thus, the selection of substrate material is not merely a process parameter but a result effective variable.
Certain materials will be more highly etched and will cause lowering of more than 30 Å.
A selection the proper material would minimize damage to the substrate, thereby reducing substrate defects.
Because the prior art recognizes that the substrate material and etching selectivity of the etchant directly affect the depth by which the surface of the substrate is lowered, the lowering is a direct result of the substrate material. Therefore it would have been obvious for one of ordinary skill in the art, prior to the filing date, to optimize this variable through routine experimentation. The selection of a proper substrate material would be a predictable response of such optimization, absent evidence of unexpected results.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Lee et. al (U.S. 20040175890), hereinafter referred to as Lee.
Regarding claim 2, Kim teaches the etching method of the semiconductor structure according to claim 1.
Kim fails to teach the oxide layer has a U-shaped cross section and is located at a bottom and two sidewalls of the gate structure.
However, Lee teaches a U-shaped cross section and is located at a bottom and two sidewalls of the gate structure, (Lee, 212, 252, Fig. 3A). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee and create their semiconductor structure such that the oxide layer has a U-shaped cross section and is located at a bottom and two sidewalls of the gate structure to create the gate structure to create the gate structure with the sidewalls acting as a buffer layer (Lee, paras. 46-47).
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Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Oh et. al. (US 20230215926), hereinafter referred to as Oh.
Regarding claim 3, Kim teaches the etching method of the semiconductor structure according to claim 1, but does not teach further comprising forming a mask layer on a top surface of the gate structure.
However, Oh teaches multiple gate structures (Oh, Fig. 1-3) covered by masks (Oh, 114, Fig 2). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Oh and create masks to protect the gate structures during the creation of the PMOS and NMOS source/drain regions (Oh, para. 22).
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Claims 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Oh and further in view of Ho et al. (US 20230064376) hereinafter referred to as Ho.
Regarding claim 4, Modified Kim teaches the etching method of the semiconductor structure according to claim 3. Modified Kim does not teach further forming a second nitride layer covering an outer sidewall of the first nitride layer, part of the surface of the substrate and the top surface and sidewall of the mask layer.
However, Ho, in Fig. 10, teaches a second nitride layer (Ho, 147, Fig. 10) covering an outer sidewall of the first nitride layer (Ho, 145, Fig. 10), part of the surface of the substrate (Ho, 102, Fig. 10) and the top surface and sidewall of the mask layer (Ho, 134, Fig. 10)
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Oh and create a second nitride layer covering an outer sidewall of the first nitride layer, part of the surface of the substrate and the top surface and sidewall of the mask layer as a hard mask, to provide stress in the amorphized regions (Ho, para. 23).
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Regarding claim 5, modified Kim discloses the etching method of the semiconductor structure according to claim 4, wherein in the etching step (Ho: figs 11-15), the first nitride layer (Ho, 145, Fig. 10), the second nitride layer (Ho, 147, Fig. 10) and the mask layer (Ho, 134, Fig. 10) are all removed (Ho: fig 15).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ho and use the etching step to remove the nitride and mask layers to form the gate structure.
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Regarding claim 6, modified Kim teaches the semiconductor etching method of the semiconductor structure according to claim 4, wherein after the second nitride layer (Ho, 147, Fig. 10) is formed, until the etching step is performed (Ho, Fig. 11), no other spacers composed of oxide layer or nitride layer are formed. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Ho and not create any more nitride or oxide layers until the etching step was performed, thus simplifying fabrication.
Claims 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Kaji et. al (U.S. Patent 4980017), hereinafter referred to as Kaji.
Regarding claim 11, Kim teaches the method for etching a semiconductor structure according to claim 7, but does not teach wherein after the etching step, an acid concentration adjustment step is further performed, a part of the phosphoric acid solution is poured out, and a new phosphoric acid solution is added and mixed.
Kaji teaches a method for recirculating high temperature etching solution. In this method Kaji teaches that the concentration and temperature distribution of the etching solution within the etching bath can be always kept constant. This is accomplished by removing a portion of the solution through an overflow weir and recirculated after being injected with pure water and heated to the required temperature. (Kaji, col 3, lines 3-46). Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to combine the incorporate the teachings of Kaji and incorporate a method to refresh the etching solution, thereby extending its useful life.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Kaji and in further view of Kim. Kim and Kaji teach the method for etching a semiconductor structure according to claim 11, but do not explicitly teach wherein after adding the new phosphoric acid solution, the etching selectivity of the phosphoric acid solution for etching the nitride material and etching the oxide material decreases.
Kim teaches that to improve the etch selectivity ratio of the silicon nitride layer with respect to the silicon oxide layer, a silicon nitride layer etching composition in which a silicic acid is dissolved in the phosphoric acid may be used (Kim, para. 61). A result of heating the phosphoric acid solution is the concentration of the solution via evaporation of the water component (Kim para. 61). This causes a rise in the silicic acid concentration, thereby increasing the etch selectivity. Likewise, a result of removing some of the etchant and replacing it with a new phosphoric acid solution is to decrease the concentration of the silicic acid and decrease the etching sensitivity of the solution.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Ho.
Regarding claim 16, Kim teaches the semiconductor etching method of the semiconductor structure according to claim 1. Kim fails to teach forming a second gate structure, which is located next to the gate structure and comprises another oxide layer and another nitride layer.
However, Ho teaches pair of gate structures, being formed in adjoining regions of the substrate (Ho, 102, Fig 13) which comprise oxide (Ho, 130, Fig. 13) and nitride (Ho, 147, Fig. 13) layers. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Lee and create a second gate structure, creating a planar transistor (Ho, para. 9).
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Regarding claim 17, modified Kim teaches the semiconductor etching method of the semiconductor structure according to claim 16, wherein after the etching step (Ho, Fig. 16), the other oxide layer (Ho, 130 Fig. 16) has been replaced by a gate dielectric layer (Ho, 166, Fig 16) which is made up of the same materials (Kim, Para. 37) and the other nitride layer (Ho, 147, Fig 10) is removed.
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to combine the teachings of modified Kim and Ho to create an etching step wherein the other oxide layer is left and the nitride layer has been removed to form a planar transistor.
Claims 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kim, in view of Ho, in further view of Oh.
Regarding claim 18, modified Kim teaches the semiconductor etching method of the semiconductor structure according to claim 16. Ho further teaches forming a mask layer on the top surface of the gate structure and forming a second mask layer on the top surface of the second gate structure (Ho, 134, Fig 9). Ho does not teach wherein the thickness of the mask layer is different from the thickness of the second mask layer.
However, Oh teaches a plurality of gate structures (Oh, Fig 4A) wherein the thickness of the mask layers (Oh, Fig. 114,4A) is different between the NMOS gates (Region A) and the PMOS gates (region B).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to further incorporate the teachings of Oh and form a mask layer on the top surface of the gate structure and form a second mask layer on the top surface of the second gate structure, wherein the thickness of the mask layer is different from the thickness of the second mask layer. The difference in the thickness of the masks is a result of the process used to create the source/drain regions for the two types of gates (Oh, para. 22).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hackett et. al. (US Patent 6162370) shows a phosphoric acid solution with 100 ppm of silicic acid.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 7:30-5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/Supervisory Patent Examiner, Art Unit 2893
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