Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-6, 9, 13, 14, 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ho et al (US 20230064376), hereinafter referred to as Ho and Hackett et al. (US 6162370), hereinafter referred to as Hackett.
Regarding claim 1, Ho teaches an etching method of a semiconductor structure, comprising: providing a substrate (Ho, 102, Fig. 9, para. 8) with a gate structure (Ho, 128, Fig. 9, para. 12, the one in 101A) disposed thereon, an oxide layer (Ho, 130,140, Fig. 9, paras. 12, 15) and a first nitride layer (Ho, 145, Fig. 9, paras. 22, shows it may be an oxynitride) are disposed beside the gate structure; and performing an etching step to remove the first nitride layer and keep the oxide layer Ho, Fig. 11, para. 32,).
Ho does not teach, wherein in the etching step, the etching selectivity ratio of etching a nitride material to etching an oxide material is greater than 300, wherein the etching step comprises etching with a phosphoric acid solution containing silicic acid, and the concentration of the silicic acid contained in the phosphoric acid solution is higher than 3.5ppm, and wherein after the etching step, a surface of the substrate next to the gate structure is lowered, and a lowered height of the surface of the substrate is within 30 angstroms.
However, Hackett teaches an etching composition wherein the etch selectivity is effectively infinite (Hackett, Table 1, Run 11 at 160° C) using a phosphoric acid solution containing silicic acid (Hackett, Col. 4, lines 55-62, describes the preparation of the solution by dissolving SiO2 into H2PO4,) and the concentration of dissolved SiO2 contained in the etching solution is 100 ppm (Hackett Table 5, Run 11).
NOTE: Dissolving SiO2 into H2PO4, form Si(OH)4, orthosilicic acid.
Therefore it would have been obvious to one of ordinary skill in the art to combine the method of Ho with the etchant of Hackett in order to effectively increase the etch rate of silicon nitride relative to silicon dioxide (Hackett, Col. 2, lines 56-57).
Hackett is silent on whether the substrate would be lowered, or by how much. However the increased selectivity of Hackett would serve to reduce the level of damage. The etchant of Hackett has been designed with a high selectivity between silicon oxide and silicon nitride, and a high etch rate for silicon nitride. Because the selectivity is essentially infinity (Hackett, Table 1, Run 11 at 160° C) the damage to the substrate would be substantially reduced. The current application, in paras. states that when the etching step E3 has an etch selectivity of 346 the substrate damage was 26Å, while at an etch selectivity of 51 it was 46Å. Therefore the effectively infinite etch selectivity of Hackett would further reduce the damage to the substrate.
Regarding claim 2, modified Ho teaches the etching method of the semiconductor structure according to claim 1, wherein the oxide layer has a U-shaped cross section and is located at a bottom and two sidewalls of the gate structure (Ho, 130, 140, Fig. 9).
Regarding claim 3, modified Ho teaches the etching method of the semiconductor structure according to claim 1, further comprising forming a mask layer on a top surface of the gate structure (Ho, 134, Fig. 9. Para. 12).
Regarding claim 4, modified Ho teaches the etching method of the semiconductor structure according to claim 3, further comprising forming a second nitride layer (Ho, 147, paras. 22-23) covering an outer sidewall of the first nitride layer, part of the surface of the substrate and the top surface and sidewall of the mask layer
Regarding claim 5, modified Ho teaches the etching method of the semiconductor structure according to claim 4, wherein in the etching step, the first nitride layer (Ho, 145, Fig. 11, para. 32), the second nitride layer (Ho, 147, Fig. 11, para. 32) and the mask layer are all removed (Ho, 134, Fig. 15, para. 36).
Regarding claim 6, modified Ho teaches the etching method of the semiconductor structure according to claim 4, wherein after the second nitride layer (Ho, 147, Fig. 10) is formed, until the etching step is performed (Ho, Fig. 11), no other spacers composed of oxide layer or nitride layer are formed.
Regarding claim 9, modified Ho teaches the etching method of the semiconductor structure according to claim 1, wherein the temperature of the phosphoric acid solution is between 150 and 160 degrees Celsius (Hackett, Table 1, Run 11, shows it at 160 degrees Celsius).
Regarding claim 13, modified Ho teaches the etching method of the semiconductor structure according to claim 1, wherein the rate of etching the nitride material by the phosphoric acid solution is more than 45 angstroms per minute (Hackett, Table 1, Run 11, 160 degrees Celsius, shows it at 5.2 nm/minute, or 52 Å/min)
Regarding claim 14, modified Ho teaches the etching method of the semiconductor structure according to claim 1, wherein the rate of etching the oxide material by the phosphoric acid solution is below 0.15 angstroms per minute (Hackett, Table 1, Run 11, 160° Celsius, shows it at 0.00 nm/minute, or 0.0 Å/min).
Regarding claim 16, modified Ho teaches The etching method of the semiconductor structure according to claim 1, further comprising forming a second gate structure (Ho, 128, Fig. 9, para. 12, the one in 101B), which is located next to the gate structure and comprises another oxide layer (Ho, 130,140, Fig. 9, paras. 12, 15) and another nitride layer (Lee, 145, Fig. 9, paras. 22, shows it may be an oxynitride).
Regarding claim 17, modified Ho teaches The etching method of the semiconductor structure according to claim 16, wherein after the etching step, the other oxide layer is left and the other nitride layer is removed (Ho, 145, Fig. 11)
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ho and Hackett as applied to claim 1 above, and further in view of . Kaji et. al. (US 4980017).
Regarding claim 10, modified Ho teaches the etching method of the semiconductor structure according to claim 1, but does not explicitly teach wherein after the etching step, the etching selectivity of the phosphoric acid solution for etching the nitride material and etching the oxide material gradually increases.
Hackett does teach using a boiling (Hackett, Col..1 , lines 53-56) phosphoric acid bath, and demonstrates (Hackett, table 1, Run 11, 160° C) that the inclusion of silicic acid increases etch selectivity. The solution of Hackett at 160°C
Hackett does not explicitly state the solution will therefore lose water through evaporation.
However, Kaji does state that the water in a phosphoric acid solution is evaporated by heating, resulting in an increase concentration of the solution (Kaji, Col. 2, lines 3-8). Because the etch selectivity is tied to the silicic acid concentration it would thereby increase the selectivity as some of the solution boils away.
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to combine the incorporate the teachings of Kaji into the method of Ho and Hackett,
Regarding claim 11, modified Ho teaches the method for etching a semiconductor structure according to claim 7, but does not teach wherein after the etching step, an acid concentration adjustment step is further performed, a part of the phosphoric acid solution is poured out, and a new phosphoric acid solution is added and mixed.
However, Kaji teaches a method for recirculating high temperature etching solution. In this method Kaji teaches that the concentration and temperature distribution of the etching solution within the etching bath can be always kept constant (Kaji, col 3, lines 3-46). This is accomplished by removing a portion of the solution through an overflow weir (Kaji,3, Fig. 1, Col 4, lines 51-53). The removed portion is then filtered (Kaji, 9, Fig. 1, Col 4, line 53) and injected with pure water to maintain the required concentration (Kaji, Col. 4, lines 62-68). Then the resulting etching solution is heated to the proper temperature (Kaji, Col. 4, lines 57-61) and recirculated from the bottom of the etching bath. (Kaji, col 4, lines 54-56).
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to combine the incorporate the teachings of Kaji and incorporate a method to refresh the etching solution, thereby extending its useful life.
Regarding claim 12, modified Ho teaches the method for etching a semiconductor structure according to claim 11, but does not explicitly teach wherein after adding the new phosphoric acid solution, the etching selectivity of the phosphoric acid solution for etching the nitride material and etching the oxide material decreases.
Hackett teaches that to improve the etch selectivity ratio of the silicon nitride layer with respect to the silicon oxide layer, a silicon nitride layer etching composition in which a silicic acid is dissolved in the phosphoric acid may be used (Hackett, Table 1, Run 11, °160 C).
Kaji teaches that a result of heating the phosphoric acid solution is the concentration of the solution via evaporation of the water (Kaji, Col. 2, lines 3-8). This will concentrate both the phosphoric acid component and the silicic acid component. Because the etch selectivity is tied to the silicic acid concentration it would thereby increase the selectivity as some of the solution boils away. Likewise, as the solution is refreshed and the concentration of silicic acid is reduced, the etch selectivity is likewise reduced.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Ho and Hackett as applied to claim 17 above, and further in view of Oh (US Pub. 20230215926)
Regarding claim 18, modified Ho teaches he etching method of the semiconductor structure according to claim 16, further comprising forming a mask layer on the top surface of the gate structure and forming a second mask layer on the top surface of the second gate structure,
Modified Ho does not teach wherein the thickness of the mask layer is different from the thickness of the second mask layer.
However, Oh teaches multiple gate structures (Oh, 112, Fig. 4A, para. 43) covered by masks (Oh, 114, Fig. 4A, para. 41) , wherein the thickness of the mask layers (Oh, 114, Fig. 4A) is different between the NMOS gates (Oh, Fig. 4A, Region A, para. 23) and the PMOS gates (Oh, Fig. 4A, region B, para. 23).
Therefore it would have been obvious to someone of ordinary skill in the art before the effective filing date of the invention to further incorporate the masks of Oh while forming the source/drain regions for the gates (Oh, para. 22)
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Examiner does not concede that Kim teaches against the use of silicic acid. Kim teaches that the use of silicic acid may cause precipitates which may increase difficulty, but does not state that using so is actively harmful to the process, and therefore does not constitute teaching away. Therefore using the using the combination of Kim’s etch selectivity of 300 and the inclusion of silicic acid in phosphoric acid does not qualify as impermissible hindsight.
Examiner does not concede that the combination and substrate are not result effective variables. The etch selectivity between the oxide and the substrate is the key factor in determining the lowering of the substrate. If the selectivity is low between the oxide layer and the substrate the substrate will necessarily be lowered more than if the etch selectivity is high, therefore the selection of the proper material for the substrate is a defining factor.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hara et al. (US Pub 20080203060) teaches an etching composition using silicic acid and phosphoric acid with an etching selectivity over 300.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIERAN M CUNNINGHAM whose telephone number is (571)272-9654. The examiner can normally be reached Mon-Fri 8:00-4:3.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 5712703042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KIERAN M. CUNNINGHAM/Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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