DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-11 in the reply filed on 12/18/25 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 and 11 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US pub 20080017961).
With respect to claim 1, Lin et al. teach a package structure, comprising (see figs. 1-3H, particularly figs. 3D and 3F and associated text):
a first substrate 210 (left portion) including a first patterned circuit layer 230 (left portion) and defining a first through hole 216 (left portion);
a first electronic component 220 (left portion) disposed over the first through hole of the first substrate, wherein the first electronic component is electrically connected to the first patterned circuit layer of the first substrate through an extending portion of the first patterned circuit layer extending beyond a sidewall of the first through hole;
a second substrate 210 (right portion) including a second patterned circuit layer 230 (right portion) and defining a second through hole 216 (right portion); and
a second electronic component 220 (right portion) disposed over the second through hole of the second substrate, wherein the second electronic component is electrically connected to the second patterned circuit layer of the second substrate through an inner extending portion of the second patterned circuit layer extending beyond a sidewall of the second through hole.
With respect to claim 2, Lin et al. teach the first substrate has a first surface (top) and a second surface (bottom) opposite to the first surface, and the first electronic component is attached to the first surface of the first substrate. See fig. 3D and 3F and associated text.
With respect to claim 3, Lin et al. teach a first active surface (bottom) of the first electronic component has a first portion (middle) and a second portion (edge), the first portion of the first active surface of the first electronic component is exposed in the first through hole of the first substrate, and the second portion of the first active surface of the first electronic component is adhered to the first surface of the first substrate through a first adhesion layer (layer between 220 and 210). See fig. 3D and 3F and associated text.
With respect to claim 4, Lin et al. teach the second portion of the first active surface of the first electronic component surrounds the first portion of the first active surface of the first electronic component. See fig. 3D and 3F and associated text.
With respect to claim 5, Lin et al. teach the first patterned circuit layer is disposed adjacent to the first surface of the first substrate. See fig. 3D and 3F and associated text.
With respect to claim 6, Lin et al. teach the first electronic component includes at least one first bump 224 disposed adjacent to a first active surface thereof, and the extending portion of the first patterned circuit layer is connected to the at least one first bump of the first electronic component. See fig. 3D and 3F and associated text.
With respect to claim 7, Lin et al. teach a package body 240 (under 220) disposed in the first through hole of the first substrate and encapsulating the extending portion of the first patterned circuit layer, wherein the package body contacts a first active surface of the first electronic component. See fig. 3D and 3F and associated text.
With respect to claim 8, Lin et al. teach the package body is further disposed on the first surface of the first substrate and encapsulating the first electronic component and the second electronic component. See fig. 3D and 3F and associated text.
With respect to claim 9, Lin et al. teach the extending portion of the first patterned circuit layer and the first patterned circuit layer are at the same layer. See fig. 3D and 3F and associated text.
With respect to claim 11, Lin et al. teach the first patterned circuit layer is formed from a metal foil. See fig. 3D and 3F and associated text.
Double Patenting
A rejection based on double patenting of the “same invention” type finds its support in the language of 35 U.S.C. 101 which states that “whoever invents or discovers any new and useful process... may obtain a patent therefor...” (Emphasis added). Thus, the term “same invention,” in this context, means an invention drawn to identical subject matter. See Miller v. Eagle Mfg. Co., 151 U.S. 186 (1894); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Ockert, 245 F.2d 467, 114 USPQ 330 (CCPA 1957).
A statutory type (35 U.S.C. 101) double patenting rejection can be overcome by canceling or amending the claims that are directed to the same invention so they are no longer coextensive in scope. The filing of a terminal disclaimer cannot overcome a double patenting rejection based upon 35 U.S.C. 101.
Claims 1-11 is/are rejected under 35 U.S.C. 101 as claiming the same invention as that of claims 1-11 of prior U.S. Patent No. 18071797. This is a statutory double patenting rejection.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having a first component over a first substrate including a first patterned conductor and a first through hole and the first component is connected to the first patterned connector and a second component over a second substrate including a second patterned conductor and a second through hole and the second component is connected to the second patterned connector as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897