DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 2 in the reply filed on 1/20/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-8 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ecton et al (US 2024/0176070).
1. A structure comprising:
a package substrate (Fig. 2A (131) and [0082]);
a first photonics chip (Fig. 2A (104-1) and [0085- PIC]) on the package substrate (Fig. 2A (131) and [0082]), the first photonics chip including an optical coupler (Fig.2A (160-1/106-3) and [0085]) and a bond pad (Fig.1A/2A (122) and [0079]); and
an electro-optic bridge chip (Fig.2A/3D (128/103) and [0085]) on the package substrate (Fig. 2A (131) and [0082]), the electro-optic bridge chip (Fig.2A (128/103) and [0085]) including a waveguide core (Fig.2A/3D (103/160) and [0085]) and an electrical trace line (Fig.2A/3D (148-2) and [0085]), the electrical trace line (Fig.2A/3D (148-2) and [0085]) coupled to the bond pad (Fig.1A/2A/3D (122) and [0079]) of the first photonics chip (Fig. 2A (104-1) and [0085- PIC]), and the waveguide core (Fig.2A/3D (103/160) and [0085]) including a first portion that is coupled to the optical coupler (Fig.2A/3E (182-1) and [0085]) of the first photonics chip (Fig. 2A (104-1) and [0085- PIC]).
4. The structure of claim 1 wherein the electro-optic bridge chip (Fig.2A/3D (128/103) and [0085]) includes a dielectric layer (Fig.2A/3D (148-2/ 148-1- includes dielectric layers) and [0085]), and the waveguide core (Fig.2A/3D (103/160) and [0085]) is disposed in the dielectric layer (Fig.2A/3D (148-2/ 148-1- includes dielectric layers which 103 is disposed in between) and [0085]).
5. The structure of claim 4 wherein the package substrate (Fig. 2A (131) and [0082]) has a top surface (top), and the waveguide core (Fig.2A/3D (103/160) and [0085]) is disposed in the dielectric layer (Fig.2A/3D (148-2/ 148-1- includes dielectric layers) above the top surface of the package substrate (Fig. 2A (131) and [0082]).
6. The structure of claim 4 wherein the package substrate (Fig. 2A (131) and [0082]) has a top surface, and the dielectric layer (Fig.2A/3D (148-2/ 148-1- includes dielectric layers) has a top surface that is disposed above the top surface of the package substrate (Fig. 2A (131) and [0082]).
7. The structure of claim 4 wherein the package substrate (Fig. 2A (131) and [0082]) has a top surface, and the dielectric layer (Fig.2A/3D (148-1- includes dielectric layers) is disposed on the top surface of the package substrate (Fig. 2A (131) and [0082]).
8. The structure of claim 4 wherein the dielectric layer (Fig.2A/3D (148-2/ 148-1- includes dielectric layers) has a top surface, and the waveguide core (Fig.2A/3D (103/160) and [0085]) is disposed adjacent to the top surface of the dielectric layer (Fig.2A/3D (148-2/ 148-1- includes dielectric layers).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Ecton et al (US 20240178207); Li (US 20240176068, US 20240176069); Pietambaram et al (US 10892219) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LAURA M MENZ/Primary Examiner, Art Unit 2813
3/30/26
Prosecution Insights