DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, as presented in at least Fig. 6 & 23 of the instant application, in the reply filed on 6 February 2026 is acknowledged.
Claims 12 – 14 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 6 February 2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: THIN FILM TRANSISTOR WITH SYMMETRIC HOLES IN CHANNEL.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4, 6 – 9, & 17 – 18, as well as their respective dependent claims, are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 1,
Lin. 14 – 15 recite the limitation “a gate electrode in an electrode conductive layer on the gate insulating layer and overlapping the channel area of the active layer”. However, due to the grammatical structure of this limitation, the relationship between the elements listed is unclear, making the claim indefinite. For the purposes of examination, this limitation will be interpreted as “a gate electrode in an electrode conductive layer, on the gate insulating layer, and overlapping the channel area of the active layer”.
Regarding Claim 4,
Lin. 11 – 13 recite the limitation “one side of the second electrode adjacent to the second through hole…is symmetrical to the first electrode with respect to the gate electrode”. However, due to the grammatical structure of this limitation, the symmetric relationship between the elements listed is unclear, making the claim indefinite. For the purposes of examination, this limitation will be interpreted as “one side of the second electrode adjacent to the second through hole…is symmetrical to the one side of the first electrode adjacent to the first through hole with respect to the gate electrode”.
Regarding Claim 6,
Lin. 26 recites the limitation “groove part” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “groove part of the first electrode”.
Regarding Claim 7,
Lin. 3 – 4 recite the limitation “groove part” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “groove part of the first electrode”.
Regarding Claim 8,
Lin. 10 recites the limitation “the other side of the edge of the first through hole” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “an other side of the edge of the first through hole”.
Lin. 11 recites the limitation “both sides of the edge of the first through hole in the second direction” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “both sides of an edge of the first through hole in the second direction”.
Regarding Claim 9,
Lin. 15 – 16 recites the limitation “a width of the first through hole in the second direction” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “the width of the first through hole in the second direction”, due to the dependence of Claim 9 upon Claim 8.
Regarding Claim 17,
Lin. 26 – 28 recite the limitation “one side of the second electrode adjacent to the second through hole…is symmetrical to the first electrode with respect to the gate electrode”. However, due to the grammatical structure of this limitation, the symmetric relationship between the elements listed is unclear, making the claim indefinite. For the purposes of examination, this limitation will be interpreted as “one side of the second electrode adjacent to the second through hole…is symmetrical to the one side of the first electrode adjacent to the first through hole with respect to the gate electrode”.
Regarding Claim 18,
Lin. 14 – 15 recite the limitation “the other side of the edge of the first through hole” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “an other side of the edge of the first through hole”.
Lin. 15 recites the limitation “both sides of the edge of the first through hole in the second direction” without a proper antecedent basis. For the purposes of examination, this limitation will be interpreted as “both sides of an edge of the first through hole in the second direction”.
Examiner’s Note
Regarding at least Claim 21, it has been well established that the manner of operating a device does not differentiate a device claim from a prior art device. "[Device] claims cover what a device is, not what a device does." Hewlett-Packard Co. v. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990) (emphasis in original). A claim containing a "recitation with respect to the manner in which a claimed [device] is intended to be employed does not differentiate the claimed [device] from a prior art [device]" if the prior art device teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987), MPEP 2114 II. Hence, the functionality requirements in at least Claim 21 do not patentably distinguish applicant’s claimed device from the known device of LEE in view of JEONG.
Regarding Fig. 10A of LEE, refer to the following associated annotated figure.
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Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 6, 8 – 11, & 15 – 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by LEE (US 20250031410 A1).
Regarding Claim 1,
LEE discloses:
A thin film transistor (Fig. 10A/10B/10C: 1000) comprising:
a substrate (110);
an active layer (130) on the substrate (110) and
including a channel area (CHA),
a first conductive area (COA1) connected to one side (left side) of the channel area (CHA), and
a second conductive area (COA2) connected to an other side (right side) of the channel area (CHA);
a gate insulating layer (140) on a portion of the active layer (130);
a first through hole (PN1) penetrating through a portion of the first conductive area (COA1);
a second through hole (PN2) penetrating through a portion of the second conductive area (COA2);
a gate electrode (150)
in an electrode conductive layer (171/150/172),
on the gate insulating layer (140), and
overlapping the channel area (CHA) of the active layer (130);
a first electrode (171/175)
in the electrode conductive layer (171/150/172),
adjacent to one side (left side) of the first through hole (PN1), and
electrically connected to the first conductive area (COA1); and
a second electrode (172/176)
in the electrode conductive layer (171/150/172),
adjacent to one side (right side) of the second through hole (PN2), and
electrically connected to the second conductive area (COA2),
wherein
one side (right side of 175) of the first electrode (171/175) adjacent to the first through hole (PN1) is parallel to the one side (left side) of the first through hole (PN1),
the first electrode (171/175) comprising
protrusion parts (rightmost portions of 175) at both ends (Fig. 10A: top end and bottom end of 175) thereof and
a groove part (right portions of 175 between protrusion parts of 171/175, hereinafter denoted GP1) concavely recessed from the gate electrode (150) as compared with the protrusion parts (As seen in Fig. 10A).
Regarding Claim 2,LEE discloses: The thin film transistor of claim 1,
wherein the first conductive area (COA1) corresponds to a first electrode connection hole (CH1) penetrating through the gate insulating layer (140),
wherein the second conductive area (COA2) corresponds to a second electrode connection hole (CH2) penetrating through the gate insulating layer (140),
wherein the first electrode (171/175) extends to the first conductive area (COA1) and in contact with a first contact area (COA11) of the first conductive area (COA1), and
wherein the second electrode (172/176) extends to the second conductive area (COA2) and in contact with a second contact area (COA21) of the second conductive area (COA2).
Regarding Claim 3,LEE discloses: The thin film transistor of claim 2,
wherein a length (perimeter of COA12 where COA12 meets PN1, as seen in Fig. 10A) of a first pass area (COA12) between the one side (left side) of the first through hole (PN1) and the first contact area (COA11) in the first conductive area (COA1) is greater than a width (from top to bottom in Fig. 10A) of the one side (left side) of the first through hole (PN1).
Regarding Claim 4,LEE discloses: The thin film transistor of claim 3,
wherein one side (left side of 176) of the second electrode (172/176) adjacent to the second through hole (PN2)
is parallel to the one side (right side) of the second through hole (PN2),
is symmetrical to the one side (right side of 175) of the first electrode (171/175) adjacent to the first through hole (PN1) with respect to the gate electrode (150),
the second electrode (172/176) comprising
protrusion parts (leftmost portions of 176) and
a groove part (left portions of 176 between protrusion parts of 172/176), and
wherein a length (from left to right in Fig. 10A) of a second pass area (COA22) between the one side (right side) of the second through hole (PN2) and the second contact area (COA21) in the second conductive area (COA2) is greater than a width (from top to bottom in Fig. 10A) of the one side (right side) of the second through hole (PN2).
Regarding Claim 5,LEE discloses: The thin film transistor of claim 4,
wherein the first conductive area (COA1) includes
a first main area (COA13) between the channel area (CHA) and the first pass area (COA12), and
wherein the second conductive area (COA2) includes
a second main area (COA23) located between the channel area (CHA) and the second pass area (COA22).
Regarding Claim 6,LEE discloses: The thin film transistor of claim 5,
wherein in a first direction (from left to right in Fig. 10A, hereinafter denoted D1) in which the first electrode (171/175) and the gate electrode (150) face each other, a maximum width of the first contact area (COA11) is greater than a width of the groove part (GP1) of the first electrode (171/175).
Regarding Claim 8,LEE discloses: The thin film transistor of claim 6,
wherein in a second direction (top to bottom in Fig. 10A, hereinafter denoted D2) crossing the first direction (D1), a width (full-width) of the first conductive area (COA1) is greater than a width (full-width) of the first through hole (PN1), and
wherein one side (left side) of an edge (top edge of PN1 in Fig. 10A) of the first through hole (PN1) in the first direction (D1) is in contact with the first pass area (COA12), and
an other side (right side) of the edge (top edge of PN1 in Fig. 10A) of the first through hole (PN1) in the first direction (D1) and both sides (top side and bottom side) of an edge (right edge of PN1 in Fig. 10A) of the first through hole (PN1) in the second direction (D2) are in contact with the first main area (COA13).
Regarding Claim 9,LEE discloses: The thin film transistor of claim 8,
wherein a width (half-width) of the groove part (GP1) in the second direction (D2) is equal to or less than 1/2 of the width (full-width) of the first through hole (PN1) in the second direction (D2).
(As per Fig. 10A, the “full-width” of GP1 and PN1 in D2 are the same. As such, the “half-width” of GP1 in D2 is equal to 1/2 of the “full-width” of PN1 in D2.)
Regarding Claim 10,LEE discloses: The thin film transistor of claim 9,
wherein the width of the groove part (GP1) in the second direction (D2) is 1 µm or more.
(Par. 142: the diameter of PN1, and thus the width of the groove part in the second direction, may be more than 2 µm.)
Regarding Claim 11,LEE discloses: The thin film transistor of claim 8,
wherein the length (As indicated in Claim 3) of the first pass area (COA12) corresponds to the width (As indicated in Claim 8) of the first through hole (PN1) in the second direction (D2) and the width (As indicated in Claim 6) of the groove part (GP1) in the first direction (D1).
Regarding Claim 15,LEE discloses: The thin film transistor of claim 2,
wherein the active layer (130) further comprises:
a first non-active area (IAA1) connected to the first contact area (COA11) of the first conductive area (COA1) and covered with the gate insulating layer (140); and
a second non-active area (IAA2) connected to the second contact area (COA21) of the second conductive area (COA2) and covered with the gate insulating layer (140).
Regarding Claim 16,
LEE discloses:
A transistor array substrate (Fig. 17: 1600) comprising:
a substrate (110; Par. 275) including
a display area (Fig. 17: 310) in which sub-pixels (Fig. 17: P) are arranged; and
a circuit layer (Fig. 10A/10B/10C: 120/140/160 of 1000, where 1600 comprises 1000; Par. 275 – 276) on the substrate (110) and including
pixel drivers (Fig. 20: PDC, where each PDC includes a TR1, as seen in Fig. 20, and each TR1 may be the thin film transistor of Fig. 10A/10B/10C: 1000, as per Par. 310, which is included in 120/140/160),
each of the pixel drivers (PDC) corresponding to a sub-pixel (P) of the sub-pixels (As seen in Fig. 20),
wherein each of the pixel drivers (PDC) comprises at least one thin film transistor (Fig. 20: TR1),
wherein the thin film transistor (As presented in Fig. 10A/10B/10C) of the circuit layer (Fig. 10A/10B/10C: 120/140/160) comprises:
an active layer (130) on the substrate (110) and including
a channel area (CHA),
a first conductive area (COA1) connected to one side (left side) of the channel area (CHA), and
a second conductive area (COA2) connected to an other side (right side) of the channel area (CHA);
a gate insulating layer (140) on a portion of the active layer (130);
a first through hole (PN1) penetrating through a portion of the first conductive area (COA1);
a second through hole (PN2) penetrating through a portion of the second conductive area (COA2);
a gate electrode (150) in an electrode conductive layer (171/150/172) on the gate insulating layer (140) and overlapping the channel area (CHA) of the active layer (130);
a first electrode (171/175) in the electrode conductive layer (171/150/172), adjacent to one side (left side) of the first through hole (PN1), and electrically connected to the first conductive area (COA1); and
a second electrode (172/176) in the electrode conductive layer (171/150/172), adjacent to one side (right side) of the second through hole (PN2), and electrically connected to the second conductive area (COA2),
wherein one side (right side of 175) of the first electrode (171/175) adjacent to the first through hole (PN1) is parallel to the one side (left side) of the first through hole (PN1), the first electrode (171/175) comprising protrusion parts (rightmost portions of 175) at both ends (Fig. 10A: top end and bottom end of 175) thereof and a groove part (right portions of 175 between protrusion parts of 171/175, hereinafter denoted GP1) concavely recessed from the gate electrode (150) as compared with the protrusion parts (As seen in Fig. 10A).
Regarding Claim 17,LEE discloses: The transistor array substrate of claim 16,
wherein the first conductive area (COA1) corresponds to a first electrode connection hole (CH1) penetrating through the gate insulating layer (140),
wherein the second conductive area (COA2) corresponds to a second electrode connection hole (CH2) penetrating through the gate insulating layer (140),
wherein the first electrode (171/175) extends to the first conductive area (COA1) and contacts a first contact area (COA11) of the first conductive area (COA1),
wherein the second electrode (172/176) extends to the second conductive area (COA2) and contacts a second contact area (COA21) of the second conductive area (COA2),
wherein a length (perimeter of COA12 where COA12 meets PN1, as seen in Fig. 10A) of a first pass area (COA12) between the one side (left side) of the first through hole (PN1) and the first contact area (COA11) in the first conductive area (COA1) is greater than a width (from top to bottom in Fig. 10A) of the one side (left side) of the first through hole (PN1),
wherein one side (left side of 176) of the second electrode (172/176) adjacent to the second through hole (PN2)
is parallel to the one side (right side) of the second through hole (PN2),
is symmetrical to the one side (right side of 175) of the first electrode (171/175) adjacent to the first through hole (PN1) with respect to the gate electrode (150), and
comprises protrusion parts (leftmost portions of 176) and a groove part (left portions of 176 between protrusion parts of 172/176), and
wherein a length (from left to right in Fig. 10A) of a second pass area (COA22) between the one side (right side) of the second through hole (PN2) and the second contact area (COA21) in the second conductive area (COA2) is greater than a width (from top to bottom in Fig. 10A) of the one side (right side) of the second through hole (PN2).
Regarding Claim 18,LEE discloses: The transistor array substrate of claim 17,
wherein the first conductive area (COA1) includes a first main area (COA13) between the channel area (CHA) and the first pass area (COA12),
wherein in a first direction (from left to right in Fig. 10A, hereinafter denoted D1) in which the first electrode (171/175) and the gate electrode (150) face each other, a maximum width of the first contact area (COA11) is greater than a width of the groove part (GP1),
wherein in a second direction (top to bottom in Fig. 10A, hereinafter denoted D2) crossing the first direction (D1), a width (full-width) of the first conductive area (COA1) is greater than a width (full-width) of the first through hole (PN1), and
wherein one side (left side) of an edge (top edge of PN1 in Fig. 10A) of the first through hole (PN1) in the first direction (D1) is in contact with the first pass area (COA12), and an other side (right side) of the edge (top edge of PN1 in Fig. 10A) of the first through hole (PN1) in the first direction (D1) and both sides (top side and bottom side) of an edge (right edge of PN1 in Fig. 10A) of the first through hole (PN1) in the second direction (D2) are in contact with the first main area (COA13).
Regarding Claim 19,LEE discloses: The transistor array substrate of claim 18,
wherein the length (As indicated in Claim 17) of the first pass area (COA12) corresponds to the width (As indicated in Claim 18) of the first through hole (PN1) in the second direction (D2) and the width (As indicated in Claim 18) of the groove part (GP1) in the first direction (D1).
Regarding Claim 20,LEE discloses: The transistor array substrate of claim 17,
wherein the active layer (130) further includes:
a first non-active area (IAA1) connected to the first contact area (COA11) of the first conductive area (COA1) and covered with the gate insulating layer (140); and
a second non-active area (IAA2) connected to the second contact area (COA21) of the second conductive area (COA2) and covered with the gate insulating layer (140).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over LEE.
Regarding Claim 7,LEE does not disclose: The thin film transistor of claim 6,
wherein in the first direction (D1), a difference between the maximum width of the first contact area (COA11) and the width of the groove part (GP1) of the first electrode (171/175) is 0.5 µm or more.
Regardless, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to enable a difference between the maximum width of the first contact area in the first direction and the width of the groove part of the first electrode in the first direction to be 0.5 µm or more in LEE, as one would have chosen the size and/or location of the associated first through hole—both of which dictate said difference—according to a result effective variable, allowing for the routine optimization of “an arrangement efficiency of the light shielding layer” to which the gate electrode is connected (LEE Par. 9) as well as the routine optimization of the diameter of the first through hole (LEE Par. 142 – 144), MPEP 2144.05 II A.
Claims 21 & 22 are rejected under 35 U.S.C. 103 as being unpatentable over LEE in view of JEONG (US 20250048739 A1).
Regarding Claim 21,LEE discloses for the embodiment of Claim 17:The transistor array substrate of claim 17, further comprising…
scan gate lines (Fig. 20: GL) to transfer scan signals (Fig. 20: SS) to the pixel drivers (Fig. 20: PDC); and
data lines (Fig. 20: DL) to transfer data signals (Fig. 20: Vdata) to the pixel drivers (Fig. 20: PDC);
(Fig. 17 shows a singular pixel P, however a plurality of pixels is disclosed, Par. 278. As such, a plurality of the components each pixel P comprises is disclosed implicitly. I.e. the plurality of the scan gate lines, transfer scan signals, pixel drivers, data lines, and transfer data signals.)
wherein a pixel driver (Fig. 20: PDC) from among the pixel drivers (one PDC for each of the plurality of sub-pixels P) comprises:
a first thin film transistor (Fig. 20: TR1) connected to a light emitting element (Fig. 20: 710) from among the light emitting elements (one 710 for each of the plurality of sub-pixels P) connected in series between a first power line (Fig. 20: PL) and a second power line (Fig. 20: low side line of 710), the first and second power lines to transfer a first power (Fig. 20: Vdd multiplied by the current passing through PL) and a second power (Fig. 20: low side power of 710) for driving the light emitting elements (As seen in Fig. 20);
a second thin film transistor (Fig. 20: TR2) electrically connected between the data line (Fig. 20: DL) and a gate electrode (As seen in Fig. 20) of the first thin film transistor (TR1) and is configured to turn on based on a scan signal (Fig. 20: SS) of the scan gate line (Fig. 20: GL);
a pixel capacitor (Fig. 20: C1) electrically connected to a first node between the gate electrode of the first thin film transistor (TR1) and the second thin film transistor (TR2) and a second node between the first thin film transistor (TR1) and the light emitting element (710);
LEE does not disclose for the embodiment of Claim 17: The transistor array substrate of claim 17, further comprising
a light emitting element layer on a via layer of the circuit layer,
wherein the light emitting element layer comprises light emitting elements electrically connected to respective pixel drivers through anode contact holes penetrating through the via layer and an interlayer insulating layer,
wherein the circuit layer further comprises:
scan gate lines to transfer scan signals to the pixel drivers;
data lines to transfer data signals to the pixel drivers; and
initialization voltage lines to transfer initialization voltages to the pixel drivers, and
wherein a pixel driver from among the pixel drivers comprises:
a third thin film transistor electrically connected between the initialization voltage line the second node and is configured to turn on based on an initialization control signal of an initialization gate line.
LEE, however, discloses for another embodiment:
scan gate lines (Fig. 21: GL) to transfer scan signals (Fig. 21: SS) to the pixel drivers (Fig. 21: PDC); and
data lines (Fig. 21: DL) to transfer data signals (Fig. 21: Vdata) to the pixel drivers (Fig. 21: PDC); and
initialization voltage lines (Fig. 21: RL) to transfer initialization voltages (Fig. 21: Vref) to the pixel drivers (Fig. 21: PDC)
(Fig. 17 shows a transistor array substrate 1600 analogous to transistor array substrate 1700, which is the same embodiment as Fig. 21. As one of ordinary skill in the art would consider 1700 to have the same structure as 1600 up to the details of the circuit diagrams provided for the separate embodiments—Fig. 20 and Fig. 21, respectively—one of ordinary skill in the art would understand a plurality of pixels is also implicitly provided for this alternate embodiment. Thus, a plurality of the components each pixel P comprises is also implicitly disclosed. I.e. the plurality of the scan gate lines, transfer scan signals, pixel drivers, data lines, transfer data signals, initialization voltage lines, and transfer initialization voltages.)
wherein a pixel driver (Fig. 21: PDC) from among the pixel drivers (one PDC for each of the plurality of sub-pixels P for transistor array substrate 1700 analogous to transistor array substrate 1600 of the embodiment of Claim 17) comprises:
a first thin film transistor (Fig. 21: TR1) connected to a light emitting element (Fig. 21: 710) from among the light emitting elements (one 710 for each of the plurality of sub-pixels P) connected in series between a first power line (Fig. 21: PL) and a second power line (Fig. 21: low side line of 710), the first and second power lines to transfer a first power (Fig. 21: Vdd multiplied by the current passing through PL) and a second power (Fig. 21: low side power of 710) for driving the light emitting elements (As seen in Fig. 21);
a second thin film transistor (Fig. 21: TR2) electrically connected between the data line (Fig. 21: DL) and a gate electrode (As seen in Fig. 21) of the first thin film transistor (TR1) and is configured to turn on based on a scan signal (Fig. 21: SS) of the scan gate line (Fig. 21: GL);
a pixel capacitor (Fig. 21: C1) electrically connected to a first node (Fig. 21: n2) between the gate electrode of the first thin film transistor (TR1) and the second thin film transistor (TR2) and a second node (Fig. 21: n1) between the first thin film transistor (TR1) and the light emitting element (710); and
a third thin film transistor (Fig. 21: TR3) electrically connected between an initialization voltage line (Fig. 21: RL) and the second node (n1) and is configured to turn on based on an initialization control signal (Fig. 21: SCS) of an initialization gate line (Fig. 21: SCL).
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the embodiment of Claim 17 of LEE with the another embodiment of LEE to enable the transistor array substrate of claim 17 to further comprise initialization voltage lines to transfer initialization voltages to the pixel drivers, and the pixel driver from among the pixel drivers to comprise…a third thin film transistor electrically connected between an initialization voltage line and the second node and is configured to turn on based on an initialization control signal of an initialization gate line according to the teachings of LEE, as these inventions are closely related and obviously juxtaposed in the same disclosure for the skilled artisan to compare and consider.
LEE does not disclose for either embodiment:
a light emitting element layer on a via layer of the circuit layer,
wherein the light emitting element layer comprises light emitting elements electrically connected to respective pixel drivers through anode contact holes penetrating through the via layer and an interlayer insulating layer,
wherein the circuit layer further comprises:
scan gate lines to transfer scan signals to the pixel drivers;
data lines to transfer data signals to the pixel drivers; and
initialization voltage lines to transfer initialization voltages to the pixel drivers
JEONG discloses:
a light emitting element layer (Fig. 17: 750/710) on a via layer (Fig. 17: upper portion of 190) of the circuit layer (Fig. 17: 120/140/180/190),
wherein the light emitting element layer (750/710) comprises light emitting elements (710) electrically connected to respective pixel drivers (Fig. 15: PDC, which is a circuit diagram of a given sub-pixel P in transistor array substrate 1000 of Fig. 13, and Fig. 17 is a cross-section of one such sub-pixel P. That is, Fig. 13, 15, & 17 are of the same embodiment, as per Par. 32 – 36) through anode contact holes (Fig. 17: H9) penetrating through the via layer (Fig. 17: upper portion of 190) and an interlayer insulating layer (Fig. 17: lower portion of 190),
(Fig. 17: 711 of 710 is electrically connected to TR2, which is a component of its respective pixel driver, PDC of Fig. 15.)
(Fig. 13 shows a singular pixel P, however a plurality of pixels is disclosed, Par. 145. As such, a plurality of the components each pixel P comprises is disclosed implicitly. I.e. the plurality of the light emitting elements, respective pixel drivers, and anode contact holes.)
scan gate lines (Fig. 15: GL) to transfer scan signals (Fig. 15: SS) to the pixel drivers (Fig. 15 PDC);
data lines (Fig. 15: DL) to transfer data signals (Fig. 15: Vdata) to the pixel drivers (Fig. 15: PDC);
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LEE with those of JEONG to enable a light emitting element layer on a via layer of the circuit layer, wherein the light emitting element layer comprises light emitting elements electrically connected to respective pixel drivers through anode contact holes penetrating through the via layer and an interlayer insulating layer in LEE according to the teachings of JEONG, as LEE discloses thin film transistors and pixel drivers designed for implementation in an OLED display (LEE Par. 308) but fails to disclose certain details necessary for an operational display (i.e. the disposition of a light emitting layer relative to the other layers present, electrical connections pertaining thereto, etc). Therefore, a person having ordinary skill in the art would look to the prior art for an analogous invention providing said details and recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the invention of JEONG meets these criteria, as both LEE and JEONG disclose thin film transistors and pixel drivers designed for implementation in an OLED display (LEE Par. 308; JEONG Par. 183).
Neither LEE nor JEONG disclose:
wherein the circuit layer further comprises:
scan gate lines; data lines; and initialization voltage lines
As described, LEE in view of JEONG discloses all of the elements above. However, LEE in view of JEONG does not disclose in which layer these elements are comprised where this claim requires said elements be comprised in the circuit layer.
Regardless, one of ordinary skill in the art would have recognized the finite number of disclosed layers in which said elements could be comprised—i.e. the substrate, the circuit layer, or the light emitting element layer. As such, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try all three disclosed layers to determine which is suitable for comprising said elements.
Regarding Claim 22,LEE discloses: The transistor array substrate of claim 17,
wherein the circuit layer (120/140/160) further comprises:
a light blocking electrode (portion of 111 in contact with BR1 and BR2) in a light blocking conductive layer (111) on the substrate (110) and overlapping the active layer (130);
a buffer layer (120) on the substrate (110) and covering the light blocking conductive layer (111);
an interlayer insulating layer (160) on the buffer layer (120) and covering the thin film transistor (As seen in Fig. 10B); and
the interlayer insulating layer (160) is in contact with the buffer layer (120) through each of the first through hole (PN1) and the second through hole (PN2).
LEE does not disclose:
a via layer on the interlayer insulating layer
JEONG discloses:
a via layer (Fig. 17: upper portion of 190) on the interlayer insulating layer (Fig. 17: lower portion of 190)
Further, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of LEE with those of JEONG to enable a via layer on the interlayer insulating layer in LEE according to the teachings of JEONG, as LEE discloses thin film transistors and pixel drivers designed for implementation in an OLED display (LEE Par. 308) but fails to disclose certain details necessary for an operational display (i.e. the disposition of a light emitting layer relative to the thin film transistor, electrical connections therebetween, a via layer through which the electrical connections may pass, etc). Therefore, a person having ordinary skill in the art would look to the prior art for an analogous invention providing said details and recognized for its suitability and intended purpose (MPEP 2144.07). Further still, the invention of JEONG meets these criteria, as both LEE and JEONG disclose thin film transistors and pixel drivers designed for implementation in an OLED display (LEE Par. 308; JEONG Par. 183).
Allowable Subject Matter
Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and said base claim and intervening claims were rewritten or amended to overcome the rejections under 35 U.S.C. 112(b) set forth in this Office Action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 23,
The closest prior art of record is LEE in view of JEONG. However, while LEE discloses a connection from the gate electrode to a respective portion of the light blocking conductive layer (Claim 22), LEE fails to disclose a connection from the first electrode and/or the second electrode to respective portions of the light blocking conductive layer. Further, while JEONG discloses a connection from the first electrode to a respective portion of the light blocking conductive layer (e.g. JEONG Fig. 10), and other related prior art discloses such connections from the first electrode and the second electrode to respective portions of the light blocking conductive layer (e.g. KIM Fig. 4A, see prior art of record), no proper motivation to combine such references with LEE is found such that the limitations of Claim 23 are satisfied.
Specifically, as the device of LEE requires a connection from the gate electrode to a respective portion of the light blocking conductive layer, and this requirement is pivotal in satisfying many of the limitations of the claims upon which Claim 23 depends—e.g. the presence and disposition of the first and second through holes in Claim 16—combining LEE with other prior art resulting in the gate electrode being connected elsewhere does not appear to satisfy many of the limitations upon which Claim 23 depends, particularly the limitations of the associated independent claim, Claim 16. Therefore, as the prior art does not appear provide example or motivation to form connections from all three electrodes to respective portions of the light blocking conductive layer—or any other means to satisfy the limitations of Claim 23—Claim 23 appears to comprise allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. KIM (US 20220173198 A1), which is used as a non-limiting example for illustrative purposes in the reasons for the indication of allowable subject matter in Claim 23.
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/K.S.S./Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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