DETAILED ACTION
This correspondence is in response to the communications received 02/27/2026. Claims 2, 3, and 13 have been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1, 4-12, and 14-20 in the reply filed on 02/27/2026 is acknowledged.
Claims 2, 3, and 13 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 02/27/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/14/2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a display device (10) comprising:
a substrate (SUB) including a display area (DA) and a peripheral area (PA) adjacent to the display area (see Fig. 1);
a power line (PL) in the peripheral area on the substrate (see Figs. 1 and 3);
a plurality of power connection lines (PCL) in the peripheral area on the substrate (see Figs. 1 and 3), extending in one direction (D1, see Fig. 3), and connected to the power line (see Fig. 3); and
a plurality of data lines (DL) in the peripheral area on the substrate (see Figs. 1 and 3), extending in the one direction (see Fig. 3), on a different layer from the power connection lines (see Fig. 6), and spaced apart from the power connection lines in a plan view (see Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210026423 A1, published 01/28/2021) in view of Kim et al. (US 20200202784 A1, published 06/25/2020, hereinafter ‘784).
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Regarding claim 1, Figs. 1-6 of Choi disclose a display device (“display apparatus 10”, [0055]) comprising:
a substrate (“substrate 100”, [0056]) including a display area and a peripheral area (“substrate 100 may have a display area DA and a peripheral area PA”, [0056]) adjacent to the display area (as seen in Fig. 2, DA is adjacent to PA);
a power line (“driving power supply line 30”, [0066]) in the peripheral area on the substrate (as seen in Fig. 2, 30 is in PA);
a plurality of power connection lines (“driving voltage line PL”, [0066], as seen in Fig. 2, PL connects 30 to “Pixels PX”, [0061], and is therefore a power connection line) in the peripheral area on the substrate (Choi does not explicitly show PL in PA on 100, however a secondary reference will be used to teach this limitation below), extending in one direction (as seen in Fig. 2, PL extend in “first direction DI1”, [0058]), and connected to the power line (as previously mentioned, PL is connected to 30); and
a plurality of data lines (“data lines DL”, [0064]) in the peripheral area on the substrate (Choi does not explicitly show DL in PA on 100, however a secondary reference will be used to teach this limitation below), extending in the one direction (as seen in Fig. 2, PL extend in DI1), on a different layer from the power connection lines (as seen in Fig. 5, DL are on a different layer from PL), and spaced apart from the power connection lines in a plan view (as seen in Fig. 2, DL are spaced apart from PL in a plan view).
Choi fails to disclose “a plurality of power connection lines in the peripheral area on the substrate; and
a plurality of data lines in the peripheral area on the substrate”.
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However, in a similar field of endeavor, Figs. 1-4 and 6-10 of ‘784 teach a plurality of power connection lines (“driving voltage lines PL1”, [0056], where PL1 of ‘784 are equivalent to PL of Choi) in the peripheral area on the substrate (as seen in Fig. 8, PL1 are in “non-display area NDA”, [0051], which as seen in Fig. 1, is on “substrate 100”, [0049], where NDA and 100 of ‘784 are equivalent to PA and 100 of Choi); and
a plurality of data lines (“data line DL”, [0051], where DL of ‘784 are equivalent to DL of Choi) in the peripheral area on the substrate (as seen in Fig. 8, DL are in “non- NDA, and as previously discussed, NDA is on 100).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a plurality of power connection lines in the peripheral area on the substrate; and
a plurality of data lines in the peripheral area on the substrate” as taught by ‘784 in the system of Choi for the purpose of providing power and data line connections between the display area and the peripheral area.
Regarding claim 9, Figs. 1-6 of Choi in combination with Figs. 1-4 and 6-10 of ‘784 disclose the display device of claim 1, Figs. 1-4 and 6-10 of ‘784 further disclose wherein the data lines include first data lines and second data lines (as seen in Fig. 8, from left to right, the first, third, fifth, and seventh instances of DL are first data lines, and from left to right, the second, fourth, and fifth instances of DL are second data lines), and
a first data signal applied to the first data lines is different from a second data signal applied to the second data lines (one having ordinary skill in the art would understand that adjacent pixels in a display device can show different colors, thus the corresponding data lines will have different signals applied).
Regarding claim 10, Figs. 1-6 of Choi in combination with Figs. 1-4 and 6-10 of ‘784 disclose the display device of claim 9, Figs. 1-4 and 6-10 of ‘784 further disclose
wherein each of the power connection lines is between a first data line and a second data line adjacent to each other in the plan view (as seen in Figs. 1 and 8, each of PL1 is between a first data line a second data line adjacent to each other in the plan view, while Fig. 8 shows the rightmost instance of PL1 as only neighboring a first data line, Fig. 1 shows that DA1 is between two instances of DA2, thus the rightmost instance of PL1 is also between a first data line and a second data line).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210026423 A1, published 01/28/2021) in view of Kim et al. (US 20200202784 A1, published 06/25/2020, hereinafter ‘784) in view of Sung et al. (US 11,294,515 B2, published 04/05/2022) in view of Kim (US 20190279575 A1, published 09/12/2019, hereinafter ‘575).
Regarding claim 4, Figs. 1-6 of Choi in combination with Figs. 1-4 and 6-10 of ‘784 disclose the display device of claim 1, Figs. 1-6 of Choi further disclose further comprising:
a via insulating layer (“sixth insulating layer 116”, [0128], Choi does not specify 116 is a via insulating layer, however a secondary reference will be used to teach this limitation below).
Choi in combination with ‘784 fails to disclose “a via insulating layer on the data lines,
wherein the power connection lines are on the via insulating layer”.
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However, in a similar field of endeavor, Figs. 1-5B of Sung teach a via insulating layer (as seen in Fig. 4, “anode electrode AE”, col. 6, lines 22-23, extends vertically through “via layer VIA”, col. 5, line 46, thus 116 of Choi is a via insulating layer as “second connection electrode 177”, [0129], extends vertically through 116, where AE and VIA of Sung are equivalent to 177 and 116 of Choi).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a via insulating layer” as taught by Sung in the system of Choi in combination with ‘784 for the purpose of preventing electrical shortages caused by electrodes extending in the vertical direction.
Choi in combination with ‘784 and Sung fails to disclose “a via insulating layer on the data lines,
wherein the power connection lines are on the via insulating layer”.
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However, in a similar field of endeavor, Figs. 1-5 of ‘575 teach a via insulating layer on the data lines (as seen in Fig. 4, “first organic insulating layer 111”, [0096], is on “data line DL”, [0045], where 111 and DL of ‘575 are equivalent to 116 and DL of Choi respectively)
wherein the power connection lines are on the via insulating layer (as seen in Fig. 4, “driving voltage line PL”, [0049], is on 111, where PL of ‘575 is equivalent to PL of Choi”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a via insulating layer on the data lines,
wherein the power connection lines are on the via insulating layer” as taught by ‘575 in the system of Choi in combination with ‘784 and Sung for the purpose of mitigating parasitic effects between signal and voltage lines.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20210026423 A1, published 01/28/2021) in view of Kim et al. (US 20200202784 A1, published 06/25/2020, hereinafter ‘784) in view of Sung et al. (US 11,294,515 B2, published 04/05/2022).
Regarding claim 5, Figs. 1-6 of Choi in combination with Figs. 1-4 and 6-10 of ‘784 disclose the display device of claim 1, Figs. 1-6 of Choi further disclose further comprising:
a via insulating layer (“sixth insulating layer 116”, [0128], Choi does not specify 116 is a via insulating layer, however a secondary reference will be used to teach this limitation below) on the power connection lines (as seen in Fig. 5, 116 is on PL),
wherein the data lines are on the via insulating layer (as seen in Fig. 5, DL is on PL).
Choi in combination with ‘784 does not specify “a via insulating layer”.
However, in a similar field of endeavor, Figs. 1-5B of Sung teach a via insulating layer (as seen in Fig. 4, “anode electrode AE”, col. 6, lines 22-23, extends vertically through “via layer VIA”, col. 5, line 46, thus 116 of Choi is a via insulating layer as “second connection electrode 177”, [0129], extends vertically through 116, where AE and VIA of Sung are equivalent to 177 and 116 of Choi respectively).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a via insulating layer” as taught by Sung in the system of Choi in combination with ‘784 for the purpose of preventing electrical shortages caused by electrodes extending in the vertical direction.
Allowable Subject Matter
Claims 6-8 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the display device as recited in the claims of the instant application.
Regarding claim 6, the prior art of Choi et al. (US 20210026423 A1) in combination with Kim et al. (US 20200202784 A1) discloses a similar display device but fails to disclose the specific claims of the instant application regarding the first power connection line and the second connection line, e.g. “wherein each of the power connection lines includes a first power connection line and a second power connection line, and
the first power connection line and the second power connection line are on different layers.”
Claims 7 and 8 are allowable by virtue of their dependence on claim 6.
Regarding claim 11, the prior art of Choi et al. (US 20210026423 A1) in combination with Kim et al. (US 20200202784 A1) discloses a similar display device but fails to disclose the specific claims of the instant application regarding the relative numbers of the power connection lines and the data lines, e.g. “wherein a number of the power connection lines is less than a number of the data lines.”
Claims 12 and 14-20 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the display device as recited in the claims of the instant application.
Regarding claim 12, the prior art of Choi et al. (US 20210026423 A1) in combination with Kim et al. (US 20200202784 A1), Li et al. (US 11,816,283 B2), and Yeke Yazdandoost et al. (US 10,838,556 B2) discloses a similar display device but fails to disclose the specific claims of the instant application regarding the demultiplexers, the pad area, and the location and positioning of the power line, the data line, the plurality of power connection lines, and the plurality of data connection lines, e.g. “a plurality of demultiplexers in the pad area on the substrate;
a power line in the pad area on the substrate;
a plurality of data connection lines in the pad area on the substrate, extending in one direction, and connected to the demultiplexers;
a plurality of power connection lines in the bending area on the substrate, extending in the one direction, and connected to the power line; and
a plurality of data lines in the bending area on the substrate, extending in the one direction, on a different layer from the power connection lines, connected to the data connection lines, and spaced apart from the power connection lines in a plan view.”
Claims 14-20 are allowable by virtue of their dependence on claim 12.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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