DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR
1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/28/2026 has been entered.
Response to Amendment
The Amendment filed on 05/28/2026 has been entered. Double patenting rejection of claims 2,
7-12 is withdrawn. The double patenting rejection of claim 1 is maintained because the amendment limitation is inherently disclosed by claims 7, 11 and 12 and limitations of claims 3-6 are disclosed by claims 1,4,5 and 7 from U.S. Patent No. US 12482768 B2, See Double Patenting rejection, below.
Response to Arguments
Applicant's arguments "Applicant Arguments/Remarks Made in an Amendment" with the
"Amendment/Req. Reconsideration-After Final Reject" filed on 05/28/2026, have been fully considered. Applicant’s amendment related to “wherein the width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer; wherein the width of the first portion of the protective layer is greater than a width of the core; wherein a sidewall of the core and the dielectric layer are separated by the second portion of the protective layer; wherein the width of the core is greater than or equal to the width of the seed layer”, does not overcome the new ground of rejections with some reference of the record, US 20090102032 A1 to Schneegans and US 20140061920 A1 to Hirano. Regarding the applicant’s amendment, Schneegans discloses a conductive member 50-52-26-28, a protective layer 28 having sides and bottom surfaces, a seed layer 52, as showed in Fig. 1, but does not disclose a dielectric layer over the substrate and surrounding the conductive member and wherein a side surface and a bottom surface of the second portion of the protective layer are in contact with the dielectric layer, such that the seed layer is not in contact with the bottom surface of the second portion of the protective layer. However, Hirano discloses a dielectric layer 9 over the substrate 20, surrounding the conductive member 30 and a seed layer 5 having a width less than a width of a core layer 6 and wherein a width of the capping layer is substantially greater than a width of the seed layer, as showed in Fig. 1.
The combination of Schneegans and Hirano results in “wherein the width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer; wherein the width of the first portion of the protective layer is greater than a width of the core; wherein a sidewall of the core and the dielectric layer are separated by the second portion of the protective layer; wherein the width of the core is greater than or equal to the width of the seed layer”, being used in the current rejection, see detail below.
The Applicant’s amendment related to “a conductive bump disposed on and electrically connected to the first conductive member, wherein the second conductive member is a conductive bump free member”, have been fully considered, however the Applicant’s amendment does not overcome the new ground of rejections with new reference, US 20200168543 A1 to Shih see detail below.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded
in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp.
Claims 1 and 3-6 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over (reference patent(s)):
Claims 1, 4-7 and 10-12 of U.S. Patent No. US 12482768 B2.
Although the claims at issue are not identical, they are not patentably distinct from each other as shown in the table below.
Instant Application
U.S. Patent No. US 12482768 B2
1. A semiconductor structure, comprising: a substrate; a conductive member disposed over the substrate, wherein the conductive member comprises a seed layer disposed over the substrate, a core disposed over the seed layer, and a protective layer having a first portion disposed on a top surface of the core and a second portion surrounding a sidewall of the core; a dielectric layer over the substrate and surrounding the conductive member; and a capping layer disposed over the protective layer and the core; wherein a width of the capping layer is substantially greater than a width of the seed layer; wherein a side surface and a bottom surface of the second portion of the protective layer are in contact with the dielectric layer, such that the seed layer is not in contact with the bottom surface of the second portion of the protective layer.
wherein the width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer;
wherein the width of the first portion of the protective layer is greater than a width of the core;
wherein a sidewall of the core and the dielectric layer are separated by the second portion of the protective layer; wherein the width of the core is greater than or equal to the width of the seed layer.
1. A semiconductor structure, comprising: a substrate; and a conductive member disposed over the substrate, wherein the conductive member includes a seed layer disposed over the substrate, a core disposed over the seed layer, and a protective layer disposed on a top surface of the core and surrounding a sidewall of the core; wherein the protective layer has a first portion disposed over the core and a second portion surrounding the core; wherein a thickness of the first portion of the protective layer is equal to a thickness of the second portion of the protective layer, wherein a width of the core is greater than a width of the seed layer, such that the seed layer is contactless with the protective layer.
6. The semiconductor structure of Claim 1, further comprising a capping layer disposed over the protective layer and the core; wherein the capping layer includes gold.
10. The semiconductor structure of Claim 6, wherein a width of the capping layer is substantially greater than a width of the seed layer.
11. The semiconductor structure of Claim 1, further comprising: a dielectric layer over the substrate and surrounding the conductive member, wherein a sidewall and a bottom wall of the second portion of the protective layer are in contact with the dielectric layer.
The amendment limitation is inherently disclosed by claims 7, 11 and 12:
Claim 7 “wherein a width of the capping layer is equal to a width of the first portion of the protective layer…”
Claim 11” a dielectric layer over the substrate and surrounding the conductive member…”
Claim 12” wherein the first protective layer has a first portion disposed over the first core and a second portion surrounding the first core”
Claim(s) 3
Claim(s) 1
Claim(s) 4
Claim(s) 4
Claim(s) 5
Claim(s) 1 and 5
Claim(s) 6
Claim(s) 7 and new matter
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claim Objections
Claim 6 is objected to because of the following informalities: “…the first portion of the protective
layer is disposed between and in contact between…”. It should be read “…the first portion of the protective layer is disposed between and in contact with…”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
Claim 6 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The specification as filed, fails to adequately describe the limitation “such that the first portion of the protective layer and the capping layer are separated by the second portion of the protective layer”. Drawings 1 and 3 is shown the first portion of the protective layer 114a below the capping layer 115 and the second portion of the protective layer 114b below 114a but it is not showed “the first portion of the protective layer and the capping layer are separated by the second portion of the protective layer”.
Claim 6 includes a new matter, figs. 1-21, none of the figures shows "the first portion of the protective layer and the capping layer are separated by the second portion of the protective layer”. For examination propose of claim 6, this limitation will not be examined.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Schneegans et al. (US 20090102032 A1, hereinafter Schneegans, of the record), in view of Hirano et al. (US 20140061920 A1, hereinafter Hirano, of the record).
Re: Independent Claim 1, Schneegans discloses a semiconductor structure (20 an electronic device in [0020], Fig. 1), comprising:
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Schneegans’s Figure 1-Annotated.
a substrate (22 a semiconductor wafer substrate in [0022], Fig. 1);
a conductive member (50,52,26,28 a conductive member including 50,52,26,28 in [0005, 0022], Fig. 1) disposed over the substrate (22), wherein the conductive member (50,52,26,28) comprises a seed layer (52 a seed layer in [0023], Fig. 1) disposed over the substrate (22), a core (26 a conducting line including a metal such as copper in [0025], Fig. 1) disposed over the seed layer (52), and a protective layer (28 a second layer including a conducting material such as nickel in [0027, 0028], Fig. 1) having a first portion (28-top Fig. 1-Annotated) disposed on a top surface (Fig. 1) of the core (26) and a second portion (28-side Fig. 1-Annotated) surrounding a sidewall (Fig. 1) of the core (26).
Schneegans does not expressly disclose a dielectric layer over the substrate and surrounding the conductive member; and a capping layer disposed on the first portion of the protective layer and the core; wherein a width of the capping layer is substantially greater than a width of the seed layer, wherein a side surface and a bottom surface of the second portion of the protective layer are in contact with the dielectric layer, such that the seed layer is not in contact with the bottom surface of the second portion of the protective layer; wherein the width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer; wherein the width of the first portion of the protective layer is greater than a width of the core; wherein a sidewall of the core and the dielectric layer are separated by the second portion of the protective layer; wherein the width of the core is greater than or equal to the width of the seed layer.
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Hirano’s Figure 1-Annotated.
However, in the same semiconductor device field of endeavor, Hirano discloses a dielectric layer (9 a protective film made of silicon nitride in [0070], Fig. 1) over the substrate (20 a semiconductor substrate in [0066], Fig. 1) and surrounding (Fig. 1-Annotated) the conductive member (30 an interconnect in [0069], Fig. 1); and a capping layer (8 a gold layer in [0067], Fig. 1) disposed on the first portion of the protective layer (7 a nickel layer such as protection layer to prevent the diffusion of the copper in [0067], Fig. 1) and the core (6 a layer made of Cu in [0067], Fig. 1); wherein a width of the capping layer (8, Hirano) is substantially greater than (Fig. 1) a width of the seed layer (5 a seed layer made of Cu having a width less than a width of core 6 in [0067], Fig. 1); wherein the width of the first portion of the protective layer (7 in [0067], Fig. 1) is greater (Fig. 1) than a width of the core (6 in [0067], Fig. 1); wherein the width of the core (6 in [0067], Fig. 1) is greater (Fig. 1) than or equal to the width of the seed layer (5 in [0067], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hirano’s feature of a dielectric layer over the substrate and surrounding the conductive member; and a capping layer disposed on the first portion of the protective layer and the core; wherein a width of the capping layer is substantially greater than a width of the seed layer and a seed layer having a width less than a width of the core layer; wherein the width of the first portion of the protective layer is greater than a width of the core; wherein the width of the core is greater than or equal to the width of the seed layer to Schneegans’s device to have a side surface and a bottom surface of the second portion of the protective layer are in contact with the dielectric layer, such that the seed layer is not in contact with the bottom surface of the second portion of the protective layer, wherein a sidewall of the core and the dielectric layer are separated by the second portion of the protective layer for improving of the electrical and mechanical connectivity between the interconnect and a wire bonded to the interconnect, as providing protection to the device ([0067, 0070], Hirano).
Schneegans modified by Hirano does not expressly disclose wherein the width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer.
However, the Applicant has not presented persuasive evidence that the claimed
“width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer). Also, the applicant has not shown that the claimed “difference of width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Schneegans discloses “width of the protective layer 28 equal to a width of the conductive member 50-52-26-28” and Hirano discloses a width of the capping layer 8 equal to the width of the protective layer 7, then it is obvious to make the width of the capping layer is equal to a width of conductive member, therefore, the width is a result effective variable. It has been held that is not inventive to discover the optimum width of the capping layer, the conductive member and the protective layer structure by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the width of the capping layer is equal to a width of conductive member which is a width of the first portion of the protective layer to the rest of the claimed invention for improving of the electrical and mechanical connectivity between the interconnect and a wire bonded to the interconnect, as providing protection to the device ([0067, 0070], Hirano).
Re: Claim 2, Schneegans modified by Hirano discloses the semiconductor structure of Claim 1,
Schneegans modified by Hirano does not expressly disclose the width of the core is equal to the width of the seed layer, such that a bottom surface of the core is not in contact with the dielectric layer.
However, the Applicant has not presented persuasive evidence that the claimed
“width of the core equal to the width of the seed layer, such that a bottom surface of the core is not in contact with the dielectric layer” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed width of the core equal to the width of the seed layer). Also, the applicant has not shown that the claimed “difference of width of the core equal to the width of the seed layer” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Schneegans discloses a width of the core 26 smaller than a width of the seed layer 52 and Hirano discloses a width of the core 6 larger than a width of the seed layer 5, then it is obvious to make the width of width of the core equal to the width of the seed layer, therefore, the width is a result effective variable. It has been held that is not inventive to discover the optimum width of the core and the width of the seed layer by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II).
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add a width of the core equal to the width of the seed layer, such that a bottom surface of the core is not in contact with the dielectric layer to the rest of the claimed invention for improving of the electrical and mechanical connectivity between the interconnect and a wire bonded to the interconnect, as providing protection to the device ([0067, 0070], Hirano).
Re: Claim 3, Schneegans modified by Hirano discloses the semiconductor structure of Claim 1,
wherein the width of the core (6, Hirano) is greater (Fig. 1, Hirano) than the width of the seed layer (5 in [0067], Fig. 1, Hirano), such that a portion of a bottom surface of the core (26, Schneegans) is in contact with the dielectric layer (Hirano’s 9 applied to Schneegans).
Re: Claim 4, Schneegans modified by Hirano discloses the semiconductor structure of Claim 1, wherein the core (26, Schneegans) includes copper (metal such as copper in [0025], Schneegans), and the protective layer (28, Schneegans) includes nickel (made of nickel in [0027, 0028], Schneegans).
Re: Claim 6, Schneegans modified by Hirano discloses the semiconductor structure of Claim 1, wherein the first portion (28-top, Schneegans) of the protective layer (28, Schneegans) is disposed between and in contact with the capping layer (8, Hirano) and the core (26, Schneegans), and the second portion (28-side, Schneegans) of the protective layer (28, Schneegans) is disposed under the capping layer (8 from Hirano applied to Schneegans).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Schneegans, in view of Hirano and further in view of Gambee (US 20190189507 A1, hereinafter Gambee, of the record).
Re: Claim 5, Schneegans modified by Hirano discloses the semiconductor structure of Claim 1, wherein the seed layer (52 in [0023], Fig. 1, Schneegans) is in contact between the substrate (22 in [0022], Fig. 1, Schneegans) and the core (26 in [0025], Fig. 1, Schneegans).
Schneegans modified by Hirano does not expressly disclose wherein the seed layer includes titanium and copper.
However, in the same semiconductor device field of endeavor, Gambee discloses the seed layer (202 a seed material in [0030], Fig. 3D) includes titanium and copper (202 having a bi-layer comprise titanium and copper in [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Gambee’s feature of the seed layer includes titanium and copper to the combination of Schneegans and Hirano to enhance adherence of the to-be-formed conductive traces, as well as a barrier with respect to substrate ([0026], Gambee).
Claims 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Schneegans, in view of Shih (US 20200168543 A1, hereinafter Shih), and further in view of Hirano.
Re: Independent Claim 7, Schneegans discloses a semiconductor structure (20 an electronic device in [0020], Fig. 1), comprising:
a substrate (22 a semiconductor wafer substrate in [0022], Fig. 1);
a first conductive member (50-L,52-L,26-L,28-L a first conductive member on left side, including 50,52,26,28 in [0005, 0022], Fig. 1) disposed over the substrate (22); and
a second conductive member (50-R,52-R,26-R,28-R a second conductive member on right side, including 50,52,26,28 in [0005, 0022], Fig. 1, Schneegans) disposed over the substrate (22, Schneegans) and adjacent to the first conductive member (50-L,52-L,26-L,28-L, Schneegans);
wherein the first conductive member (50-L,52-L,26-L,28-L) comprises a first seed layer (52-L a seed layer in [0023], Fig. 1) disposed over the substrate (22), a first core (26-L a conducting line including a metal such as copper in [0025], Fig. 1) disposed over the seed layer (52), a first protective layer (28-L a layer including a conducting material such as nickel in [0027, 0028], Fig. 1) having a first portion (28-L-top Fig. 1-Annotated) disposed on a top surface (Fig. 1) of the first core (26) and having a second portion (28-L-side Fig. 1-Annotated) on a sidewall (Fig. 1) of the first core (26); wherein the second conductive member (50-R,52-R,26-R,28-R, Schneegans) comprises a second seed layer (52-R a seed layer in [0023], Fig. 1, Schneegans) disposed over the substrate (22, Schneegans), a second core (26-R a conducting line including a metal such as copper in [0025], Fig. 1, Schneegans) disposed over the second seed layer (52-R, Schneegans), a second protective layer (28-R a layer including a conducting material such as nickel in [0027, 0028], Fig. 1, Schneegans) disposed on a top surface (Fig. 1, Schneegans) of the second core (26-R, Schneegans) and on a sidewall of the second core (26-R, Schneegans), and
wherein a height of the first conductive member (50-L,52-L,26-L,28-L, Schneegans) is equal (Fig. 1, Schneegans) to a height of the second conductive member (50-R,52-R,26-R,28-R, Schneegans).
Schneegans does not expressly a conductive bump disposed on and electrically connected to the first conductive member, wherein the second conductive member is a conductive bump free member; a first capping layer disposed over the first protective layer; and a second capping layer disposed over the second protective layer; wherein a width of the second capping layer is substantially greater than a width of the second seed layer; wherein the first seed layer is not in contact with a bottom surface of the second portion of the first protective layer.
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Shih’s Figure 4-Annotated.
However, in the same semiconductor device field of endeavor, Shih discloses a conductive bump (203 a second connector as a bump in [0066], Fig. 4) disposed on and electrically connected (Fig. 4) to the first conductive member (105 a conductive via in [0053], Fig. 4), wherein the second conductive member (106 a metallic strip in [0055], Fig. 4) is a conductive bump (106 does not includes bumps 203 Fig. 4) free member.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shih’s feature of a conductive bump disposed on and electrically connected to the first conductive member, wherein the second conductive member is a conductive bump free member to Schneegans’s device to improve the structure and the fabrication of semiconductor devices ([0004], Shih).
Schneegans modified by Shih does not expressly a first capping layer disposed over the first protective layer; and a second capping layer disposed over the second protective layer; wherein a width of the second capping layer is substantially greater than a width of the second seed layer; wherein the first seed layer is not in contact with a bottom surface of the second portion of the first protective layer.
However, in the same semiconductor device field of endeavor, Hirano discloses a first capping layer (8 a gold layer in [0067], Fig. 1) disposed over the first protective layer (7 a nickel layer such as protection layer to prevent the diffusion of the copper in [0067], Fig. 1); wherein a width of the second capping layer (8 Fig. 1) is substantially greater than (Fig. 1) a width of the second seed layer (5 a seed layer made of Cu having a width less than a width of the core 6 in [0067], Fig. 1).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hirano’s feature of a first capping layer disposed over the first protective layer; wherein a width of the second capping layer is substantially greater than a width of the second seed layer to Schneegans’s device to obtain wherein the first seed layer is not in contact with a bottom surface of the second portion of the first protective layer for improving of the electrical and mechanical connectivity between the interconnect and a wire bonded to the interconnect ([0067], Hirano).
Schneegans modified by Shih and Hirano does not expressly disclose a second capping layer disposed over the second protective layer.
However, in the same semiconductor device field of endeavor, Hirano discloses a capping layer (8 a gold layer in [0067], Fig. 1) disposed over a protective layer (7 a nickel layer such as protection layer to prevent the diffusion of the copper in [0067], Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hirano’s feature of a second capping layer disposed over the second protective layer to the combination of Schneegans, Shih and Hirano for improving of the electrical and mechanical connectivity between the interconnect and a wire bonded to the interconnect ([0067], Hirano).
Re: Claim 8, Schneegans modified by Shih and Hirano discloses the semiconductor structure of Claim 7,
Schneegans modified by Shih and Hirano does not expressly further comprising a bump pad disposed on the first conductive member, wherein the conductive bump is disposed on the bump pad to electrically connect with the first conductive member, wherein a width of the bump pad is greater than the width of the first capping layer.
However, in the same semiconductor device field of endeavor, Shih discloses a bump pad (105b a pad portion in [0054], Fig. 4) disposed on the first conductive member (105 a conductive via in [0053], Fig. 4), wherein the conductive bump (203 a second connector as a bump in [0066], Fig. 4) is disposed on the bump pad (105b) to electrically connect with the first conductive member (105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shih’s feature of a bump pad disposed on the first conductive member, wherein the conductive bump is disposed on the bump pad to electrically connect with the first conductive member to the combination of Schneegans, Shih and Hirano to improve the structure and the fabrication of semiconductor devices ([0004], Shih).
Still, Schneegans modified by Shih and Hirano does not expressly wherein a width of the bump pad is greater than the width of the first capping layer.
However, the Applicant has not presented persuasive evidence that the claimed “width of the bump pad greater than the width of the first capping layer” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of a width of the bump pad greater than the width of the first capping layer). Also, the applicant has not shown that the claimed “difference of width of the bump pad greater than the width of the first capping layer” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Shih discloses a width of the bump pad 105b greater than a width of the first conductive member 105, therefore, the width is a result effective variable. It has been held that is not inventive to discover the optimum width of the bump pad and the width of the first capping layer by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the width of the bump pad greater than the width of the first capping layer to improve the structure and the fabrication of semiconductor devices ([0004], Shih).
Re: Claim 9, Schneegans modified by Shih and Hirano discloses the semiconductor structure of Claim 8,
Schneegans modified by Shih and Hirano does not disclose wherein a width of the first conductive member is greater than or less than a width of the second conductive member.
However, the Applicant has not presented persuasive evidence that the claimed
“width of the first conductive member is greater than or less than a width of the second conductive member” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed range of the width of the first conductive member is greater than or less than a width of the second conductive member). Also, the applicant has not shown that the claimed “difference of width of the first conductive member is greater than or less than a width of the second conductive member” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. At meantime, Schneegans discloses “a width of the first conductive member that is the same of width of the second conductive member”, therefore, the width is a result effective variable. It has been held that is not inventive to discover the optimum width of the first conductive member and a width of the second conductive member by routine experimentation (In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), MPEP 2144.05 II). Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add the width of the first conductive member is greater than or less than a width of the second conductive member to increase or decrease the connector density in the device.
Re: Claim 10, Schneegans modified by Shih and Hirano discloses the semiconductor structure of Claim 8, wherein the first protective layer (28-L, Schneegans) and the second protective layer (28-R, Schneegans) include a same material (a conducting material such as nickel in [0028], Fig. 1, Schneegans)
Re: Claim 11, Schneegans modified by Shih and Hirano discloses the semiconductor structure of Claim 8,
Schneegans modified by Shih and Hirano does not expressly disclose further comprising: a dielectric layer over the substrate and surrounding the first conductive member and the second conductive member; wherein a top surface of the dielectric layer, a top surface of the first capping layer, and a top surface of the second capping layer are coplanar with each other.
However, in the same semiconductor device field of endeavor, Hirano discloses
a dielectric layer (9 a protective film made of silicon nitride in [0070], Fig. 1) over the substrate (20 a semiconductor substrate in [0066], Fig. 1) and surrounding a conductive member (5,6,7 a seed layer 5, a core layer 6 and a protective layer 7 in [0067], Fig. 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hirano’s feature of a dielectric layer over the substrate and surrounding a conductive member to the combination of Schneegans, Shih and Hirano to obtain a dielectric layer over the substrate and surrounding the first conductive member and the second conductive member; wherein a side surface and a bottom surface of the second portion of the protective layer are in contact with the dielectric layer for protecting the device ([0070], Hirano).
Schneegans modified by Shih and Hirano does not expressly disclose wherein a top surface of the dielectric layer, a top surface of the first capping layer, and a top surface of the second capping layer are coplanar with each other.
However, in the same semiconductor device field of endeavor, Shih discloses a top surface of the dielectric layer (104c a dielectric layer in [0052], Fig. 4) and a top surface of the conductive member (105 a conductive via in [0053], Fig. 4) are coplanar with each other (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Shih’s feature of a top surface of the dielectric layer and a top surface of the conductive member are coplanar with each other to the combination of Schneegans, Shih and Hirano to improve the structure and the fabrication of semiconductor devices ([0004], Shih).
The combination of Schneegans, Shih and Hirano results in a top surface of the dielectric layer (Shih’s 104c applied to Hirano’s 9), a top surface of the first capping layer (Hirano’s 8 applied to Schneegans), and a top surface of the second capping layer (Hirano’s 8 applied to Schneegans) are coplanar with each other.
Re: Claim 12, Schneegans modified by Shih and Hirano discloses the semiconductor structure of Claim 11,
Schneegans modified by Shih and Hirano does not expressly disclose wherein the dielectric layer is at least partially in contact with a bottom wall of the first core.
However, in the same semiconductor device field of endeavor, Hirano discloses wherein the dielectric layer (9, Hirano, Fig. 1) is at least partially in contact with a bottom wall (Hirano, Fig. 1) of the first core (6 made of Cu in [0067], Fig. 1, Hirano).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Hirano’s feature wherein the dielectric layer is at least partially in contact with a bottom wall of the first core to the combination of Schneegans, Shih and Hirano for protecting the device ([0070], Hirano).
Conclusion
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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