DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 9-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/29/2025.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the silicon oxide" in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of prosecution, either the first silicon oxide film or the second oxide film will be considered to meet the limitations of claim 5’s “the silicon oxide film”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (U.S. Publication No. 2019/0198510 A1)
With respect to claim 17, Kim discloses a system comprising: a host, including a processor [1018]; a three-dimensional (3D) NAND memory device [1002], coupled to the host, having, a stacked layer structure, including a plurality of wordline layers [WL0 through WLm] (see Figure 1 and [86] in Figure 23); a plurality of vertical memory holes [66/68] (see Figure 23), formed in the stacked layer structure; a plurality of stacked memory layers [1003] (see Figure 1), each memory layer including an array of floating-gate memory cells in a respective wordline layer, a memory cell comprising, a control gate [84]; a storage node [50]; and a plurality of inter-poly dielectric (IPD) films [42/44/76] disposed between the storage node and the control gate, wherein memory cells in different memory layers form strings of memory cells sharing a vertical memory hole and wherein memory cells sharing a vertical memory hole in adjacent wordline layers are separated by inter-wordline airgaps [88a] (see Figure 23).
With respect to claim 20, Kim discloses wherein the vertical memory holes pass through at least 50 wordline layers, and, for a string of memory cells, a level of uniformity of a first memory cell structure in a top wordline layer and a second memory cell structure in bottom wordline layer is substantially the same (See Kim Figure 1-2; as many wordline layers WLm as desired and Figure 23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-8 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Koval et al. (U.S. Publication No. 2019/0043960 A1; hereinafter Koval)
With respect to claim 1, Kim discloses a memory device, comprising: a stacked layer structure, including a plurality of wordline layers [WL0 through WLm] (see Figure 1 and [86] in Figure 23); a plurality of vertical memory holes [66/68] (see Figure 23), formed in the stacked layer structure; a plurality of stacked memory layers [1003] (see Figure 1), each memory layer including an array of floating-gate memory cells in a respective wordline layer, comprising, a control gate [84]; a storage node [50]; and a plurality of inter-poly dielectric (IPD) films [42/44/76] disposed between the storage node and the control gate, wherein memory cells in different memory layers form strings of memory cells sharing a vertical memory hole (see Figure 23). Kim fails to disclose wherein a cross-section profile of the control gate and storage node have vertical sides that are flat. In the same field of endeavor, Koval teaches wherein a cross-section profile of the control gate [108] and storage node [105] have vertical sides that are flat (see Figure 1A) as an alternative to a curved vertical profile (see Figure 6A). Implementation of a modified geometry of the control gate and storage node, as taught by Koval contributes to improved device performance and reliability of the memory cell (See Koval ¶[0024]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 2, the combination of Kim and Koval discloses a plurality of inter-wordline airgaps [88a] between adjacent pairs of wordline layers (See Kim Figure 23).
With respect to claim 3, the combination of Kim and Koval discloses wherein the control gate and storage node comprise polysilicon (poly-Si) (see Kim ¶[0044], ¶[0062] and Koval ¶[0022]).
With respect to claim 4, the combination of Kim and Koval discloses wherein the IPD films comprise: a first silicon oxide film [44]; a first silicon nitride film [42] adjacent to the first silicon oxide film; and a second silicon oxide film, adjacent to the first silicon nitride film (See Kim ¶[0042], ¶[0061] and Koval ¶[0022]).
With respect to claim 5, the combination of Kim and Koval discloses wherein the IPD films further comprise a second silicon nitride film [115] adjacent to the silicon oxide film (see Koval ¶[0027]).
With respect to claim 6, the combination of Kim and Koval discloses wherein the plurality of IPD films have vertical sides that are flat (see Kim Figure 23 and Koval Figure 1A).
With respect to claim 7, the combination of Kim and Koval discloses wherein the vertical memory holes pass through at least 50 wordline layers, and, for a string of memory cells, a level of uniformity of a first memory cell structure in a top wordline layer and a second memory cell structure in bottom wordline layer is substantially the same (See Kim Figure 1-2; as many wordline layers WLm as desired and Figure 23)
With respect to claim 8, the combination of Kim and Koval discloses wherein fabrication of the memory device comprises: fabricating a stacked layer structure comprising alternating layers of polysilicon [32] and silicon nitride [18]; forming a plurality of memory hole passing vertically through the alternating layers of polysilicon and silicon nitride (See Figure 8); performing in-memory hole processing under which multiple films of materials are formed over sidewalls of the plurality of memory holes (See Figure 14); forming inter-wordline airgaps between the polysilicon layers (See Figure 20); and performing back-side isolation processing to selectively form memory cells in between the polysilicon layers (see Figure 22; Note: Claim is a product-by process claim. "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process." In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985).)
With respect to claim 18, Kim fails to disclose wherein a cross-section profile of the control gate and storage node for a memory cell have vertical sides that are straight.
In the same field of endeavor, Koval teaches wherein a cross-section profile of the control gate [108] and storage node [105] for a memory cell have vertical sides that are straight (see Figure 1A) as an alternative to a curved vertical profile (see Figure 6A). Implementation of a modified geometry of the control gate and storage node, as taught by Koval contributes to improved device performance and reliability of the memory cell (See Koval ¶[0024]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention
With respect to claim 19, Kim fails to disclose wherein the IPD films comprise one of: a first silicon oxide film; a silicon nitride film adjacent to the first silicon oxide film; and a second silicon oxide film, adjacent to the silicon nitride film; or a first silicon oxide film; a first silicon nitride film adjacent to the first silicon oxide film; a second silicon oxide film, adjacent to the first silicon nitride film; and a second silicon nitride film adjacent to the second silicon oxide film, however does disclose a first silicon oxide layer [44] and first silicon nitride layer [42]. In the same field of endeavor, Koval teaches the IPD films comprise one of: a first silicon oxide film; a silicon nitride film adjacent to the first silicon oxide film; and a second silicon oxide film, adjacent to the silicon nitride film; or a first silicon oxide film; a first silicon nitride film adjacent to the first silicon oxide film; a second silicon oxide film, adjacent to the first silicon nitride film; and a second silicon nitride film adjacent to the second silicon oxide film (see ¶[0022]).
Implementation of the IPD films in the orientation as taught by Koval within the NAND device of Kim allows for proper insulation of the corresponding floating gate from the adjacent memory cell (See ¶[0029]). Therefore, it would have been obvious to one of ordinary skill in the art at the time of invention that the combination of references would arrive at the claimed invention.
Conclusion
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/JONATHAN HAN/Primary Examiner, Art Unit 2818