DETAILED ACTION This correspondence is in response to the communications received FILLIN "Enter date" \* MERGEFORMAT FILLIN "Enter appropriate date" \* MERGEFORMAT 02/02/2026 . Claims FILLIN "Enter claim identification information" \* MERGEFORMAT 19 and 20 have been withdrawn. Claims FILLIN "Enter claim identification information" \* MERGEFORMAT 1-18 and 21 are pending. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of FILLIN "Enter claim indentification information" \* MERGEFORMAT claims 1-18 and 21 in the reply filed on FILLIN "Enter mail date of the reply." \* MERGEFORMAT 02/02/2026 is acknowledged. Claim FILLIN "Enter claim identification information" \* MERGEFORMAT s 19 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected FILLIN "Enter the appropriate information" \* MERGEFORMAT invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on FILLIN "Enter mail date of the reply." \* MERGEFORMAT 02/02/2026 . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement s (IDS) submitted on 03/27/2024 and 08/26/2025 ha ve been considered by the examiner and made of record in the application file. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claim 21 is objected to because of the following informalities: Claim 21 requires “A packaging structure for asymmetric transient voltage suppressor”, it appears this should be written as “A packaging structure for an asymmetric transient voltage suppressor” . Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim FILLIN "Enter claim indentification information" \* MERGEFORMAT 13 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 13 recites the limitation “wherein the one or more stress relief grooves are configured to be formed symmetrically about the stress relief opening in the slanted portion of the lead frame”. There is insufficient antecedent basis for this limitation in the claim. While claim 12 does require “wherein the one or more first stress relief features include at least one of the following: a stress relief opening, one or more stress relief grooves, and any combination thereof”, this limitation only requires one of the stress relief opening or the one or more stress relief grooves, not both as required in claim 13. Thus, there is insufficient antecedent basis in claim 13. Applicant’s Claim to Figure Comparison It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant. Regarding claim 1, an apparatus ("surface mount packaging structure 100"), comprising: a housing (102); a lead frame ("second lead 110"), at least partially encapsulated by the housing (see Fig. 1), the lead frame including a chip mounting surface ("chip mounting surface (e.g., panel 210 as shown in FIGS. 2 and 6)", [0070]) having a chip mounting pad ("chip support pad 112"), and one or more first stress relief features ("stress protection/relief opening(s) 202 and stress protection/relief groove(s) 206 (a, b) (as shown in FIGS. 2 and 6)", [0069]) disposed outside of the chip mounting surface (see Fig. 2); and another lead frame ("first lead 108"), at least partially encapsulated by the housing (see Fig. 1), the another lead frame including one or more second stress relief features ("protection/relief bar 204, as shown in FIGS. 2 and 6"). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-4 and 7-16 are rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 20180331021 A1, published 11/15/2018) in view of Griffin (US 8,105,880 B2, published 01/31/2012) in view of Lin et al. ( US 20200235255 A1, published 07/23/2020) . Regarding claim 1, Figs. 13-15 of Qin disclose an apparatus (“the die package component 100”, [0054]), comprising: a housing (“package body 4”, [0053]); a lead frame (“the first lead frame 211”, [0053]), at least partially encapsulated by the housing ( as seen in Fig. 14 , 211 is at least partially encapsulated by 4 ), the lead frame including a chip mounting surface (“die connection surface 2111”, [0052]) having a chip mounting pad (Qin does not disclose a chip mounting pad, however a secondary reference will be used to teach this limitation below) , and one or more first stress relief features (the opening denoted “OP1” in Fig. 15 is a first stress relief feature, however Qin does not specifically disclose this functionality, instead a secondary reference will be used to teach this limitation below) disposed outside of the chip mounting surface (as seen in Fig. 15, OP1 is disposed outside of 2111) ; and another lead frame (“second lead frame 212”, [0053]) , at least partially encapsulated by the housing (as seen in Fig. 14, 212 is at least partially encapsulated by 4) , the another lead frame including one or more second stress relief features (“guide-stop structures 2122”, [0051], where “the lead welding portion 112 is constrained by the two guide-stop structures 2122 so as to prevent the lead welding portion 112 from leaving the lead frame connection groove 2121 along the vertical route P”, [0051]) . Qin fails to disclose “a lead frame … including a chip mounting surface having a chip mounting pad, and one or more first stress relief features”. However, in a similar field of endeavor, Figs. 1-22 of Griffin teach a lead frame (“ leadframe 4”, col. 8, line 45) … including a chip mounting surface (as seen in Fig. 1, the upper surface of 4 is a chip mounting surface) having a chip mounting pad (“carrier pad 3”, col. 8, line 44). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a lead frame … including a chip mounting surface having a chip mounting pad” as taught by Griffin in the system of Qin for improving the mechanical and electrical connection between a die and a leadframe . Qin in combination with Griffin fails to specify “a lead frame … including … one or more first stress relief features”. However, in a similar field of endeavor, Figs. 4 and 5 of Lin teaches a lead frame (“chip-mounting frame 10a”, [0047]) … including … one or more first stress relief features (“The first through-hole 110 and the second through-hole 210 can minimize stress generation when bending the leads”, [0047], thus as OP1 of Qin is equivalent to 110 of Lin, OP1 is a first stress relief feature). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a lead frame … including … one or more first stress relief features” as taught by Lin the system of Qin in combination with Griffin for the purpose of minimizing stress during device processing. Regarding claim 2, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1, Figs. 1-22 of Griffin further disclose wherein a semiconductor chip is configured to be coupled to the chip mounting pad (as seen in Fig. 1, “semiconductor die 2”, col. 8, lines 43-44, is coupled to 3 , where 2 of Griffin is equivalent to “die 3”, [0050] of Qin ). Regarding claim 3, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 3, Figs. 1-22 of Griffin further disclose wherein, upon coupling of the semiconductor chip to the chip mounting pad, the chip mounting surface does not contact the semiconductor chip (as seen in Fig. 1, the upper surface of 4 does not contact 2). Regarding claim 4, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 3, Figs. 13-15 of Qin further disclose further comprising a clip (“jumper structure 11”, [0052] , Merriam-Webster defines a clip as “any of various devices that grip, clasp, or hook” and as seen in Fig. 14, 11 hooks onto 212, thus 11 is a clip ) fully encapsulated by the housing (as seen in Fig. 14, 11 is fully encapsulated by 4), wherein the another lead frame is configured to be coupled to the clip (as seen in Fig. 14, 212 is coupled to 11). Regarding claim 7, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 4, Figs. 13-15 of Qin further disclose wherein the clip is configured to include one or more support bars extending laterally away from one or more edges of the clip (as seen in Fig. 15, the portions of 11 denoted “SB” are support bars that extend laterally away from the edges of 11, while Qin does not explicitly state that SB are support bars, one having ordinary skill in the art would recognize that such structures would limit the movement of 11 with 4 in the R direction as seen in Figs. 14 and 15 ). Regarding claim 8 , Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 4, Figs. 13-15 of Qin further disclose wherein the one or more second stress relief features include one or more stress relief bars extending laterally away from the another lead frame (as previously discussed 2122 are stress relief features, and as seen in Fig. 15, 2122 extend laterally away from 212 and are in the shape of a bar) . Regarding claim 9, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 8, Figs. 13-15 of Qin further disclose wherein the clip is configured to have a curved structure (as seen in Fig. 14, 11 has a curved structure), wherein at least a portion of the curved structure of the clip is configured to extend away from the semiconductor chip (as seen in Fig. 14, the leftmost portion of 11 is configured to extend away from 3 in the upwards direction). Regarding claim 10, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1, Figs. 13-15 of Qin further disclose wherein the lead frame includes a slanted portion (as seen in Fig. 14, 211 includes a slanted portion denoted “SP”) configured to angularly extend away from the chip mounting surface (as seen in Fig. 14, SP angularly extends away from 2111). Regarding claim 11, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 10, Figs. 13-15 of Qin further disclose wherein the one or more first stress relief features are configured to be formed in the slanted portion (as seen in Fig. 15, OP1 is formed in SP). Regarding claim 12, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 11, Figs. 13-15 of Qin further disclose wherein the one or more first stress relief features include at least one of the following: a stress relief opening, one or more stress relief grooves, and any combination thereof (as seen in Fig. 15, OP1 is a stress relief opening). Regarding claim 1 3 , Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1 2 , Figs. 4 and 5 of Lin further disclose wherein the one or more stress relief grooves (“ first groove 120 ”, [0046] , Lin does not specify that 120 are “ stress relief grooves ”, however, one having ordinary skill in the art would recognize that grooves effectively thin the element they are made in and would thereby reduce the stress induced by bending said element ) . Figs. 13-15 of Qin further disclose wherein the one or more stress relief grooves are configured to be formed symmetrically about the stress relief opening (as seen in Fig. 15, OP1 is centered vertically in 211, therefore after combining Qin and Lin, 120 of Lin which will extend the entire height of 211 as seen in Fig. 4 of Lin and will therefore be formed symmetrically about OP1 ) in the slanted portion of the lead frame (after combining Qin and Lin, 120 of Lin will be adjacent to OP1 of Qin, and will therefore be in SP of Qin). Regarding claim 14, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1, Figs. 13-15 of Qin further disclose where the lead frame includes a lead frame terminal end (“first lead 2112”, [0053], as seen in Fig. 14, 2112 is a terminal end of 211) and the another lead frame includes another lead frame terminal end (“second lead 2123”, [0053], as seen in Fig. 14, 2123 is a terminal end of 212). Regarding claim 15, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 14, Figs. 1-22 of Griffin further disclose wherein the lead frame terminal end and the another lead terminal frame end are configured to be coupled to at least one of the following: a substrate, a printed circuit board, and any combination thereof (“Mutually insulated leads 8 of the leadframe 4 extend outwardly from the encapsulating housing 7 for electrically coupling the semiconductor device 1 to, for example, a printed circuit board (not shown)”, col. 8, lines 50-54, where 8 of Griffin are equivalent to 2112 and 2123 of Qin). Regarding claim 16, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1, Figs. 4 and 5 of Lin further discloses wherein the housing is manufactured from at least one of the following: an epoxy compound, a plastic, and any combination thereof (“housing 30 in a preferred implementation may be opaque to all radiation in and/or around the visible spectrum, for example, being formed of optically opaque thermoplastic molding material”, [0038], where 30 of Lin is equivalent to 4 of Qin). Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 20180331021 A1, published 11/15/2018) in view of Griffin (US 8,105,880 B2, published 01/31/2012) in view of Lin et al. (US 20200235255 A1, published 07/23/2020) in view of Romig et al. (US 20210257282 A1, published 08-19-2021). Regarding claim 5, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 4. Qin in combination with Griffin and Lin fails to disclose “wherein the semiconductor chip includes a semiconductor chip working area.” However, in a similar field of endeavor, Figs. 1-2 of Romig teach wherein the semiconductor chip includes a semiconductor chip working area (as seen in Fig. 2, “second Rx die 142 and the Tx die 130 each comprise a substrate 105a and 105b, such as comprising silicon, including circuitry for each die shown as 180a and 180b having nodes connected to bond pads 131a and 131b”, [0031], where 180a is a working area and 130 of Romig is equivalent to 3 of Qin). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the semiconductor chip includes a semiconductor chip working area” as taught by Romig in the system of Qin in combination with Griffin and Lin for the purpose of providing electronic functionality to the die. Regarding claim 6, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin , Figs. 4 and 5 of Lin , and Figs. 1-2 of Romig disclose the apparatus according to claim 5, Figs. 13-15 of Qin further disclose wherein the clip is configured to be coupled to the semiconductor chip working area (as seen in Fig. 14, 11 is coupled to 3, thus after combining Qin and Romig , 11 would be coupled to 180a of Romig as 180a would be included in 3 of Qin. Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 20180331021 A1, published 11/15/2018) in view of Griffin (US 8,105,880 B2, published 01/31/2012) in view of Lin et al. (US 20200235255 A1, published 07/23/2020) in view of Ding et al . (US 10 , 163 , 762 B2, published 12-25-2018). Regarding claim 17, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1. Qin in combination with Griffin and Lin fails to disclose “wherein the apparatus is configured to be a surface mounted apparatus.” However, in a similar field of endeavor, Fig s . 1 -3 of Ding teach wherein the apparatus is configured to be a surface mounted apparatus (“A semiconductor package assembly is provided that includes a semiconductor die and a conductive clip and provides an assembly suitable for high-power applications. Clip bonding is used in a number of semiconductor package assemblies, including, for example, surface mount packages”, col. 2, lines 28-32, thus 100 of Qin can be a surface mount apparatus). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the apparatus is configured to be a surface mounted apparatus” as taught by Ding in the system of Qin in combination with Griffin and Lin for the purpose of easily integrating the die package component into a larger device. Regarding claim 18, Figs. 13-15 of Qin in combination with Figs. 1-22 of Griffin and Figs. 4 and 5 of Lin disclose the apparatus according to claim 1. Qin in combination with Griffin and Lin fails to disclose “further comprising a transient voltage suppression device.” However, in a similar field of endeavor, Figs. 1-3 of Ding teach further comprising a transient voltage suppression device (“ By way of example the die 110 may be a two terminal device such as a diode, a transient voltage suppressor or an LED ”, col. 2 , lines 56-58, thus 3 of Qin can be a transient voltage suppression device ). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “ further comprising a transient voltage suppression device ” as taught by Ding in the system of Qin in combination with Griffin and Lin for the purpose of protecting connected electrical devices from overvoltage damage . Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Qin et al. (US 20180331021 A1, published 11/15/2018) in view of Appel (US 20230412167 A1, filed 10-08-2021) in view of Griffin (US 8,105,880 B2, published 01/31/2012) in view of Lin et al. (US 20200235255 A1, published 07/23/2020). Regarding claim 2 1, Figs. 13-15 of Qin disclose a packaging structure for asymmetric transient voltage suppressor (“the die package component 100”, [0054], Qin does not specify that 100 is for an asymmetric transient voltage suppressor, however a secondary reference will be used to teach this limitation below), comprising: a housing (“package body 4”, [0053]); a lead frame (“the first lead frame 211”, [0053]), at least partially encapsulated by the housing (as seen in Fig. 14, 211 is at least partially encapsulated by 4), the lead frame including a chip mounting surface (“die connection surface 2111”, [0052]) having a chip mounting pad (Qin does not disclose a chip mounting pad, however a secondary reference will be used to teach this limitation below), and one or more first stress relief features (the opening denoted “OP1” in Fig. 15 is a first stress relief feature, however Qin does not specifically disclose this functionality, instead a secondary reference will be used to teach this limitation below) disposed outside of the chip mounting surface (as seen in Fig. 15, OP1 is disposed outside of 2111); and another lead frame (“second lead frame 212”, [0053]), at least partially encapsulated by the housing (as seen in Fig. 14, 212 is at least partially encapsulated by 4), the another lead frame including one or more second stress relief features (“guide-stop structures 2122”, [0051], where “the lead welding portion 112 is constrained by the two guide-stop structures 2122 so as to prevent the lead welding portion 112 from leaving the lead frame connection groove 2121 along the vertical route P”, [0051]). Qin fails to disclose “ asymmetric transient voltage suppressor, … a lead frame … including a chip mounting surface having a chip mounting pad, and one or more first stress relief features”. However, in a similar field of endeavor, Appel teaches asymmetric transient voltage suppressor (“The power electronic module according to the invention is a power electronic module comprising at least one semiconductor switch and a gate-source control unit, wherein the gate-source control unit comprise an asymmetric transient voltage suppressor (TVS) diode or two Zener or one or more avalanche diodes arranged between the gate terminal and the source of the die or terminal of the semiconductor switch”, [0009]). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “asymmetric transient voltage suppressor” as taught by Appel in the system of Qin for the purpose of providing “an improved gate driver that is simple, fast and show a high current capability. Moreover, the gate driver does not require additional terminals to be controlled” (Appel, [0009]). Qin in combination with Appel fails to disclose “a lead frame … including a chip mounting surface having a chip mounting pad, and one or more first stress relief features”. However, in a similar field of endeavor, Figs. 1-22 of Griffin teach a lead frame (“ leadframe 4”, col. 8, line 45)… including a chip mounting surface (as seen in Fig. 1, the upper surface of 4 is a chip mounting surface) having a chip mounting pad (“carrier pad 3”, col. 8, line 44). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a lead frame … including a chip mounting surface having a chip mounting pad” as taught by Griffin in the system of Qin in combination with Appel for improving the mechanical and electrical connection between a die and a leadframe . Qin in combination with Appel and Griffin fails to specify “a lead frame … including … one or more first stress relief features”. However, in a similar field of endeavor, Figs. 4 and 5 of Lin teaches a lead frame (“chip-mounting frame 10a”, [0047]) … including … one or more first stress relief features (“The first through-hole 110 and the second through-hole 210 can minimize stress generation when bending the leads”, [0047], thus as OP1 of Qin is equivalent to 110 of Lin, OP1 is a first stress relief feature). Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a lead frame … including … one or more first stress relief features” as taught by Lin the system of Qin in combination with Appel and Griffin for the purpose of minimizing stress during device processing. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT BENJAMIN M KUPP whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5608 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday, 7:00 am - 4:00 pm PT . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Yara Green can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-3035 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN MICHAEL KUPP/ Examiner, Art Unit 2893 /YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893