DETAILED ACTION
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7-12 & 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over (US-4,351,677) by Mochizuki et al (“Mochizuki”).
Regarding claim 1, Mochizuki discloses in FIG. 1g and related text, e.g., a transient voltage suppression (TVS) device (first of all, the preamble in and of itself does not carry any patentable weight; second of all, col. 3, line 8 states the device of FIG. 1g is a “thyristor”; it is notoriously well-known in the art to use thyristors for an application, such as TVS device; as evidence of Examiner’s assertion, see US-6,266,223, col. 5, line 45: “transient voltage suppressor thyristor”; this is not an earliest use of thyristor in such application; this is merely the earliest that uses the exact wording, without any synonyms, and also in a single sentence; for example, see US-4,870,530, col. 1, line 35; it teaches use of thyristor as ESD protection structure (an example of “transient voltage suppression”); hence, use of thyristor of Mochizuki as TVS device, is at the very least obvious in light of preponderance of evidence), comprising:
a first layer, disposed on a first surface of a substrate, comprising a first P+ layer (top “p” layer, directly connected to “18”; as far as “P+”, this is an indicator of degree, which changes with technology and application; in other words, what one person calls “P+”, another person can call “P-“; there is no universally recognized industry standard for it; in other words, the “p” in Mochizuki can read on anything from “P-“ to “P+”);
a second layer, disposed on a second surface of the substrate, opposite the first surface, comprising a second P+ layer (bottom “p” layer, directly connected to “17”; the bottom horizontal portion);
a third layer, disposed between the first P+ layer and the second P+ layer, comprising an N- layer (the middle “n” layer, between the two “p” layers cited above); and
an isolation diffusion region, comprising a P structure, connected to the second P+ layer, and extending along a perimeter of the N- layer (bottom “p” layer, directly connected to “17”; the vertical portions on the left and right sides of the device).
Mochizuki does not explicitly state that his invention is “a transient voltage suppression (TVS) device” (Mochizuki has it, as was explained above; but, to eliminate all possible grounds for arguments, a “motivation to modify” is being elucidated).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Mochizuki with it being used in “a transient voltage suppression (TVS) device” application, since thyristors are notoriously well-known to be good in this sort of application (see explanation above, regarding preamble) and therefore this would be an appropriate use for Mochizuki’s device.
Regarding claim 2, Mochizuki discloses in FIG. 1g and related text, e.g., wherein the first layer, the second layer, and the third layer form a non-punch through device (this is what “transient voltage suppression” and “ESD protection structure” is; a “non-punch through device”) having a negative dynamic resistance in reverse blocking mode (first of all, these are “method of operating” limitations in a claim drawn to device, hence, they carry no patentable weight in a claim drawn to device; to elaborate briefly on the above, see US-3,659,200, FIG. 1 and col. 2, lines 41-65 and col. 4, line 61 through col. 5, line 24; they provide the necessary academic discussion of the term “negative dynamic resistance” and how it relates to the diodes; the above discussion makes clear that the limitations are merely a “method of operating” of diode; since thyristor in question (FIG. 1g) is just a series of diodes back to back (there are 3 p-n junctions, marked J1 through J3; thus there are 3 diodes; this means that the whole issue stops being related to a device under examination; now, it is just a matter of voltages applied to it [Wingdings font/0xE0] a “method of operating” limitations; second of all, please note that the reference in question is from 1972; hence, the whole topic of “operating diode in a negative dynamic resistance” mode is notoriously well-known; it is just a matter of desirability for specific application; third of all, the limitations “reverse blocking mode” automatically apply to back-to-back diodes; Mochizuki teaches connected diodes, of which at least one is p-n diode, and at least one is n-p diode; hence, at least one of them operates in “reverse blocking mode” no matter which way the voltages are applied; thus automatically meeting these limitations).
Mochizuki does not explicitly state that his invention is “having a negative dynamic resistance in reverse blocking mode” (Mochizuki has it, as was explained above; but, to eliminate all possible grounds for arguments, a “motivation to modify” is being elucidated).
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Mochizuki with it being used in a mode “having a negative dynamic resistance in reverse blocking mode”, since it is just a notoriously well-known mode of operating a diode (as explained above), and thus using such a notoriously well-known mode of operating of diode in an application where such a voltage curve is desired (as discussed above, regarding FIG. 1 of patent US-3,659,200) would be within abilities of a POSITA.
Regarding claim 3, Mochizuki discloses in FIG. 1g and related text, e.g., wherein the isolation diffusion region (the vertical left and right side portions of bottom “p” layer) extends from the second surface to the first surface (see FIG. 1g), wherein the first P+ layer extends over a first portion of the first surface (central portion of first (top) surface), wherein the N- layer extends over a second portion of the first surface (the portion of first (top) surface that is hidden under 31 (glass)), and wherein the first P+ layer is electrically isolated from the isolation diffusion region (it has 31 (glass) in-between).
Regarding claim 4, Mochizuki discloses in FIG. 1g and related text, e.g., but does not disclose “further comprising a mesa isolation region, extending from the first surface, and surrounding the first P+ layer, wherein the mesa isolation region is disposed in contact with the isolation diffusion region”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Mochizuki with “further comprising a mesa isolation region, extending from the first surface, and surrounding the first P+ layer, wherein the mesa isolation region is disposed in contact with the isolation diffusion region”, since “mesa” and “moat” are notoriously well-known structural equivalents that can be used interchangeably (as evidence of Examiner’s assertion, see US-4,113,516, which in col. 1, lines 14-34 makes it clear that its device is a “mesa” device; however, in col. 1, line 65 through col. 2, line 5, it makes clear that even back in 1978 the two structures (“mesa” and “moat”) were functional equivalents; hence, replacing “moat” of Mochizuki (the area filled with (31)) with a “mesa” instead going to the edge of the device (like the US-4,113,516 shows in FIG. 4, 54), would have been within the skills of a POSITA, the result being “a mesa isolation region (as was explained above), extending from the first surface (top surface), and surrounding the first P+ layer (it is already surrounding top p layer in FIG. 1g, and would continue to do so, when “moat” is replaced with “mesa” that goes to the left and right edges of the device), wherein the mesa isolation region is disposed in contact with the isolation diffusion region (the resultant continuation of mesa to the edge of the device, in FIG. 1g, would have the “mesa” contact the vertical P structure, which is “isolation diffusion region”, in a device where “moat” has been replaced with its functional equivalent “mesa”, as is notoriously well-known, and as is evidenced by US-4,113,516.
Regarding claim 7, Mochizuki discloses in FIG. 1g and related text, e.g., further comprising a moat isolation region (filled with 31 in FIG. 1g), extending from the first surface into the N-layer (see FIG. 1g), and surrounding the first P+ layer (see FIG. 1g), wherein the moat isolation region is disposed in contact with the isolation diffusion region (see FIG. 1g).
Regarding claim 8, Mochizuki discloses in FIG. 1g and related text, e.g., wherein the isolation region forms an isolation diffusion edge termination for the TVS device (by definition; it provide isolation on the edges; hence “edge termination for the TVS device”).
Regarding claim 9, Mochizuki discloses in FIG. 1g and related text, e.g., asymmetric bidirectional transient voltage suppression (TVS) device (see claim 1; regarding “asymmetric”, the device of FIG. 1g is not symmetric top to bottom; meaning, the diodes that form it are “asymmetric”), comprising:
a semiconductor substrate (semiconductor layers between 17 and 19), having a first main surface (top), a second main surface (bottom), opposite to the first main surface, and a set of side surfaces;
a first layer, disposed on the first main surface and comprising a first polarity (see claim 1);
a second layer, disposed on the second main surface and comprising the first polarity (see claim 1); and
a third layer, comprising a second polarity and being disposed within a bulk of the substrate, and being disposed between and in contact with the first layer and the second layer (see claim 1 and FIG. 1g); and
an isolation diffusion region, comprising a doped material having the first polarity, the isolation diffusion region being disposed along the set of side surfaces, connected to the second layer, and extending along a perimeter of the third layer (see claim 1 and FIG. 1g).
Regarding claim 10, Mochizuki discloses in FIG. 1g and related text, e.g., wherein the first layer comprises a first P+ layer, the second layer comprises a second P+ layer, and the third layer comprises an N- layer wherein the first P+ layer, the second P+ layer (see claim 1), and the N- layer form a non- punch through device having a negative dynamic resistance in reverse blocking mode (see claim 2).
Regarding claim 11, Mochizuki discloses in FIG. 1g and related text, e.g., wherein the isolation diffusion region extends from the second main surface to the first main surface, wherein the first P+ layer extends over a first portion of the first main surface, wherein the N- layer extends over a second portion of the first main surface, and wherein the first P+ layer is electrically isolated from the isolation diffusion region (see claim 3).
Regarding claim 12, Mochizuki discloses in FIG. 1g and related text, e.g., further comprising a mesa isolation region, extending from the first main surface, and surrounding the first P+ layer, wherein the mesa isolation region is disposed in contact with the isolation diffusion region (see claim 4).
Regarding claim 15, Mochizuki discloses in FIG. 1g and related text, e.g., further comprising a moat isolation region, extending from the first main surface into the N- layer, and surrounding the first P+ layer, wherein the moat isolation region is disposed in contact with the isolation diffusion region, and is not in contact with the set of side surfaces (see claim 7 and FIG. 1g).
Regarding claim 16, Mochizuki discloses in FIG. 1g and related text, e.g., wherein the isolation diffusion region forms an isolation diffusion edge termination (see claim 8).
Claims 5-6 & 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over (US-4,351,677) by Mochizuki et al (“Mochizuki”) in view of (US-2015/0285952) by Soloviev et al (“Soloviev”).
Regarding claim 5, Mochizuki discloses in FIG. 1g and related text, e.g., substantially the entirety of claimed subject matter, but does not disclose “wherein the mesa isolation region comprises a two-step mesa structure”.
Soloviev discloses in FIG. 4 and related text, e.g., “wherein the mesa isolation region (62/64/66 comprise a mesa) comprises a two-step mesa structure (as described in par. 40; the mesa can be one step as in FIG. 4, or it can be two step)”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Mochizuki with “wherein the mesa isolation region comprises a two-step mesa structure” as taught by Soloviev, in order to lower the electrical field in that immediate area (par. 40), and since Soloviev teaches the equivalence of single step mesa and two-step mesa for the purposes of lowering the electrical field in that immediate area (par. 40), and since merely a change in shape is known to be within the skills of POSITA (MPEP 2144.04).
Examiner’s Note: the use of “two step mesa” structures for its effects on electric field and related concepts affected by electric field (such as leakage current and capacitance) is pretty well known. Here are some examples: US-2007/0249109, par. 54 (also, 2 other references by same author), US-2011/0317956, par. 20 (and 1 other reference by same author). Keep in mind that this was a search for exact key words (“two step mesa”) without looking for any synonyms.
Regarding claim 6, the combined device of Mochizuki and Soloviev disclose in cited figures and related text, e.g., wherein a first step of the mesa isolation region has a lower surface formed within the first P+ layer (top layer of “J2” p-n diode, taught by Mochizuki, marked as “p”), and wherein a second step of the mesa isolation region has a lower surface formed within the N-layer (bottom layer of “J2” p-n diode, taught by Mochizuki, marked as “n”; since the diode of Mochizuki has two layers, the two steps have to be in those two layers, by definition; thus meeting limitations; to put it in other words, the Soloviev’s one step, shown in FIG. 4, is present in bottom layer 62, which is of first conductivity type; the second step, by definition, has to be in layer 64 or 66, which are both second conductivity type; hence, Soloviev’s two steps would be in a p-layer and n-layer; hence, when his teachings are applied to Mochizuki, his two steps have to be in the same layers; thus meeting limitations).
Regarding claim 13, the combined device of Mochizuki and Soloviev disclose in cited figures and related text, e.g., wherein the mesa isolation region comprises a two-step mesa structure (see claim 5).
Regarding claim 14, the combined device of Mochizuki and Soloviev disclose in cited figures and related text, e.g., wherein a first step of the mesa isolation region has a lower surface formed within the first P+ layer, and wherein a second step of the mesa isolation region has a lower surface formed within the N- layer (see claim 6).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/22/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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