DETAILED ACTION
This correspondence is in response to the communications received 01/28/2026. Claims 1-12 have been canceled. Claims 13-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 13-20 in the reply filed on 01/28/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/28/2024 has been considered by the examiner and made of record in the application file.
Specification
Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. The abstract of the instant application includes the phrase “Embodiments of this disclosure provide a method of manufacturing a semiconductor structure”. This phrase can be implied from the title, therefore the phrase should be removed or amended so as to not repeat the information given in the title.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 requires “wherein the first air gap comprises a first space and a second space, and the first space is disposed between a vertical portion of the first nitride layer and the first air gap in a vertical direction”. It is unclear how the first air gap comprises a first space that is disposed between the first nitride layer and the first airgap itself. For the purposes of examination, this limitation as best understood based on paragraph [0050] of the instant specification, will be interpretated as “wherein the first air gap comprises a first space and a second space, and the first space is disposed between a vertical portion of the first nitride layer and each of the plurality of the bit line structures”.
Claim 14 requires “the first space is disposed between a vertical portion of the first nitride layer and the first air gap in a vertical direction”. It is unclear how the first space is disposed between a vertical portion of an element in a vertical direction. Based on the depiction of “a first space SP1” ([0050]) in Fig. 7, the limitation will be interpretated as “the first space is disposed between a vertical portion of the first nitride layer and the first air gap in a lateral direction” for the purposes of examination.
Claim 14 requires “the second space is disposed between a lateral portion of the first nitride layer and the first barrier layer in a lateral direction”. It is unclear how the second space is disposed between a lateral portion of an element in a lateral direction. Based on the depiction of “a second space SP2” ([0050]) in Fig. 7, the limitation will be interpretated as “the second space is disposed between a lateral portion of the first nitride layer and the first barrier layer in a vertical direction” for the purposes of examination.
The term “associated” in claims 15 and 17 is a broad term which renders the claims indefinite. The term “associated” is not defined by the claims, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. Due to the term "associated" it
Claim 16 requires “the third space is disposed between a vertical portion of the first nitride layer and the second nitride layer in a vertical direction”. It is unclear how the third space is disposed between a vertical portion of an element in a vertical direction. Based on the depiction of “a third space SP3” ([0051]) in Fig. 7, the limitation will be interpretated as “the third space is disposed between a vertical portion of the first nitride layer and the second nitride layer in a lateral direction” for the purposes of examination.
Claim 16 requires “the fourth space is disposed between the second nitride layer and a lateral portion of the first nitride layer in a lateral direction”. It is unclear how the second space is disposed between a lateral portion of an element in a lateral direction. Based on the depiction of “a fourth space SP4” ([0051]) in Fig. 7, the limitation will be interpretated as “the fourth space is disposed between the second nitride layer and a lateral portion of the first nitride layer in a vertical direction” for the purposes of examination.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 13, a semiconductor structure, comprising:
a substrate (102), comprising a plurality of active areas (110) and a plurality of insulation areas (120) between the active areas (see Fig. 7);
a first barrier layer (130), disposed on the substrate (see Fig. 7);
a plurality of bit line structures (140), disposed on the first barrier layer and protruding from the substrate (see Fig. 7);
a spacer (150), disposed surrounding a sidewall of each of the plurality of bit line structures (see Fig. 7), wherein the spacer comprises a first air gap (152A), a first nitride layer (154), a second air gap (156A) and a second nitride layer (158) arranged outward in sequence from each of the bit line structures (see Fig. 7); and
a plurality of landing pads (LP), disposed over the plurality of bit line structures with the spacer (see Fig. 17).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230144120 A1, published 05/11/2023) in view of Lee et al. (US 20230225111 A1, published 07/13/2023).
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Regarding claim 1, Figs. 1-9 of Chen disclose a semiconductor structure (“semiconductor memory device 100”, [0028]), comprising:
a substrate (“substrate 110”, [0029]), comprising a plurality of active areas (“plurality of active areas (AA) 103”, [0029]) and a plurality of insulation areas (“at least one isolating region 101”, [0029], where “The formation of the isolating region is for example accomplished by firstly etching the substrate 110 to form a plurality of trenches (not shown in the drawing), and then filling the trenches with an insulating material”, [0029]) between the active areas (as seen in Fig. 9, 101 is between 103);
a first barrier layer (“barrier layer 163”, [0029]), disposed on the substrate (as seen in Fig. 9, 163 is on 110);
a plurality of bit line structures (“plurality of bit lines 160”, [0030], where “each of the bit lines 160 for example includes a semiconductor layer 161, a barrier layer 163, a metal layer 165, and a capping layer 167 stacked from bottom to top”, [0030], and “after the etching process P1 is performed, only the metal layer 165, the barrier layer 163 and the semiconductor layer 161 are remained to form each bit line 260”, [0033]), disposed on the first barrier layer (as seen in Fig. 9, 167 and 165 are disposed on 163) and protruding from the substrate (“A portion of the bit lines 160 is further extended into the substrate 110 through the bottom thereof, to serve as a bit line contact (BLCs) 160a”, [0030]);
a spacer (“spacer structure 170”, [0034]), disposed surrounding a sidewall of each of the plurality of bit line structures (as seen in Fig. 9, 170 surrounds a sidewall of each of 260), wherein the spacer comprises a first air gap (the instances of “first air gap layer 171b”, [0034], denoted “AG1” in Fig. 9 are a first air gap), a first nitride layer (the instances of “spacer 173”, [0034], denoted “SP1” in Fig. 9 are a first layer, however, Chen discloses “the forming process of the first spacer 173 is carried out by entirely depositing a silicon oxide material layer … followed by performing another etching back process, to partially remove the silicon oxide material layer to form the first spacer 173”, [0031], therefore a secondary reference will be used to teach the first nitride layer below), a second air gap (the instances of “second air gap layer 175b”, [0034], denoted “AG2” are a second air gap) and a second nitride layer (the instances of “spacer 173”, [0034], denoted “SP2” in Fig. 9 are a second layer, which will likewise be combined with a secondary reference below to form a second nitride layer) arranged outward in sequence from each of the bit line structures (as seen in Fig. 9, AG1, SP1, AG2, and SP2 are arranged outward in sequence from each of 260); and
a plurality of landing pads (“plurality of storage node pads (SN pads) 181”, [0032]), disposed over the plurality of bit line structures with the spacer (as seen in Fig. 9, 181 is disposed over 260 and 170).
Chen fails to disclose “a first nitride layer and a second nitride layer”.
However, in a similar field of endeavor, Figs. 1-7 of Lee teach a first nitride layer and a second nitride layer (“The spacer structure 140 may include, but is not limited to, insulating materials, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and combinations thereof”, [0046], thus both SP1 and SP2 which were disclosed by Chen to include silicon oxide, could be made of silicon nitride, silicon oxynitride, or silicon oxycarbonitride).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first nitride layer and a second nitride layer” as taught by Lee in the system of Chen for the purpose of tuning the etch rate of the spacer material.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230144120 A1, published 05/11/2023) in view of Lee et al. (US 20230225111 A1, published 07/13/2023) in view of Ahn et al. (US 11,226,552 B2, published 01/18/2022).
Regarding claim 18, Figs. 1-9 of Chen in combination with Figs. 1-7 of Lee disclose the semiconductor structure according to claim 13, Figs. 1-9 of Chen further disclose wherein each of the plurality of bit line structures comprises:
a bottom cap layer (“dielectric layer 130”, [0030], where “dielectric layer 130 preferably includes a multilayer structure, for example including an oxide layer 131-nitride layer 133-oxide layer 135 (oxide-nitride-oxide, ONO) structure, but is not limited thereto”, [0030], Chen does not specify that 130 is a cap layer, however, as seen in Fig. 9, 130 caps the bottom of 260, further a secondary ref will be used below to relate a cap layer and a dielectric layer), disposed over the substrate (as seen in Fig. 9, 130 is disposed over 110);
a conductive layer (“metal layer 165”, [0165], metal is known in the art as conductive), disposed on the bottom cap layer (as seen in Fig. 9, 165 is disposed on 130); and
a top cap layer (“insulating layer 185”, [0034], Chen does not specify that 185 is a cap layer, however, as seen in Fig. 9, 185 caps the top of 260, further a secondary ref will be used below to relate a cap layer and an insulating layer), disposed on the conductive layer (as seen in Fig. 9, 185 is disposed on 165).
Chen in combination with Lee does not specify “a bottom cap layer, and a top cap layer”.
However, in a similar field of endeavor, Figs. 16A-16D of Ahn teach a bottom cap layer, and a top cap layer (“an insulating capping layer for covering the insulator patterns 112 and 114 and the direct contact conductive layer and forming a bit-line structure 140, a first metal-based conductive layer, a second metal-based conductive layer, and the insulating capping layer are etched to form a plurality of bit-lines 147, including a first metal-based conductive pattern 145 and a second metal-based conductive pattern 146 that are linear, and a plurality of insulating capping lines 148”, col. 17, lines 61-67, and col. 18, lines 1-2, thus 130 and 185 of Chen which are also formed of insulating materials are both cap layers).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a bottom cap layer, and a top cap layer” as taught by Ahn in the system of Chen in combination with Lee for the purpose of protecting the bit line structure during processing and preventing electrical leakage.
Regarding claim 19, Figs. 1-9 of Chen in combination with Figs. 1-7 of Lee and Figs. 16A-16D of Ahn disclose the semiconductor structure according to claim 13, Figs. 1-9 of Chen further disclose wherein the bottom cap layer has a first height (Merriam-Webster defines height as “the part that rises or extends upward the greatest distance : the highest part” or “the extent of elevation above a level”, therefore 130 has a first height defined as the distance from the bottom surface of 110 to the top surface of 130 as seen in Fig. 9), the conductive layer has a second height (165 has a second height defined as the distance from the bottom surface of 110 to the top surface of 165 as seen in Fig. 9), and the top cap layer has a third height (185 has a third height defined as the distance from the bottom surface of 110 to the top surface of 130 as seen in Fig. 9), and
the third height is greater than the second height (as seen in Fig. 9, the distance from the bottom of 110 to the top of 185 is greater than the distance from the bottom of 110 to the top of 165), and the second height is greater than the first height (as seen in Fig. 9, the distance from the bottom of 110 to the top of 165 is greater than the distance from the bottom of 110 to the top of 130).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 20230144120 A1, published 05/11/2023) in view of Lee et al. (US 20230225111 A1, published 07/13/2023) in view of Wang et al. (US 10,937,884 B1, published 03/02/2021).
Regarding claim 20, Figs. 1-9 of Chen in combination with Figs. 1-7 of Lee disclose the semiconductor structure according to claim 13, Figs. 1-9 of Chen further disclose further comprising:
a sealing layer (“capacitor dielectric layer 213”, [0036], where “capacitor dielectric layer 213 for example includes a high dielectric constant dielectric material which is selected from the group consisting of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), zinc oxide (ZrO2), titanium oxide (TiO2) and zirconia-alumina-zirconia (ZAZ), and preferably includes zirconia-alumina-zirconia. The top electrode layer 215 for example includes a low resistance metal material such as aluminum, titanium, copper or tungsten, and preferably includes titanium, but not limited thereto”, [0036], Chen does not specify that 213 is a sealing layer, however a secondary reference will be used to teach this limitation below), disposed on the landing pads and the spacer (as seen in Fig. 9, 213 is disposed on 181 and 170).
Chen in combination with Lee fails to disclose “a sealing layer”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 2P of Wang teaches a sealing layer (“For example, the insulating sealing layer 170 is made of Si, SiO, SiN, SiC, SiCN, SiOC, SiON, SiCN, SiOCN, ZrO, HfO2, AlO, AlON, or a high-k material or another applicable dielectric material”, thus as 170 of Wang and 213 of Chen can be formed of the same material, 213 of Chen is also a sealing layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a sealing layer” as taught by Wang in the system of Chen in combination with Lee for the purpose of preventing electrical leakage between adjacent conductive elements.
Allowable Subject Matter
Claims 14-17 would be allowable if rewritten to overcome the rejections under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the semiconductor structure as recited in the claims of the instant application.
Regarding claim 14, the prior art of Chen et al. (US 20230144120 A1) in combination with Lee et al. (US 20230225111 A1) discloses a similar semiconductor structure but fails to disclose the specific claims of the instant application regarding the second space in relation to the first nitride layer and the first barrier layer e.g. “wherein the first air gap comprises a first space and a second space, and … the second space is disposed between a lateral portion of the first nitride layer and the first barrier layer in a lateral direction”.
Claim 15 would be allowable by virtue of its dependence on claim 14.
Regarding claim 16, the prior art of Chen et al. (US 20230144120 A1) in combination with Lee et al. (US 20230225111 A1) discloses a similar semiconductor structure but fails to disclose the specific claims of the instant application regarding the fourth space in relation to the second nitride layer and the first nitride layer e.g. “wherein the second air gap comprises a third space and a fourth space, and …the fourth space is disposed between the second nitride layer and a lateral portion of the first nitride layer in a lateral direction”.
Claim 17 would be allowable by virtue of its dependence on claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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