DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-10, 13-14, and 16-18 are rejected under 35 U.S.C. 102 as being anticipated by You et al.; US 2022/0216097 A1; 10/2021
Regarding claim 1, You teaches a method of manufacturing a semiconductor device, comprising: providing a substrate ( Fig. 3A #100 ) having an array area ( Fig. 3A #101) and a periphery area ( Fig. 3A #102 ); forming an etch stop layer on a top surface of the substrate in the array area and the periphery area ( [0045] At step S22, the upper surface of the substrate #100 is etched by adopting a dry etching process or a wet etching process based on the first graphical mask layer, so as to obtain the trench structure #12 ); forming a patterned mask layer on a top surface of the etch stop layer in the array area and the periphery area ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ), wherein the patterned mask layer has a plurality of hollowed portions ( a mask used for the formation of trenches in a semiconductor device would inherently be patterned and contain physical openings which can be considered hollow ), and wherein the patterned mask layer includes oxide ( [0052] the formed first graphical mask layer can include a hard mask layer, the hard mask layer can be a single-layer structure or a multi-layer stacking structure, and the material of the hard mask layer can be silicon oxide ); forming a plurality of trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101 ) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0037] At step S2, a substrate is provided, and a trench structure is formed in the substrate ), wherein the trenches run through the etch stop layer and are recessed from the top surface of the substrate ( as shown in Fig. 3B ); removing the patterned mask layer ( [0052] the graphical photoetching glue layer is removed after etching the substrate #100 ); and depositing an oxide layer to fill the trenches by a deposition process ( [0054] a first dielectric material layer #131 is formed, and the first dielectric layer #131 covers the side wall and bottom of the trench structure #12 as well as the upper surface of the substrate #100; [0077] The first dielectric material layer #131 can include, but not limited to, a silicon oxide layer ).
Regarding claim 2, You teaches the method of claim 1 ( as discussed above), wherein depositing the oxide layer is performed such that the oxide layer fully fills the trenches ( Fig. 2H ).
Regarding claim 3, You teaches the method of claim 1 ( as discussed above), wherein removing the patterned mask layer ( Fig. 1: S2 ) is performed before depositing the oxide layer ( Fig. 1: S4 ).
Regarding claim 5, You teaches the method of claim 1 ( as discussed above), wherein forming the patterned mask layer ( [0044] At step S211, a first mask layer is formed on the upper surface of the substrate ) is performed before depositing the oxide layer ( [0054] At step S42, a first dielectric material layer #131 is formed ).
Regarding claim 6, You teaches the method of claim 1 ( as discussed above), wherein depositing the oxide layer is performed such that a top surface of the oxide layer and the top surface of the etch stop layer are coplanar ( [0040] The protective layer covers and protects a top side wall of the trench structure ).
Regarding claim 7, You teaches the method of claim 1 ( as discussed above), further comprising removing a portion of the oxide layer by a planarization process ( [0070] The upper surface of the substrate #100 can be set in order to perform the chemical mechanical polishing process for a stopping layer, and then the protective material layer #141 and the second dielectric material layer #151 that are located on the surface of the substrate #100 and the trench structure #12 are removed ).
Regarding claim 8, You teaches the method of claim 7 ( as discussed above), wherein removing the portion of the oxide layer is performed such that a top surface of the oxide layer and the top surface of the etch stop layer are coplanar ( [0070] the upper surface of the substrate #100 is flattened ).
Regarding claim 9, You teaches the method of claim 1 ( as discussed above), wherein forming the trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ) is performed such that an aspect ratio of the trenches in the array area and an aspect ratio of the trenches in the periphery area are different ( as shown in Fig. 3B ).
Regarding claim 10, You teaches the method of claim 1 ( as discussed above), wherein forming the trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101 ) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ) is performed such that an aspect ratio of a depth to a width of the trenches in the array area is greater ( [0073] the depth of the first trench structure #121 is less than the depth of the second trench structure #122 and the width of the third trench structure #123 is less than the width of the fourth trench structure #124 ) than an aspect ratio of a depth to a width of the trenches in the periphery area ( [0073] both are identical to the width of the second trench structure #122 ).
Regarding claim 13, You teaches a method of manufacturing a semiconductor device, comprising: providing a substrate ( Fig. 3A #100 ) having an array area ( Fig. 3A #101) and a periphery area ( Fig. 3A #102 ); forming an etch stop layer on a top surface of the substrate in the array area and the periphery area ( [0045] At step S22, the upper surface of the substrate #100 is etched by adopting a dry etching process or a wet etching process based on the first graphical mask layer, so as to obtain the trench structure #12 ); forming a patterned mask layer on a top surface of the etch stop layer in the array area and the periphery area ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ), wherein the patterned mask layer has a plurality of hollowed portions ( a mask used for the formation of trenches in a semiconductor device would inherently be patterned and contain physical openings which can be considered hollow ), and wherein the patterned mask layer includes oxide ( [0052] the formed first graphical mask layer can include a hard mask layer, the hard mask layer can be a single-layer structure or a multi-layer stacking structure, and the material of the hard mask layer can be silicon oxide ); forming a plurality of trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101 ) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0037] At step S2, a substrate is provided, and a trench structure is formed in the substrate ), wherein the trenches run through the etch stop layer and are recessed from the top surface of the substrate ( as shown in Fig. 3B ); removing the patterned mask layer ( [0052] the graphical photoetching glue layer is removed after etching the substrate #100 ); overfilling the trenches by depositing an oxide layer ( Fig. 2G ) ; and removing a portion of the oxide layer by a planarization process ( Fig. 2H ), such that a top surface of the oxide layer and the top surface of the etch stop layer are coplanar ( as shown in Fig. 2H ).
Regarding claim 14, You teaches the method of claim 13 ( as discussed above), wherein removing the patterned mask layer ( Fig. 1: S2 ) is performed before depositing the oxide layer ( Fig. 1: S4 ).
Regarding claim 16, You teaches the method of claim 13 ( as discussed above), wherein forming the patterned mask layer ( [0044] At step S211, a first mask layer is formed on the upper surface of the substrate ) is performed before depositing the oxide layer ( [0054] At step S42, a first dielectric material layer #131 is formed ).
Regarding claim 17, You teaches the method of claim 13 ( as discussed above), wherein forming the trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ) is performed such that an aspect ratio of the trenches in the array area and an aspect ratio of the trenches in the periphery area are different ( as shown in Fig. 3B ).
Regarding claim 18, You teaches the method of claim 13 ( as discussed above), wherein forming the trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101 ) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ) is performed such that an aspect ratio of a depth to a width of the trenches in the array area is greater ( [0073] the depth of the first trench structure #121 is less than the depth of the second trench structure #122 and the width of the third trench structure #123 is less than the width of the fourth trench structure #124 ) than an aspect ratio of a depth to a width of the trenches in the periphery area ( [0073] both are identical to the width of the second trench structure #122 ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 15 are rejected under U.S.C. 103 as being unpatentable over You et al.; US 2022/0216097 A1; 10/2021 in view of Sun et al.; US 7,364,832 B2; 06/2004
Claim 4: You discloses the method of claim 1 ( as discussed above).
You does not appear to disclose the patterned mask layer has a thickness in a range between 30 nm and 150 nm.
However, Sun teaches the patterned mask layer has a thickness in a range between 30 nm and 150 nm ( Col. 3 Lines 58 – 63 Referring to Fig. 1a, a photosensitive and anti-reflective hard mask or protective layer #10 is spin coated onto the substrate #12 at a thickness from about 20-150 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sun with You to implement the patterned mask layer has a thickness in a range between 30 nm and 150 nm because this balances high-resolution imaging with sufficient physical protection during etching.
Claim 15: You discloses the method of claim 13 ( as discussed above).
You does not appear to disclose the patterned mask layer has a thickness in a range between 30 nm and 150 nm.
However, Sun teaches the patterned mask layer has a thickness in a range between 30 nm and 150 nm ( Col. 3 Lines 58 – 63 Referring to Fig. 1a, a photosensitive and anti-reflective hard mask or protective layer #10 is spin coated onto the substrate #12 at a thickness from about 20-150 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Sun with You to implement the patterned mask layer has a thickness in a range between 30 nm and 150 nm because this balances high-resolution imaging with sufficient physical protection during etching.
Claims 11, 12, and 19 are rejected under U.S.C. 103 as being unpatentable over You et al.; US 2022/0216097 A1; 10/2021 in view of Lee et al.; US 8,614,126 B1; 08/2012
Claim 11: You discloses the method of claim 1 ( as discussed above).
You does not appear to disclose the etch stop layer has a thickness in a range between 15 nm and 50 nm.
However, Lee (126) teaches the etch stop layer has a thickness in a range between 15 nm and 50 nm ( Col. 4 lines 58 – 59 The etch stop is typically thin, such as 10-70 nm, such as 20 – 50 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with You to implement the etch stop layer has a thickness in a range between 15 nm and 50 nm because this layer must be thick enough to resist the “over-etch” phase of the primary etching process.
Claim 12: You discloses the method of claim 1 ( as discussed above).
You does not appear to disclose the etch stop layer comprises nitride.
However, Lee (126) teaches the etch stop layer comprises nitride ( Col. 4 line 66 – Col. 5 Etching with the first non-selective etch is then stopped and the slit trenches #110 are filled with a sacrificial etch stop material #110A. The slit trenches 110 may be filled with any suitable material 110A such as stoichiometric or non-stoichiometric, AlO.sub.x, AlN, AlON, SiC, SiCN, TiN and/or TiO.sub.x ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with You to implement the etch stop layer comprises nitride because of the unique chemical and physical properties that ensure process reliability.
Claim 19: You discloses the method of claim 13 ( as discussed above).
You does not appear to disclose the etch stop layer has a thickness in a range between 15 nm and 50 nm.
However, Lee (126) teaches the etch stop layer has a thickness in a range between 15 nm and 50 nm ( Col. 4 lines 58 – 59 The etch stop is typically thin, such as 10-70 nm, such as 20 – 50 nm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee (126) with You to implement the etch stop layer has a thickness in a range between 15 nm and 50 nm because this layer must be thick enough to resist the “over-etch” phase of the primary etching process.
Claim 20 is rejected under U.S.C. 103 as being unpatentable over You et al.; US 2022/0216097 A1; 10/2021 in view of Lee et al.; US 8,252,192 B2; 03/2009
Claim 20: You discloses the method of claim 13 ( as discussed above), wherein forming the trenches on the top surface of the etch stop layer in the array area ( Fig. 3B trench structures #121 and #122 are in the array area #101 ) and the periphery area ( Fig. 3B trench structures #123 and #124 are in the peripheral area #102 ) through the hollowed portions of the patterned mask layer ( [0048] At step S211, a first mask layer is formed on the upper surface of the substrate #100 ).
You does not appear to disclose the pattern mask layer is removed simultaneously.
However, Lee (192) teaches the pattern mask layer is removed simultaneously ( Col. 7 lines 50 – 55 By removing the third mask layer #122 while completing the transfer of pattern #130 to the underlying thin film #110 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee (192) with You to implement the pattern mask layer is removed simultaneously because this reduces over-etching damage and simplifies the process.
Response to Arguments
Applicant's arguments filed 03/23/26 have been fully considered but they are not persuasive.
On page 4 of the remarks, applicant argues that in claim 1 and 13 the “mask layer” of You is mapped to the “patterned mask layer” and the “etch stop layer” of the application. The rejection cites step S22 where the upper surface of the substrate #100 is etched based on the first graphical mask layer to address the feature “forming an etch stop layer on a top surface of the substrate in the array area and the periphery area.” Further, the rejection cites step S211 where a first mask layer is formed on the upper surface of the substrate to address the feature “forming a patterned mask layer on a top surface of the etch stop layer in the array area and the periphery area.” You addresses the features of the independent claims 1 and 13 with regard to the etching process and the use of etch stop layers in the process of etching and patterned mask layers.
On page 5 of the remarks, applicant argues that claims 4 and 15 rejected by Sun and claims 11, 12, and 19 rejected by Lee ‘126 as well as claim 20 rejected by Lee `192 are traverses due to the arguments above for You. These arguments are overcome in the by You as discussed above.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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