DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments to claims 1 and 11 have been fully considered. Based on the cited prior arts Yang, Wang, and Lin and new grounds of rejection from Kim (US20080217685A1) the claims 1, 3-12, 14-22 are rejected.
Response to Amendment
Applicant’s amendments to the claims 6, 15, and 17 have been fully
considered and resolve the claim objections. The claim objections have been
withdrawn. Applicant’s amendments to the specification has been fully considered
and resolve the specification objection. The specification objection has been
withdrawn. Applicant’s cancellation of claim 2 and 13 has been acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 – 12, 18 - 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US20160141359A1; hereinafter Yang) in view of Wang et al. (US20190157421A1; Wang), further in view Kim (US20080217685A1; hereinafter Kim).
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Kim: FIG. 5C
Regarding Claim 1 (Currently amended), Yang discloses a semiconductor device (semiconductor structure [0008]) comprising:
a first oxide layer (18) disposed on a substrate (10), FIG. 5, [0018], [0019]; and
a gate structure disposed on the first oxide layer (18), wherein the gate structure comprises a gate (30), the first oxide layer (18) comprises an exposed segment not covered by the gate structure, (a width W1 of the gate electrode 30 may be smaller than the width W2 of the silicon oxide layer 18, FIG. 5 reproduced above, [0022]).
Yang does not disclose “wherein the gate structure comprises a spacer surrounding the gate; a thickness of the first oxide layer right below the gate is fixed, and the thickness of the first oxide layer right below the gate is greater than a thickness of the exposed segment.”
In a similar art, Wang discloses a transistor with dual spacers [0006].
Wang discloses: a first oxide layer (120b) disposed on a substrate (110) and a gate structure (M2) disposed on the first oxide layer (120b), FIG. 10 reproduced above, [0028].
wherein the gate structure comprises a gate (M2) and a spacer surrounding the gate (142b and 152b), the first oxide layer (120b) comprises an exposed segment (K4) not covered by the gate structure, FIG. 10, [0017], [0028].
a first light doped drain region (lightly doped drain 144b on the left of M2) and a second light doped drain region (lightly doped drain 144b on the right of M2) respectively located at two sides of the gate structure (M2), FIG. 10, [0017]).
a thickness of the first oxide layer (120b) right below the gate is fixed (thickness t5) and the thickness of the first oxide layer right below the gate (thickness t5) is greater than a thickness of the exposed segment (thickness t6 of fourth part K4 of 120b), (a thickness t5 of the third part K3 is larger than a thickness t6 of the fourth part K4, FIG. 10, [0028]).
Wang discloses that a device as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s device, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
The combination of Yang and Wang does not disclose “wherein a portion of the first light doped drain region and a portion of the second light doped drain region are located right below the gate.”
In a similar art, Kim discloses a semiconductor device [0006].
Kim discloses: wherein a portion of the first light doped drain region (LDD region 112) and a portion of the second light doped drain region (LDD region 112) are located right below the gate (gate electrode 106), FIG. 5C reproduced above, [0038].
Kim discloses that a device as taught can minimize short channel effects and hot carrier effects and reduce the overall manufacturing costs [0056]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yang and Wang’s device, in order to minimize short channel effects and hot carrier effects and the overall manufacturing costs as disclosed by Kim [0056].
Regarding Claim 4 (Currently amended), The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 1.
Wang discloses: further comprising: a source region (source/drain 166 on the left of M2) and a drain region (source/drain 166 on the right side of M2) respectively located at the two sides of the gate structure (M2), and the drain region is adjacent to the exposed segment (source/drain 166 on the right side of M2 is adjacent to exposed segment K4), FIG. 10, [0023], [0028].
Wang discloses that a device as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 5, The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 4.
Wang discloses: wherein a portion of the drain region (source/drain 166 on the right side of M2) is located below the exposed segment (K4) and is aligned with an outer edge of the gate structure (M2 with spacers 142b and 152b), FIG. 10, [0028].
Wang discloses that a device as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 6 (Currently amended), The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 4.
Wang discloses: wherein the first light doped drain region (144b on the left side of M2) surrounds the source region (source/drain 166 on the left side of M2), and the second light doped drain region (144b on the right side of M2) surrounds the drain region (source/drain 166 on the right side of M2), FIG. 10, [0028].
Wang discloses that a device as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 7, The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 1.
Wang [0009] discloses forming transistors with spacers to adjust the distance between the source/drain and the gate; and [0029] discloses the gate dielectric layer can have multi partial thicknesses through the etchings of spacers, indicating the spacer width and the exposed segment of the oxide layer can be varied and a ratio of a width of the exposed segment to a width of a sidewall of the spacer can be greater than or equal to 2.
Wang discloses that a device as taught avoids high electric field occurring between the source/drain and the gate and improves the electrical performance of the semiconductor device [0009]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0009].
Regarding Claim 8, The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 1.
Yang discloses: further comprising: two bird's beak structures respectively extending integrally from two sides (two bird’s beak structures extending laterally from both edges of 18) of the first oxide layer (18), and the two bird's beak structures do not overlap with the gate (30) in a vertical direction, FIG. 5, [0018], [0022].
Regarding Claim 9, The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 8.
The combination of Yang and Wang discloses: wherein one of the bird's beak structures (Yang: bird’s beak on the left edge of 18, FIG. 5, [0018]) is located below a sidewall of the spacer (Wang: 142b and 152b on the left side of M2, FIG. 10, [0028]), and another one of the bird's beak structures (Yang: bird’s beak on the right edge of 18, FIG. 8, [0025]) is located outside another sidewall of the spacer (Wang: 142b and 152b on the right side of M2).
Wang discloses that a device as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the device, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 10, The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 1.
Yang discloses: wherein a side of the first oxide layer (side of 18 with 34/134) away from the exposed segment (segment of 18 with bird’s beak exposed on the right side of 36) is aligned with a side surface of the gate (left sidewall of gate 36), FIG. 8, [0025].
Regarding Claim 11 (Currently amended), Yang discloses a method for fabricating a semiconductor device (fabricating method of a semiconductor structure, [0009]), comprising:
performing a thermal oxidation process to form an oxide layer (18) on a substrate (10) FIG. 2A, [0018].
wherein the oxide layer (18) comprises a first oxide layer (118) and a second oxide layer (thin oxide layer 134), and a thickness of the first oxide layer (118) is greater than a thickness of the second oxide layer (thin oxide layer 134), FIG. 8, [0025];
forming a gate structure (136) on the oxide layer (18), FIG. 8, [0025].
the gate structure (136) partially covers the first oxide layer (118), so that the first oxide layer (118) comprises an exposed segment not covered by the gate structure (the gate electrode 136 only partly covers the silicon oxide layer 118, FIG. 8, [0025]);
Yang does not disclose “performing a first ion implantation process to form a first light doped drain region and a second light doped drain region separated from each other in the substrate; wherein the gate structure comprises a gate and a spacer surrounding the gate; and removing a portion of the exposed segment, so that a thickness of the exposed segment is less than a thickness of a portion of the first oxide layer other than the exposed segment.”
In a similar art, Wang discloses a transistor with dual spacers and a method of forming the transistor [0011].
Wang discloses: performing a first ion implantation process to form a first light doped drain region (lightly doped drain 144b on the left of M2)) and a second light doped drain region (lightly doped drain 144b on the right of M2) separated from each other in the substrate (110), FIG. 10, [0017].
wherein the oxide layer comprises a first oxide layer (120b) and a second oxide layer (fourth part K4), and a thickness of the first oxide layer (t5) is greater than a thickness of the second oxide layer (t6), FIG. 10, [0028].
forming a gate structure (M2 with spacers 142b and 152b) on the oxide layer (120b), wherein the gate structure comprises a gate (M2) and a spacer surrounding the gate (142b and 152b), FIG. 10, [0017], [0028].
and the gate structure partially covers the first oxide layer (120b), so that the first oxide layer comprises an exposed segment not covered by the gate structure (fourth part K4), FIG. 10, [0028]; and
removing a portion of the exposed segment (fourth part K4), so that a thickness of the exposed segment (t6) is less than a thickness of a portion of the first oxide layer (t5) other than the exposed segment, FIG. 10, [0022], [0028].
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
The combination of Yang and Wang does not disclose “wherein a portion of the first light doped drain region and a portion of the second light doped drain region are located right below the gate.”
In a similar art, Kim discloses a semiconductor device [0006].
Kim discloses: wherein a portion of the first light doped drain region (LDD region 112) and a portion of the second light doped drain region (LDD region 112) are located right below the gate (gate electrode 106), FIG. 5C reproduced above, [0038].
Kim discloses that a device as taught can minimize short channel effects and hot carrier effects and reduce the overall manufacturing costs [0056]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yang and Wang’s device, in order to minimize short channel effects and hot carrier effects and the overall manufacturing costs as disclosed by Kim [0056].
Regarding Claim 12, The combination of Yang, Wang, and Kim discloses the method of claim 11.
Yang discloses: before performing the thermal oxidation process, the method further comprising:
forming a patterned material layer (the first masks 12 may have multiple layers which include a silicon nitride layer 14 and a pad oxide 16) on the substrate (10), FIG. 1, [0017].
wherein the patterned material layer (silicon nitride layer 14 and a pad oxide 16) has an opening region (space S1, FIG. 1, [0017]), the first oxide layer (118) corresponds to the opening region (S1), FIG. 7, [0017].
Yang does not disclose “and the second oxide layer is formed by oxidizing the patterned material layer.”
Wang discloses: the second oxide layer (K2/K4) is formed by oxidizing the patterned material layer, FIG. 6, [0022].
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 18 (Currently amended), The combination of Yang, Wang, and Kim discloses the method of claim 11.
Yang discloses forming the gate (36) on the oxide layer (18), FIG. 5, [0022], but does not disclose “forming the spacer surrounding the gate.”
Wang discloses: wherein forming the gate structure on the oxide layer (120b) comprises: forming the gate (M2) on the oxide layer (120b); and forming the spacer (142b and 152b) surrounding the gate (M2), FIG. 10, [0017], [0028].
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 19, The combination of Yang, Wang, and Kim discloses the method of claim 18.
Wang [0009] discloses forming transistors with spacers to adjust the distance between the source/drain and the gate; and [0029] discloses the gate dielectric layer can have multi partial thicknesses through the etchings of spacers, indicating the spacer width and the exposed segment of the oxide layer can be varied and a ratio of a width of the exposed segment to a width of a sidewall of the spacer can be greater than or equal to 2.
Wang discloses that a method as taught avoids high electric field occurring between the source/drain and the gate and improves the electrical performance of the semiconductor device [0009]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0009].
Regarding Claim 20, The combination of Yang, Wang, and Kim discloses the method of claim 18.
Yang discloses: wherein the oxide layer (18) further comprises two bird's beak structures respectively extending integrally from two sides (two bird’s beak structures extending laterally from both edges of 18) of the first oxide layer (18), and the two bird's beak structures do not overlap with the gate (30) in a vertical direction, FIG. 5, [0018], [0022].
Regarding Claim 21, The combination of Yang, Wang, and Kim discloses the method of claim 20.
The combination of Yang and Wang discloses: wherein one of the bird's beak structures (Yang: bird’s beak on the left edge of 18, FIG. 5, [0018]) is located below a sidewall of the spacer (Wang: 142b and 152b on the left side of M2, FIG. 10, [0028]), and another one of the bird's beak structures (Yang: bird’s beak on the right edge of 18, FIG. 8, [0025]) is located outside another sidewall of the spacer (Wang: 142b and 152b on the right side of M2).
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 22, The combination of Yang, Wang, and Kim discloses the method of claim 18.
Yang discloses: wherein a side of the first oxide layer (side of 18 with 34/134) away from the exposed segment (segment of 18 with bird’s beak exposed on the right side of 36) is aligned with a side surface of the gate (left sidewall of gate 36), FIG. 8, [0025].
Claims 3, 14, 15, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Wang, further in view of Kim, still further in view of Lin et al. (US20220384608A1; hereinafter Lin).
Regarding Claim 3 (Currently amended), The combination of Yang, Wang, and Kim discloses the semiconductor device of claim 1.
Yang discloses an exposed segment of the first oxide layer 18, but does not disclose “wherein the second light doped drain region is located below the exposed segment, and a width of the second light doped drain region is greater than a width of the first light doped drain region.”
Wang discloses: wherein the second light doped drain region (lightly doped drain 144b on the right of M2) is located below the exposed segment (fourth part K4 of 120b), FIG. 10, [0017].
The combination of Yang, Wang, and Kim does not disclose “a width of the second light doped drain region is greater than a width of the first light doped drain region.”
In a similar art, Lin discloses a semiconductor device and a method of forming the same [0002].
Lin discloses: a width of the second light doped drain region (width W2 of 124) is greater than a width of the first light doped drain region (width W1 of 123), FIG. 1H, [0062].
Lin discloses that a device as taught increases the breakdown voltage and improves electrical performance of the semiconductor device [0019]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yang, Wang, and Kim’s device, in order to provide a semiconductor device with increased breakdown voltage and improved electrical performance as disclosed by Lin [0019].
Regarding Claim 14 (Currently amended), The combination of Yang, Wang, and Kim discloses the method of claim 12.
Yang discloses the exposed segment of the first oxide layer 18, but does not disclose “wherein the second light doped drain region is located below the exposed segment, and a width of the second light doped drain region is greater than a width of the first light doped drain region.”
Wang discloses: wherein the second light doped drain region (lightly doped drain 144b on the right of M2) is located below the exposed segment (fourth part K4 of 120b), FIG. 10, [0017].
The combination of Yang, Wang, and Kim does not disclose “a width of the second light doped drain region is greater than a width of the first light doped drain region.”
Lin discloses: a width of the second light doped drain region (width W2 of 124) is greater than a width of the first light doped drain region (width W1 of 123), FIG. 1H, [0062].
Lin discloses that a method as taught increases the breakdown voltage and improves electrical performance of the semiconductor device [0019]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify Yang, Wang, and Kim’s method, in order to provide a semiconductor device with increased breakdown voltage and improved electrical performance as disclosed by Lin [0019].
Regarding Claim 15 (Currently amended), The combination of Yang, Wang, Kim, and Lin disclose the method of claim 14.
Wang discloses: further comprising: removing the second oxide layer (fourth part K4), FIG. 10, [0028]; and
performing a second ion implantation process to form a source region
and a drain region in the substrate (ion implantation process is performed to form a source/drain 166 in the substrate 110, [0023]) corresponding to the regions where the second oxide layer (fourth part K4) is originally disposed, wherein the drain region (source/drain 166) is adjacent to the exposed segment (fourth part K4), FIG. 10, [0028].
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 16, The combination of Yang, Wang, Kim, and Lin discloses the method of claim 15.
Wang discloses: wherein a portion of the drain region (source/drain 166 on the right side of M2) is located below the exposed segment (K4) and is aligned with an outer edge of the gate structure (M2 with spacers 142b and 152b), FIG. 10, [0028].
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Regarding Claim 17 (Currently amended), The combination of Yang, Wang, Kim, and Lin disclose the method of claim 15.
Wang discloses: wherein the first light doped drain region (144b on the left side of M2) surrounds the source region (source/drain 166 on the left side of M2), and the second light doped drain region (144b on the right side of M2) surrounds the drain region (source/drain 166 on the right side of M2), FIG. 10, [0028].
Wang discloses that a method as taught improves the electrical performance of the semiconductor device [0029]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to modify the method, in order to provide a semiconductor device with improved electrical performance as disclosed by Wang [0029].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Krishna J Palaniswamy/
Examiner, Art Unit 2899
/Brent A. Fairbanks/Supervisory Patent Examiner, Art Unit 2899
Prosecution Insights