DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 11-19 and 20-25 in the reply filed on 02/03/2026 is acknowledged.
Claims 1-10 has been canceled.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-12, 14, 20-23 and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Velez et al [US 2018/0061775].
With respect to claim 11, Velez et al (fig. 2) disclose a system, comprising:
a chip-sized package (200, pp [0023]) mounted to a printed circuit board (100, pp [0023]);
wherein the chip-sized package comprises:
a primary integrated circuit die (202, pp [0024]) having a back face connected to the printed circuit board (100, pp [0023]);
cavities (221, pp [0029]) formed in the back face of the primary integrated circuit die to define pillars extending outwardly from a planar portion of the primary integrated circuit die; and
pads (220, pp [0029]) formed on distal ends of the pillars;
wherein the pads on the distal ends of the pillars are connected to corresponding pads on the printed circuit board by surface mount solder (222, pp [0029]).
With respect to claim 12, Velez et al (fig. 2) disclose wherein the chip-sized package includes a secondary integrated circuit die (206, 208, pp [0024]) mounted to a front face of the primary integrated circuit die (202, pp [0024]) via solder balls (260, 280, pp [0026]) between corresponding pads (204, pp [0024]) of the secondary integrated circuit die and the primary integrated circuit die.
With respect to claim 14, Velez et al (fig. 2) disclose wherein a distal end of one of the pillars defined by the cavities (221, pp [0029]) has a thermal pad (220, pp [0024]); and wherein the thermal pad is connected to a corresponding pad on the printed circuit board (100, pp [0023]) by surface mount solder (222, pp [0029]).
With respect to claim 20, Velez et al (fig. 2) disclose a system, comprising:
a printed circuit board (PCB) (100, pp [0023]) having pads on a front face thereof; and
a chip-sized package (200, pp [0023]) mounted to the printed circuit board (100, pp [0023]), the chip-sized package comprises:
a primary integrated circuit die (202, pp [0024]) having:
a planar portion with an active area formed therein;
a back face facing the printed circuit board (100, pp [0023]), the pillars being defined by cavities (221, pp [0029]) formed in the back face of the primary integrated circuit die (202, pp [0024]);
pads (220, pp [0024]) formed on distal ends of the pillars; and
surface-mount solder joints connecting the pads on the distal ends of the pillars to the pads of the printed circuit board (100, pp [0023]);
wherein the cavities and the printed circuit board (100, pp [0023]) form open chambers that allow the primary integrated circuit die (202, pp [0024]) to flex relative to
the printed circuit board to reduce mechanical stress transmitted to the active area of the primary integrated circuit die.
With respect to claim 21, Velez et al (fig. 2) disclose a secondary integrated circuit die (206, 208, pp [0024]) mounted to a front face of the primary integrated circuit die (202, pp [0024]), wherein solder balls (260, 280, pp [0026]) connect pads (204, pp [0024]) of the primary integrated circuit die to pads of the secondary integrated circuit die.
With respect to claim 22, Velez et al (fig. 2) disclose wherein one of the pillars includes a thermal pad (220, pp [0024]) at a distal end, and the thermal pad is surface-mount soldered to a corresponding pad on the printed circuit board (100, pp [0023]).
With respect to claim 23, Velez et al (fig. 2) disclose wherein one of the pillars is centrally located on the primary integrated circuit die (206, 208, pp [0024]) and carries the thermal pad.
With respect to claim 25, Velez et al (fig. 2) disclose wherein the chip-sized package (200, pp [0023]) lacks a secondary integrated circuit die.
Allowable Subject Matter
Claims 16-19 are allowed.
Claims 13, 15 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record fails to disclose wherein the primary integrated circuit die has through- silicon vias extending from a back face of pads formed in a front face of the primary integrated circuit die to corresponding ones of the pads on the distal end of the pillars (claim 13); wherein the primary integrated circuit die has through- silicon vias extending from a back face of pads formed in a front face of the primary integrated circuit die to corresponding ones of the pads on the distal end of the pillars; wherein one of the pillars defined by the cavities has a thermal pad on its distal end, with this pillar lacking a through-silicon via extending therethrough; and wherein the thermal pad is connected to a corresponding pad on the printed circuit board by surface mount solder (claim 15); wherein at least one of the pillars has vias extending therethrough to electrically connect certain ones of the pads on the front face to other pads formed on distal ends of the pillars; a thermal pad located on a back face of the primary silicon die on the distal end of the centrally located pillar; and cavities formed at the back face of the primary die, the cavities forming open chambers in combination with a printed circuit board when the primary die is mounted on the printed circuit board (claim 16); wherein through-silicon vias extend through at least one of the pillars to electrically connect pads on the front face of the primary integrated circuit die to the pads on the distal ends of the pillars (claim 24).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOAI V PHAM whose telephone number is (571)272-1715. The examiner can normally be reached M-F 8:30a.m-10:00p.m.
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/HOAI V PHAM/Primary Examiner, Art Unit 2892