DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/18/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
Figures 1-2 & 4-5 (it noted that these figures which disclosed in the BACKGROUND) should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14 & 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Boutaud et al. (US 5,072,219 A).
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Regarding claim 14, Boutaud et al. discloses in Fig. 1 a measurement system, comprising:
first and second capacitances (capacitors 26 and 27);
a switching circuit (switches 29-1 to 29-6) having
a first terminal (annotated TA1) coupled to a reference voltage (GND, ground reference),
a second terminal (annotated TA2) coupled to a first voltage (annotated Potential V1) greater than the reference voltage (ground reference), and
a third terminal (annotated TA3) coupled to a second voltage (annotated Potential V2) greater than the reference voltage (ground reference);
the switching circuit (switches 29-1 to 29-6) receiving first and second control signals (PHI1 and PHI2), and configured to couple first terminals of the first and second capacitances (TC1 and TC2) to different ones of the reference, first, and second voltages depending on the first and second control signals, such that:
in response to the first control signal (PHI1) being asserted while the second control signal (PHI2) is deasserted, couple the first terminal of the first capacitance to the first voltage and couple the first terminal of the second capacitance to the second voltage;
in response to the first control signal (PHI1) being deasserted while the second control signal (PHI2) is asserted, couple the first terminals of the first and second capacitances to the reference voltage (ground reference); and
in response to the first and second control signals (PHI1 and PHI2) being deasserted, decouple the first terminals of the first and second capacitances from the first, second, and reference voltages; and
a measurement circuit (annotated MEAS1 which includes amplifier 25) configured to monitor resulting currents flowing through the first and second capacitances (capacitances 26 and 27), with these currents being indicative of capacitance values of the first and second capacitances.
Regarding claim 15, Boutaud et al. discloses in Fig. 1, the measurement system of claim 14, wherein the reference voltage is ground (GND).
Allowable Subject Matter
Claims 1-13 & 20-29 are allowed.
The following is an examiner’s statement of reasons for allowance:
The most relevant prior art reference of Boutaud et al. does not teach: in regards to Claim 1, “a differential integrator comprising: a differential operational amplifier having an inverting input connected to a second terminal of said first capacitance and a non-inverting input connected to a second terminal of said second capacitance; a first integration capacitance having a first terminal connected to said inverting input of said differential operational amplifier and a second terminal connected via a first electronic switch to a positive output terminal of said differential operational amplifier; a first output node of said differential integrator connected to said second terminal of said first integration capacitance; a second integration capacitance having a first terminal connected to said non-inverting input of said differential operational amplifier and a second terminal connected via a second electronic switch to a negative output terminal of said differential operational amplifier; a second output node of said differential integrator connected to said second terminal of said second integration capacitance; a third electronic switch connected between said inverting input of said differential operational amplifier and said positive output terminal of said differential operational amplifier; and a fourth electronic switch connected between said non-inverting input of said differential operational amplifier and said negative output terminal of said differential operational amplifier; and a comparator with hysteresis configured, in response to a voltage applied to a negative input terminal of said comparator exceeding a voltage applied to a positive input terminal of said comparator plus a hysteresis threshold, to set a first output terminal of said comparator to high and a second output terminal of said comparator to low, wherein said comparator comprises: a fifth electronic switch connected between said negative input terminal of said comparator and said second output terminal of said comparator; a sixth electronic switch connected between said positive input terminal of said comparator and said first output terminal of said comparator; a first decoupling capacitance connected between the negative input terminal of said comparator and said first output node of said differential integrator; and a second decoupling capacitance connected between the positive input terminal of said comparator and said second output node of said differential integrator; the control circuit further configured to: during a normal operation phase: close said first electronic switch and said second electronic switch by asserting said second control signal, and open said first electronic switch and said second electronic switch by de-asserting said second control signal; close said third electronic switch and said fourth electronic switch by asserting said first control signal, and open said third electronic switch and said fourth electronic switch by de-asserting said first control signal; open said fifth electronic switch and said sixth electronic switch; and monitor a reset request signal indicating a reset request and start a reset phase in response to determining that said reset request signal indicates a reset request; and during said reset phase: for a first reset interval, close said first electronic switch, second electronic switch, third electronic switch, fourth electronic switch, fifth electronic switch and sixth electronic switch; and for a second reset interval, open said third electronic switch and said fourth electronic switch and maintain said first electronic switch, second electronic switch, fifth electronic switch, and sixth electronic switch as being closed, and then start said normal operation phase again”. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 2-13 have also been determined to be novel and non-obvious.
The most relevant prior art reference of Boutaud et al. does not teach: in regards to Claim 20, “a comparator with hysteresis configured, in response to a voltage applied to a negative input terminal of said comparator exceeding a voltage applied to a positive input terminal of said comparator plus a hysteresis threshold, to set a first output terminal of said comparator to high and a second output terminal of said comparator to low, wherein said comparator comprises: a fifth electronic switch connected between said negative input of said comparator and said second output terminal of said comparator; and a sixth electronic switch connected between said positive input of said comparator with hysteresis and said first output terminal of said comparator; and a first decoupling capacitance connected between the negative input of said comparator and said first output node of said differential integrator, and a second decoupling capacitance connected between the positive input of said comparator and said second output node of said differential integrator”. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 21-29 have also been determined to be novel and non-obvious.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The most relevant prior art reference of Boutaud et al. does not teach: in regards to Claim 16, wherein the first and second voltages are equal to a voltage generated by a voltage generator. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious
The most relevant prior art reference of Boutaud et al. does not teach: in regards to Claim 17, a differential operational amplifier having an inverting input connected to a second terminal of the first capacitance and a non-inverting input connected to a second terminal of the second capacitance; a differential comparator having an inverting input coupled to the inverting input of the differential operational amplifier through a first decoupling capacitor connected in series with a first integration capacitor, a non-inverting input coupled to the non-inverting input of the differential operational amplifier through a second decoupling capacitor connected in series with a second integration capacitor; a first switch connected between a first tap and a non-inverting output of the differential operational amplifier, the first tap being between the first decoupling capacitor and first integration capacitor, the first switch controlled based upon the second control signal; a second switch connected between a second tap and an inverting output of the differential operational amplifier, the second tap being between the second decoupling capacitor and second integration capacitor, the second switch controlled based upon the second control signal; and a processing circuit having a first input coupled to the first output of the differential comparator, a second input coupled to the second output of the differential comparator, and an output, the processing circuit configured to determine capacitance values of the first and second capacitances. Therefore, the applicant’s claimed invention has been determined to be novel and non-obvious. By virtue of dependency from claims 18-19 have also been determined to be novel and non-obvious.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843