Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Amendment filed on 4/2/26 has been entered.
Response to Arguments
Applicant’s arguments have been fully considered but they are moot because the arguments do not apply to any of the references being used in the current rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5, 7 and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hikida (US 20120168869) in view of Hsiao (US 10008573).
Regarding claim 1. Fig 13 (4) of Hikida discloses A middle voltage transistor structure (this feature is an intended use of the applicant's device and not limiting feature of the claim, and the claim does not recite what a range of ‘middle voltage’ is. Because the structure of the claimed device is the same as the Hikida’s device, the claimed invention does not distinguish over the Hikida’s device), comprising:
a substrate 1;
a shallow trench isolation (STI) 2 [0075] disposed in the substrate;
a gate structure 9A/6 disposed on the substrate;
a source lightly doped region 7 (left) [0079] and a drain lightly doped region 7 (right) [0079] embedded within the substrate at two sides of the gate structure (left and right sides);
a conductive structure 9C/6 contacting the drain lightly doped region;
a first spacer 11 (the 11 surrounding 9A) surrounding the gate structure; and
a second spacer 11 (the 11 surrounding 9C) surrounding the conductive structure;
wherein the first spacer contacts the second spacer (refer to each 11 between 9A and 9C).
But Hikida does not disclose a conductive structure contacting the STI.
Fig 1 of Hsiao discloses a conductive structure (S1) contacting the drain lightly doped region 12A and the STI 13A.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the Hsiao’s structure to the Hikida’s device for the purpose of providing improved breakdown voltage, reducing on-resistance, and enhancing reliability because of reduced the peak electric field near the drain-gate edge.
Regarding claim 5. Hikida in view of Hsiao discloses The middle voltage transistor structure of claim 1, Hikida discloses wherein a top surface of the gate structure is aligned with a top surface of the conductive structure (Fig 13(4)).
Regarding claim 7. Hikida in view of Hsiao discloses The middle voltage transistor structure of claim 1, Hsiao wherein the second spacer 16 (the 16 right side of 14A) contacts the drain lightly doped region 12A.
Regarding claim 16. Hikida discloses A fabricating method of a middle voltage transistor structure (this feature is an intended use of the applicant's method and not limiting feature of the claim, and the claim does not recite what a range of ‘middle voltage’ is. Because the structure of the claimed method is the same as the Hikida’s method, the claimed invention does not distinguish over the Hikida’s method), comprising:
providing a substrate 1 with a shallow trench isolation (STI) 2 disposed therein (Fig 2(a));
forming a source lightly doped region 7 (left) and a drain lightly doped region 7 (right) embedded in the substrate (Fig 2(c));
forming a middle voltage dielectric layer 6 [0059]: silicon oxide) disposed between the source lightly doped region and the drain lightly doped region (Fig 2 (c);
simultaneously forming a first polysilicon layer 9A [0066] and a second polysilicon layer 9C [0066] (Fig 3(e)),
wherein the first polysilicon layer overlaps the middle voltage dielectric layer, and the second polysilicon layer covers part of the drain lightly doped region (Fig 3(e)); and
forming a first spacer 11 (around 9A) and a second spacer 11 (around 9C) (Fig 3(f)),
wherein the first spacer surrounds the first polysilicon layer and the middle voltage dielectric layer, the second spacer surrounds the second polysilicon layer, and the first spacer contacts the second spacer (Fig 3(f)).
But Hikida does not disclose the second polysilicon layer covers part of the STI.
Fig 1 of Hsiao discloses a conductive structure (S1) contacting the drain lightly doped region 12A and the STI 13A.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the Hsiao’s method to the Hikida’s method for the purpose of providing improved breakdown voltage, reducing on-resistance, and enhancing reliability because of reduced the peak electric field near the drain-gate edge.
Regarding claim 17. Hikida in view of Hsiao discloses The fabricating method of a middle voltage transistor structure of claim 16, Hikida discloses further comprising:
performing an ion implantation process to form a source doped region 12 (left) within the source lightly doped region by taking the first polysilicon layer, the second polysilicon layer, the first spacer and the second spacer as a mask (Fig 4(g) – Fig 4(h), [0094]); and
performing a silicide process to transform part of the first polysilicon layer into a first silicide 13 (in 9A), part of the second polysilicon layer into a second silicide 13 (in 9C) and part of the source doped region into a third silicide 13 (in right 12) (Fig 3(g), [0071]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Hikida (US 20120168869) in view of Hsiao (US 10008573), and further in view of Lin (US 20180277677).
Regarding claim 2. Hikida in view of Hsiao discloses The middle voltage transistor structure of claim 1, Hikida discloses wherein the gate structure comprises a middle voltage dielectric layer ([0059]: 6 is ‘silicon oxide’ which is a middle voltage dielectric layer), a first polysilicon layer (Fig 13(4), [0069]: in the 9A) and a first silicide 13 (Fig 13(4), [0061]: the 13 on 9A) disposed on the substrate from bottom to top,
the conductive structure comprises a second polysilicon layer (Fig 13(4), [0069]: in the 9B) and a second silicide 13 (Fig 13(4), [0061]: the 13 on 9B) disposed on the substrate from bottom to top.
But Hikida in view of Hsiao does not disclose the second polysilicon layer contacts the drain lightly doped region.
However, Fig 5 of Lin discloses the second polysilicon layer 120A [0023] contacts the drain lightly doped region 101B.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the Hikida in view of Hsiao’s device structure to have the Lin’s contact structure for the purpose of providing enhanced off-state leakage current and on-resistance characteristics of the MOSFET [0018].
Allowable Subject Matter
Claims 8 and 10-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the conductive structure covers the shallow trench isolation and covers one of the four corners; and a first spacer surrounding the gate structure and a second spacer surrounding the conductive structure, wherein the first spacer contacts the second spacer”.
Claims 3-4, 6 and 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “the gate structure comprises a middle voltage dielectric layer, a first polysilicon layer and a first silicide disposed on the substrate from bottom to top, the conductive structure comprises a low voltage dielectric layer, a second polysilicon layer and a second silicide disposed on the substrate from bottom to top, and the low voltage dielectric layer contacts the drain lightly doped region”.
Regarding claim 6. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “a source doped region disposed in the source lightly doped region, no drain doped region is disposed in the drain lightly doped region”.
Regarding claim 18. the cited prior art of record does not teach or fairly suggest, along with the other claimed features, “after forming the middle voltage dielectric layer and before forming the second polysilicon layer, forming a low voltage dielectric layer covering the drain lightly doped region, the low voltage dielectric layer overlaps the second polysilicon layer”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 8A-4P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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