Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
Claims 1-20 pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-8 and 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over KR 2021/0122938 A Kim et al (herein “Kim”) in view of US 2021/0036029 A1 Park et al (herein “Park”).
Regarding Claim 1, Kim discloses:
A display panel (see generally Fig. 1) comprising:
a light-emitting element (#LED); and
a pixel circuit (see region #DA that contains transistors #TR1 and #TR2) electrically connected to the light-emitting element (#LED), the pixel circuit (#DA) including:
a first transistor (#TR2) including a first semiconductor pattern (#130) including a first source region (#131), a first drain region (#133), and a first channel region (#132) disposed between the first source region (#131) and the first drain region (#133), and a first gate electrode (#GE2) disposed on the first semiconductor pattern (#130) and overlapping the first channel region (#132);
a first insulation layer (#141) disposed between the first semiconductor pattern (#130) and the first gate electrode (#GE2) and overlapping the first channel region (#132);
a second insulation layer (#161) disposed on the first gate electrode (#GE2) and covering the first transistor (#TR2);
a second transistor (#TR1) disposed on the second insulation layer (#161) and including a second semiconductor pattern (#135) including a second source region (#136), a second drain region (#138), and a second channel region (#137) disposed between the second source region (#136) and the second drain region (#138), and a second gate electrode (#GE1) disposed on the second semiconductor pattern (#135) and overlapping the second channel region (#138); and
a third insulation layer (#143) disposed between the second semiconductor pattern (#135) and the second gate electrode (#GE1) and overlapping the first transistor (#TR1) in a plan view,
wherein the first semiconductor pattern (#135) includes a metal oxide semiconductor material (see Espacenet translation of KR 2021/0122938 A Kim et al paragraph [0048]: “The first semiconductor (135) may include an oxide semiconductor.”).
Kim does not explicitly disclose:
wherein the first semiconductor pattern and the second semiconductor pattern each include a metal oxide semiconductor material.
However, in analogous art, Park teaches:
See Fig. 7.
wherein the first semiconductor pattern (first semiconductor layer comprises active layer #350, see paragraph [0107]) and the second semiconductor pattern (second semiconductor layer comprises active layer #450, see paragraph [0107]) each include a metal oxide semiconductor material (see abstract, see paragraphs [0107]-[0108]).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Park to the device disclosed by Kim and include a metal oxide material like, for example, indium-tin oxide (ITO), indium-gallium-tin oxide (ITGO), indium-gallium-zinc oxide (IGZO) or indium-gallium-zinc-tin oxide (IGZTO). Doing so would be a simple substitution of one known semiconductor material for another, in this case substituting in an oxide semiconductor. Additionally, doing so may simplify the manufacturing process, as the same material could be used for both semiconductor layers, like the embodiment shown in Park Fig. 7.
Regarding Claim 2, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein a charge carrier in the first semiconductor pattern (#130) has a first mobility and a charge carrier in the second semiconductor pattern (#135) has a second mobility, wherein the first mobility is lower than the second mobility.
See generally paragraph [0072]-[0073] of Espacenet translation of KR 2021/0122938 A Kim et al:
“[0072]During the manufacturing process of the display device, after forming the third opening (OP3) and the fourth opening (OP4) overlapping the source region (131) and the drain region (133) of the second transistor (TR2), in the process of doping impurities and annealing, hydrogen may move through the insulating layers disposed adjacent to the first semiconductor (135) and the second semiconductor (130), for example, the first gate insulating film (141), the second gate insulating film (142), the first interlayer insulating film (161), the third gate insulating film (143), and the second interlayer insulating film (162), and leak out through the transmission portion (OP) of the transmission area (TA), which is the edge of the insulating layers (141, 142, 161, 143, 162).
[0073] In this way, when hydrogen flows out from the first semiconductor (135) and the second semiconductor (130), the hydrogen concentration of the first semiconductor (135) decreases, the dopant decreases, the carrier decreases, and thereby the on-state current of the first transistor (TR1) may decrease. Additionally, the driving range of the second semiconductor (130) may change and the on-state current may also decrease. In this way, when hydrogen flows out from the first semiconductor (135) and the second semiconductor (130), the characteristics of the first transistor (TR1) and the second transistor (TR2) may change.”
Additionally, see MPEP 2144.05 (II)(B); the carrier mobility directly affects the current through the cited first and second semiconductor patterns, and is therefore considered a result effective variable that may be optimized by the person of ordinary skill in the art. In this case, the person of ordinary skill may adjust carrier mobility to achieve application specific results, i.e. adjusting for a targeted current.
Regarding Claim 3, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein the first transistor (#TR2) and the second transistor (#TR1) are spaced apart along a first direction (horizontal direction with respect to Fig. 1), and the third insulation layer (#143) is extended in the first direction (horizontal direction with respect to Fig. 1).
Regarding Claim 4, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein the third insulation layer (#143) overlaps each of the second source region (#136), the second drain region (#138), and the second channel region (#137).
Regarding Claim 5, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein the third insulation layer (#143) comprises:
a first insulation portion (portion of #143 extending left and right from the second semiconductor pattern #135) disposed on the second insulation layer (#161); and
a second insulation portion (portion of #143 directly on second semiconductor pattern #135) disposed on the second semiconductor pattern (#135).
Regarding Claim 6, Kim in view of Park discloses: the display panel of claim 5.
Kim further discloses:
wherein the third insulation layer (#143) contacts a side surface (see Fig. 1) of the second semiconductor pattern (#135).
Regarding Claim 7, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein: the first transistor (#TR2) is a driving transistor (see paragraph [0062] of Espacenet translation of KR 2021/0122938 A Kim et al); and the second transistor (#TR1) is a switching transistor (see paragraph [0062] of Espacenet translation of KR 2021/0122938 A Kim et al).
Regarding Claim 8, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein the pixel circuit (#DA) further comprises a fourth insulation layer (#162) disposed on the second gate electrode (#GE1) and covering the second transistor (#TR1).
Regarding Claim 10, Kim in view of Park discloses: the display panel of claim 1.
Kim further discloses:
wherein: the first insulation layer (#141) overlaps each of the first channel region (#132), the first source region (#131), and the first drain region (#133); and
the first gate electrode (#GE2) overlaps the first channel region (#132).
For the purposes of examination, the phrase “overlaps” is interpreted as overlapping from a top-down view.
Regarding Claim 11, Kim in view of Park discloses: the display panel of claim 1.
Kim in view of Park does not explicitly disclose:
wherein the first transistor further comprises a first conductive pattern disposed below the first semiconductor pattern, wherein the pixel circuit further comprises a buffer layer disposed on the first conductive pattern.
However, in analogous art, Park further teaches:
See Fig 7 and paragraphs [0109]-[0112].
wherein the first transistor (driving transistor #DRT, see paragraph [0109]) further comprises a first conductive pattern (#360) disposed below the first semiconductor pattern (#350), wherein the pixel circuit (#DA) further comprises a buffer layer (#120) disposed on the first conductive pattern (#360).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Park to the device disclosed by Kim in view of Park and include a conductive pattern below the semiconductor pattern. Doing so would provide the device with a light blocking layer, which may assist in preventing light being incident on first active layer 350 from the first substrate 110 to thereby preventing leakage current flowing in the first active layer 350. Additionally, the inclusion of a buffer layer may protect the driving transistor DRT and the first switching transistor SCT of the pixel PX from moisture permeating through the first substrate 110. See paragraphs [0109]-[0112].
Regarding Claim 12, Kim in view of Park discloses: the display panel of claim 1.
Kim in view of Park does not explicitly disclose:
wherein the pixel circuit further comprises a first capacitor including a first hold electrode and a second hold electrode, wherein:
the second hold electrode is disposed in a same layer as a layer on which the first semiconductor pattern is disposed; and
the first hold electrode is disposed in a same layer as a layer on which the first gate electrode is disposed.
However, in analogous art, Park further teaches:
See Fig. 10 and paragraphs [0000]-[0000].
wherein the pixel circuit (#DA) further comprises a first capacitor (#CST, includes #710 and #720) including a first hold electrode (#720) and a second hold electrode (#710), wherein:
the second hold electrode (#710) is disposed in a same layer (#160) as a layer on which the first semiconductor pattern (#350) is disposed; and
the first hold electrode (#720) is disposed in a same layer (#180) as a layer on which the first gate electrode (#310) is disposed.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Park to the device disclosed by Kim in view of Park and include a capacitor to the pixel circuit, in order to store or hold input charge for later use within the device. Additionally, doing so may retain the data voltage that may be applied to the gate electrode of the driving transistor constant.
For the purposes of examination, the term “on” as used in lines 4 and 6 of the claim is being interpreted as in contact with. Thus, the layer the first hold electrode is disposed is in contact with the layer the first gate electrode is disposed in.
Regarding Claim 13, Kim in view of Park discloses: the display panel of claim 12.
Park further teaches:
wherein the first insulation layer (#160) is disposed between the first hold electrode (#720) and the second hold electrode (#710).
Regarding Claim 14, Kim in view of Park discloses: the display panel of claim 11.
Kim in view of Park does not explicitly disclose:
wherein the pixel circuit further comprises a second capacitor including a first storage electrode and a second storage electrode, wherein: the first storage electrode is disposed in a same layer as a layer on which the first conductive pattern is disposed; and the second storage electrode is disposed in a same layer as a layer on which the first semiconductor pattern is disposed.
However, in analogous art, Park further teaches:
wherein the pixel circuit (#DA) further comprises a second capacitor (#CST, includes #710 and #720) including a first storage electrode (#720) and a second storage electrode (#710), wherein:
the first storage electrode (#710) is disposed in a same layer (#160) as a layer on which the first conductive pattern (#360) is disposed; and
the second storage electrode (#720) is disposed in a same layer (#180) as a layer on which the first semiconductor pattern (#350) is disposed.
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Park to the device disclosed by Kim in view of Park and include a capacitor to the pixel circuit, in order to store or hold input charge for later use within the device. Additionally, doing so may retain the data voltage that may be applied to the gate electrode of the driving transistor constant.
For the purposes of examination, the term “on” as used in lines 4 and 6 of the claim is being interpreted as in contact with. Thus, the layer the first hold electrode is disposed is in contact with the layer the first gate electrode is disposed in.
Regarding Claim 15, Kim in view of Park discloses: the display panel of claim 14.
wherein the buffer layer (#160) is disposed between the first storage electrode (#720) and the second storage electrode (#710).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over KR 2021/0122938 A Kim et al in view of US 2021/0036029 A1 Park et al and further in view of US 2022/0109037 A1 Yuan et al (herein “Yuan”).
Regarding Claim 9, Kim in view of Park discloses: the display panel of claim 8.
Kim in view of Park does not explicitly disclose:
wherein a hydrogen content of the fourth insulation layer is higher than a hydrogen content of the third insulation layer.
However, in analogous art, Yuan teaches:
See Fig. 1 and paragraph [0032]: “The concentration of the first insulating layer 70 in the first area 701 is set to be higher than the concentration of the first insulating layer 70 in the second area 702 so that the hydrogen content in the film layer of the first transistor 20 can be reduced, thereby avoiding the reduction of subthreshold swing caused by hydrogen provided for the LTPS layer when the hydrogen concentration is large. In the specific implementation, the dehydrogenation treatment may be performed on the first insulating layer 70 of the second transistor in part or the whole AA area. After the dehydrogenation treatment, the hydrogen concentration of the first insulating layer 70 in the second area 702 decreases while the hydrogen concentration in the first area 701 remains.”
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Yuan to the device disclosed by Kim in view of Park and form the insulating layers such that the hydrogen concentration is higher in the fourth insulation layer than in the third insulation layer. As taught by Yuan, by changing the hydrogen concentration above each respective transistor, specifically in regions 701, 702, and 703 in Fig. 1, the subthreshold swing can be adjusted depending on the chosen hydrogen concentration. Additionally, see MPEP 2144.05 (II)(B); the hydrogen concentration directly affects the subthreshold swing of the cited dielectric layers, and is therefore considered a result effective variable that may be optimized by the person of ordinary skill in the art.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over KR 2021/0122938 A Kim et al in view of US 2021/0036029 A1 Park et al and further in view of US 2022/0302239 A1 Kim (herein “Kim2”).
Regarding Claim 16, Kim in view of Park discloses: the display panel of claim 1
Kim in view of Park does not explicitly disclose:
wherein the second transistor further comprises a metal oxide pattern disposed below the second semiconductor pattern, wherein the metal oxide pattern includes a first pattern portion overlapping the second source region and a second pattern portion overlapping the second drain region.
However, in analogous art, Kim2 teaches:
See Fig. 5. See also paragraphs [0061] and [0070]. The source/drain regions are not explicitly assigned an element number, however paragraph [0061] discloses “the driving transistor 260 may include a first active layer 140, a first gate electrode 180, a first source electrode, and a first drain electrode.” Fig. 5 shows the metal oxide light blocking layer (see paragraph [0070]) #530 overlaps the entire transistor structure, which therefore reads on the claimed subject matter below.
wherein the second transistor further comprises a metal oxide pattern (metal oxide light blocking layer #530) disposed below the second semiconductor pattern (#260), wherein the metal oxide pattern (#530) includes a first pattern portion (see note above) overlapping the second source region (see note above) and a second pattern portion (see note above) overlapping the second drain region (see note above).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kim2 to the device disclosed by Kim in view of Park and include a metal oxide light blocking layer below the second semiconductor pattern to assist in device performance and help prevent excess light from interacting with the second semiconductor pattern. Additionally, doing so would prevent leakage current flowing in the first active layer of the second semiconductor pattern.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over KR 2021/0122938 A Kim et al in view of US 2022/0302239 A1 Kim (Kim2) and further in view of US 2022/0109037 A1 Yuan et al.
Regarding Claim 20, Kim discloses:
A display panel (see generally Fig. 1) comprising:
a light-emitting element (#LED); and
a pixel circuit (see region #DA that contains transistors #TR1 and #TR2) electrically connected to the light-emitting element (#LED), the pixel circuit (#DA) including:
a metal oxide transistor (#TR2) including a metal oxide semiconductor pattern (#130) including a source region (#131), a drain region (#133), and a channel region (#132) disposed between the source region (#131) and the drain region (#133), and a gate electrode (#GE2) disposed on the metal oxide semiconductor pattern (#130) and overlapping the channel region (#132);
a gate insulation portion (#141) disposed between the metal oxide semiconductor pattern (#130) and the gate electrode (#GE2) and overlapping the source region (#131), the drain region (#133), and the channel region (#132), and in contact with a side surface of the metal oxide semiconductor pattern (#130);
an upper insulation portion (#161) disposed on the gate insulation portion (#143) and the gate electrode (#GE2);
Kim does not explicitly disclose:
a metal oxide pattern disposed below the metal oxide semiconductor pattern, and including a first pattern portion overlapping the source region and a second pattern portion overlapping the drain region; and
wherein a hydrogen content of the gate insulation portion is lower than a hydrogen content of the upper insulation portion.
However, in analogous art, Kim2 teaches:
See Fig. 5. See also paragraphs [0061] and [0070]. The source/drain regions are not explicitly assigned an element number, however paragraph [0061] discloses “the driving transistor 260 may include a first active layer 140, a first gate electrode 180, a first source electrode, and a first drain electrode.” Fig. 5 shows the metal oxide light blocking layer (see paragraph [0070]) #530 overlaps the entire transistor structure, which therefore reads on the claimed subject matter below.
wherein the second transistor further comprises a metal oxide pattern (metal oxide light blocking layer #530) disposed below the second semiconductor pattern (#260), wherein the metal oxide pattern (#530) includes a first pattern portion (see note above) overlapping the second source region (see note above) and a second pattern portion (see note above) overlapping the second drain region (see note above).
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Kim2 to the device disclosed by Kim and include a metal oxide light blocking layer below the second semiconductor pattern to assist in device performance and help prevent excess light from interacting with the second semiconductor pattern. Additionally, doing so would prevent leakage current flowing in the first active layer of the second semiconductor pattern.
Kim in view of Kim2 does not explicitly disclose:
wherein a hydrogen content of the gate insulation portion is lower than a hydrogen content of the upper insulation portion.
Additionally, in analogous art, Yuan teaches:
See Fig. 1 and paragraph [0032]: “The concentration of the first insulating layer 70 in the first area 701 is set to be higher than the concentration of the first insulating layer 70 in the second area 702 so that the hydrogen content in the film layer of the first transistor 20 can be reduced, thereby avoiding the reduction of subthreshold swing caused by hydrogen provided for the LTPS layer when the hydrogen concentration is large. In the specific implementation, the dehydrogenation treatment may be performed on the first insulating layer 70 of the second transistor in part or the whole AA area. After the dehydrogenation treatment, the hydrogen concentration of the first insulating layer 70 in the second area 702 decreases while the hydrogen concentration in the first area 701 remains.”
Therefore, it would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention to consider combining the teachings of Yuan to the device disclosed by Kim in view of Park and form the insulating layers such that the hydrogen concentration is higher in the fourth insulation layer than in the third insulation layer. As taught by Yuan, by changing the hydrogen concentration above each respective transistor, specifically in regions 701, 702, and 703 in Fig. 1, the subthreshold swing can be adjusted depending on the chosen hydrogen concentration. Additionally, see MPEP 2144.05 (II)(B); the hydrogen concentration directly affects the subthreshold swing of the cited dielectric layers, and is therefore considered a result effective variable that may be optimized by the person of ordinary skill in the art.
Allowable Subject Matter
Claims 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 17: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “wherein the metal oxide pattern does not overlap the second channel region.”
Regarding Claim 18: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “wherein: the first pattern portion and the second pattern portion are spaced apart in the plan view; and the first insulation layer is disposed between the first pattern portion and the second pattern portion.”
Regarding Claim 19: The following is a statement of reasons for the indication of allowable subject matter: The prior art of record as considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitation, in combination with the remaining claimed limitations. The prior art fails to teach or suggest the claimed limitations, namely: “wherein: the metal oxide pattern is disposed in a same layer as a layer on which the first semiconductor pattern is disposed, and a material included in the metal oxide pattern is identical to a material included in the first semiconductor pattern.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Andrew V. Prostor whose telephone number is (571) 272-2686. The examiner can normally be reached M-F 8:00a-4:30p.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ANDREW VICTOR PROSTOR/Examiner, Art Unit 2812
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812