DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on February 05th, 2025, has been entered.
Upon entrance of the Amendment, claim 1 was amended. Claims 1-15 are currently pending.
Response to Arguments
Applicant's arguments filed on February 05th, 2025 with respect to the rejection of claim 8 have been fully considered but they are not persuasive.
The Applicant has argued “Ponoth fails to disclose that a bottom surface of the first gate electrode between the first fin-shaped structure and the second fin-shaped structure is higher than a bottom surface of the first gate electrode adjacent to the first fin-shaped structure, as recited in the claim 8 of the present invention. Instead, the bottom surface of the first gate electrode (265) between the first fin-shaped structure (212) and the second fin-shaped structure (213) is clearly even with the bottom surface of the first gate electrode adjacent to the first fin-shaped structure in the same MOSCAP region (310)….”. The arguments are not persuasive because in the rejection, the bottom position of the first gate structure 265 on the non-MOSCAP region was cited to meet the limitation of “a bottom surface of the first gate electrode adjacent to the first fin-shaped structure.” There is no fin between fin 211 and fin 212, therefore any regions between fin 211 (the first fin) could be considered “adjacent to the first fin-shaped structure”.
Please see the annotations in the attached reproduced Fig. 3H, which explains how Ponoth discloses the limitations of claim 8.
PNG
media_image1.png
759
1438
media_image1.png
Greyscale
Claim 8: a semiconductor device, comprising:
a substrate having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region and a MOSCAP region (Fig. 8H, the MOSCAP region is capacitor region including dielectric layer sandwiched between conductor structures 265 and 255, on the left side of the structure, another region is non-MOSCAP region);
a first fin-shaped structure and a second fin-shaped structure on the MOSCAP region (Fig. 8H, first fin-shaped structure 211 and a second fin-shaped structure 210 on the MOSCAP region); and
a first gate electrode on the first fin-shaped structure and the second fin-shaped structure (Fig. 3H, element 265, first gate electrode including structure 255 on both MOSCAP and non-MOSCAP regions, the first gate electrode is on the first fin-shaped structure 211and the second fin-shaped structure 210), wherein a bottom surface of the first gate electrode between the first fin-shaped structure and the second fin-shaped structure is higher than a bottom surface of the first gate electrode adjacent to the first fin-shaped structure (Fig. 3H, please also see the attached figure, bottom surface of the first gate electrode 265 between the first fin-shaped structure and the second fin-shaped structure, (which is bottom surface of the first gate electrode 265 in MOSCAP region), is located higher than the bottom surface of the first gate electrode adjacent to the first fin-shaped structure, (which is bottom surface of the first gate electrode 265 in non-MOSCAP region)).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 8-10 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ponoth et al. (U.S. Patent No. 9,941,271).
Regarding to claim 8, Ponoth teaches a semiconductor device, comprising:
a substrate (Fig. 3H; element 205; column 5, line 47) having a non-metal-oxide semiconductor capacitor (non-MOSCAP) region (Fig. 3H, right side of substrate 205; column 5, lines 3-4) and a MOSCAP region (Fig. 3H, left side of substrate 205; column 6, lines 19-20);
a first fin-shaped structure (Fig. 3H, elements 211; column 5, line 49) and a second fin-shaped structure (Fig. 3H, elements 210; column 5, line 49) on the MOSCAP region (Fig. 3H); and
a first gate electrode on the first fin-shaped structure and the second fin-shaped structure (Fig. 3H; element 265; column 7, line 22), wherein a bottom surface of the first gate electrode between the first fin-shaped structure and the second fin-shaped structure is higher than a bottom surface of the first gate electrode adjacent to the first fin-shaped structure (Fig. 3H, bottom surface of the first gate electrode 265 between the first fin-shaped structure 211 and the second fin-shaped structure 210 is higher than a bottom surface of the first gate electrode 265 in the non MOSCAP region adjacent to the first fin-shaped structure 211).
Regarding to claim 9, Ponoth teaches a gate oxide layer between the first gate electrode and the first fin-shaped structure (Fig. 3H, element 230; column 7, lines 1-2).
Regarding to claim 10, Ponoth teaches
a third fin-shaped structure on the non-MOSCAP region (Fig. 3H, elements 212; column 5, line 49); and
a shallow trench isolation (STI) around the third fin-shaped structure (Fig. 3H, element 215; column 5, line 62-64).
Regarding to claim 12, Ponoth teaches a second gate electrode on the third fin-shaped structure (Fig. 3H, element 265; column 5, line 8).
Regarding to claim 13, Ponoth teaches a bottom surface of the second gate electrode is higher than the bottom surface of the first gate electrode (Fig. 3H, a bottom surface of the second gate electrode 265, on top surface of fin 212, is higher than the bottom surface of the first gate electrode 265, between fins 210 and 211).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (U.S. Patent No. 9,941,271), as applied to claim 8 above, further in view of Liu et al. (U.S. Patent No. 11,521,971).
Regarding to claim 14, Ponoth does not disclose the non-MOSCAP region comprises an input/output (I/O) region. Liu discloses a non-MOSCAP region comprises an input/output (I/O) region (Fig. 3). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ponoth in view of Liu to comprise in the non-MOSCAP region an input/output (I/O) region in order to provide power and control signals to the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ponoth et al. (U.S. Patent No. 9,941,271), as applied to claim 8 above, further in view of Ie et al. (U.S. Patent No. 10,079,186).
Regarding to claim 15, Ponoth does not disclose the non-MOSCAP region comprises a low-voltage (LV) region. Liu discloses a non-MOSCAP region comprises a low-voltage (LV) region (Fig. 2, column 2, lines 60-62). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ponoth in view of Ie to comprise in the non-MOSCAP region a low-voltage (LV) region in order to provide flexibility to circuit design and system operation.
Allowable Subject Matter
Claims 1-7 are allowed.
Claim 11 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 1, the prior art fails to anticipate or render obvious the claimed limitations including “performing a second etching process to remove part of the STI on the non-MOSCAP region and the MOSCAP region immediately after the first etching process” in combination with the rest of limitations recited in claim 1.
Regarding to claim 11, the prior art fails to anticipate or render obvious the claimed limitations including “a maximum concentration of dopants in the third fin-shaped structure is less than a maximum concentration of dopants in the first fin-shaped structure” in combination with the limitations recited in claim 8 and claim 10.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/VU A VU/Primary Examiner, Art Unit 2897