DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over YANAGISAWA et al. (US PG Pub 2022/0270954, hereinafter Yanagisawa).
Regarding claim 12, figure 1 of Yanagisawa discloses a circuit comprising:
a plurality MOS transistor including:
a drain region (below drain electrode D);
a first source region and a second source region (below sections of source electrode S); and
a Pi or H shaped gate (G) and gate oxide layer (would be below gate electrode to form a functioning transistor), the Pi or H shaped gate including a first gate portion extending (21 on the far left) between the drain region and the first source region, a second gate portion (21 second from the left) parallel to the first gate portion and extending between the drain region and the second source region, and a first connecting gate portion (22A) transverse to the first and second gate portions and connecting the first and second gate portions.
Yanagisawa does not explicitly disclose a plurality of MOS transistors.
However, it would have been obvious to form a plurality of MOS transistors in order to form an integrated circuit device and also since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8
Regarding claim 13, figure 1 of Yanagisawa discloses the Pi or H shaped gate (G) is an H shaped gate that further includes a second connecting gate portion (22B) arranged parallel with the first connecting gate portion and also connecting the first and second gate portions, wherein the drain region (below drain electrode D) and the first and second source regions (below source electrode S) are disposed between the first connecting gate portion and the second connecting gate portion.
Allowable Subject Matter
Claims 1-11 and 14-20 are allowed.
Regarding claims 1 and 14, the prior art of record, either singularly or in combination, does not disclose or suggest the combination of limitations including “a Pi shaped or H shaped gate and gate oxide layer, the Pi or H shaped gate including a first gate portion extending between the emitter region and the first collector region, a second gate portion parallel to the first gate portion and extending between the emitter region and the second collector region, and a first connecting gate portion transverse to the first and second gate portions and connecting the first and second gate portions; and a first base region disposed underneath the first gate portion and a second base region disposed underneath the second gate portion”.
Conclusion
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/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
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