DETAILED ACTION
This office action is in response to the election filed 6/10/2026.
Currently, claims 1-20 are pending. Of these, claims 10 and 20 have been withdrawn from consideration.
Election/Restrictions
Applicant’s election without traverse of Species I is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/20/2023 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: ARRANGEMENT OF DRIVING VOLTAGE LINE IN DISPLAY APPARATUS
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 and 11-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “semiconductor layer” in lines 3, 5, 9 and 11. It is not clear what is meant by “semiconductor layer” in light of the disclosure. In line 3, the semiconductor layer is defined in part by the driving transistor comprising it. In other words, the semiconductor layer is a part to the whole of the driving transistor. Referencing FIG. 9, the semiconductor layer would be A1, which is a part of driving transistor T1. However, in line 5, the semiconductor layer is defined as one of two points between which the driving voltage line is located. Referencing FIG. 9, the driving voltage line is PL and thus the semiconductor layer would apparently be CE3, which is obviously different than A1. Furthermore, it would appear that CE3 is different from the claimed semiconductor layer, as lines 10-11 compare the third capacitor electrode (CE3) and the semiconductor layer as different entities (and similarly the comparison of the second capacitor electrode and the semiconductor layer in lines 8-9). Thus, it is not clear what exactly is meant by the limitation “semiconductor layer”.
Claim 11 recites the same limitation. Claims 2-9 and 12-19 recite the same limitation at least via dependency.
Allowable Subject Matter
As discussed above, the claims are not allowable because it is unclear what is meant by the limitation “semiconductor layer”. However, the disclosure does contain subject matter that has been identified as allowable. In particular, the combination of the following aspects is not taught by the prior art:
A driving transistor over a substrate and comprising a portion of a semiconductor layer for the source/channel/drain
An additional portion of the semiconductor layer at the same level as the portion used for the source/channel/drain of the driving transistor, which is used for the upper electrodes of both a holding capacitor and a storage capacitor
A driving voltage line located between the substrate and the portion of the semiconductor layer used for the upper electrode of the holding capacitor, wherein the driving voltage line functions as the lower electrode of the holding capacitor
A lower electrode of the storage capacitor at a same level as the driving voltage line
While prior art references such as Kim et al. (US 2023/0069761), Park et al. (US 2021/0327910), Shin et al. (US 10,002,916), Pyon (US 10,340,324), Park et al. (US 2021/0225292), Won et al. (US 12,127,449), Kim et al. (US 9,799,718), Lee et al. (US 10,340,316), Hwang (US 9,299,949), and Lee et al. (US 9,748,323) teach many of these features in isolation, they fail to teach the particular combination of features described above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL LUKE/Primary Examiner, Art Unit 2896
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