DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1-2, 6-8, 10-11, 15-17 and 19 in the Applicant’s response dated 17 December 2025. The claim amendments and the Applicant’s accompanying comments have been addressed below.
The Examiner acknowledges the amendment to the specification and therefore withdraws the objection to the drawings.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show “a tapered portion 141p” as described in para [0052] of the specification. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 6, the claim recites, “a first sacrificial layer formed…”, however the first sacrificial layer structure is not part of the final structure of the final device. The claim states “the semiconductor device of claim 5” wherein the semiconductor device appears to be the final device structure such as represented in at least Fig. 1A – Fig. 3B. As shown in at least Fig. 1A- Fig. 3B and the processing steps as described in Fig. 4, the first sacrificial layer is fully removed prior to the formation of the final device structure. Claim 6 appears to be directed to an intermediate device structure with respect to the language of a first sacrificial layer. Therefore, it is unclear to one of ordinary skill in the art how a semiconductor device, such as claimed in claim 1 and claim 3-5 can represent a final structure and embodiment of a device and then how claim 6 which is dependent upon claims 1 and 3-5, may further represent an intermediate structure different from the claims it depends upon.
Regarding Claim 7, the claim recites, “a second sacrificial layer formed…”, however the second sacrificial layer structure is not part of the final structure of the final device. The claim states “the semiconductor device of claim 6” wherein the semiconductor device appears to be the final device structure such as represented in at least Fig. 1A – Fig. 3B. As shown in at least Fig. 1A- Fig. 3B and the processing steps as described in Fig. 4, the second sacrificial layer is fully removed prior to the formation of the final device structure. Claim 7 appears to be directed to an intermediate device structure with respect to the language of a second sacrificial layer. Therefore, it is unclear to one of ordinary skill in the art how a semiconductor device, such as claimed in claim 1 and claim 3-5 can represent a final structure and embodiment of a device and then how claim 7 which is dependent upon claims 1 and 3-5, may further represent an intermediate structure different from the claims it depends upon.
Regarding Claim 8, the claim recites, “a material of the first sacrificial layer…” and “a material of the second sacrificial layer…”, however the first and second sacrificial structures are not part of the final structure of the final device. The claim states “the semiconductor device of claim 7” wherein the semiconductor device appears to be the final device structure such as represented in at least Fig. 1A – Fig. 3B. As shown in at least Fig. 1A- Fig. 3B and the processing steps as described in Fig. 4, the first sacrificial layer is fully removed prior to the formation of the final device structure. Claim 8 appears to be directed to an intermediate device structure with respect to the language of the first sacrificial layer and the second sacrificial layer. Therefore, it is unclear to one of ordinary skill in the art how a semiconductor device, such as claimed in claim 1 and claim 3-5 can represent a final structure and embodiment of a device and then how claim 8 which is dependent upon claims 1 and 3-5, may further represent an intermediate structure different from the claims it depends upon.
Claim 9 is rejected from its dependence upon claim 8.
Claims 15-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 15, the claim recites, “a first sacrificial layer formed…”, however the first sacrificial layer structure is not part of the final structure of the final device. The claim states “the semiconductor device of claim 10” wherein the semiconductor device appears to be the final device structure such as represented in at least Fig. 1A – Fig. 3B. As shown in at least Fig. 1A- Fig. 3B and the processing steps as described in Fig. 4, the first sacrificial layer is fully removed prior to the formation of the final device structure. Claim 15 appears to be directed to an intermediate device structure with respect to the language of a first sacrificial layer. Therefore, it is unclear to one of ordinary skill in the art how a semiconductor device, such as claimed in claim 10 can represent a final structure and embodiment of a device and then how claim 15 which is dependent upon claims 10, may further represent an intermediate structure different from the claims it depends upon.
Regarding Claim 16, the claim recites, “a second sacrificial layer formed…”, however the second sacrificial layer structure is not part of the final structure of the final device. The claim states “the semiconductor device of claim 15” wherein the semiconductor device appears to be the final device structure such as represented in at least Fig. 1A – Fig. 3B. As shown in at least Fig. 1A- Fig. 3B and the processing steps as described in Fig. 4, the second sacrificial layer is fully removed prior to the formation of the final device structure. Claim 16 appears to be directed to an intermediate device structure with respect to the language of a second sacrificial layer. Therefore, it is unclear to one of ordinary skill in the art how a semiconductor device, such as claimed in claim 10 can represent a final structure and embodiment of a device and then how claim 16 which is dependent upon claims 10, may further represent an intermediate structure different from the claims it depends upon.
Regarding Claim 17, the claim recites, “a material of the first sacrificial layer…” and “a material of the second sacrificial layer…”, however the first and second sacrificial structures are not part of the final structure of the final device. The claim states “the semiconductor device of claim 16” wherein the semiconductor device appears to be the final device structure such as represented in at least Fig. 1A – Fig. 3B. As shown in at least Fig. 1A- Fig. 3B and the processing steps as described in Fig. 4, the first sacrificial layer is fully removed prior to the formation of the final device structure. Claim 17 appears to be directed to an intermediate device structure with respect to the language of the first sacrificial layer and the second sacrificial layer. Therefore, it is unclear to one of ordinary skill in the art how a semiconductor device, such as claimed in claim 10 can represent a final structure and embodiment of a device and then how claim 17 which is dependent upon claims 10, may further represent an intermediate structure different from the claims it depends upon.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-7, 10 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using PE2E machine translation for English translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”).
Regarding Claim 1, Chen teaches a semiconductor device, comprising:
a substrate (100, Fig. 14, page 6 of the PE2E machine translation, describes as a substrate made of a silicon material);
a lower horizontal supporting layer disposed on the substrate (102, Fig. 14, page 9 of the PE2E machine translation describes an isolation layer that is part of the wrapping support structure and is comprised of the same material as the support structure);
an upper horizontal supporting layer disposed on the lower horizontal supporting layer (104, Fig. 14, page 9 of the PE2E machine translation describes a transverse support layer);
a vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer (105 from Fig. 13, Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer);
a first capacitor electrode disposed on the substrate and extending from the lower horizontal supporting layer to the upper horizontal supporting layer (106, Fig. 14, page 10 of the PE2E machine translation describes a lower electrode of the capacitor device); and
a middle horizontal supporting layer disposed between the lower horizontal supporting layer and the upper horizontal supporting layer (201, Fig. 14, page 9 of the PE2E machine translation describes a lower support layer 201 that is between lower horizontal supporting layer 102 and upper horizontal supporting layer 104);
wherein the first capacitor electrode is in contact with the lower horizontal supporting layer (Fig. 14, the first capacitor electrode 106 can be seen in contact with the lower horizontal support layer 102 in Fig. 14);
wherein the vertical supporting structure comprises a first pillar disposed between and in contact with the lower horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer and annotated Fig. 14 depicts wherein a lower portion of vertical supporting structure 105 comprising a first pillar is disposed between and in contact with lower horizontal supporting layer 102 and middle horizontal supporting layer 201), and a second pillar disposed between and in contact with the upper horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer and annotated Fig. 14 depicts wherein an upper portion of vertical supporting structure 105 comprising a second pillar is disposed between and in contact with upper horizontal supporting layer 104 and middle horizontal supporting layer 201).
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Chen fails to explicitly teach wherein a material of the first pillar is different from a material of the second pillar.
However, Chang teaches a similar semiconductor device, wherein a material of the first pillar (310, Fig. 10, para [012] describes a first filling layer 310 comprising a first pillar of a support structure 306 comprised of a boro-phospho-silicate glass material) is different from a material of the second pillar (316, Fig. 10, para [0012] describes a third filling layer 316 comprising a first second of a support structure 306 comprised of a silicon oxide material).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Chang to further disclose a semiconductor device wherein a material of a first pillar is different than a material of a second pillar in order to provide the advantage of enabling different etch selectivity’s of multiple layers so that a first support pillar and a second support pillar can be removed in different etching steps, improving accuracy when forming a bottom electrode layer thus providing a device with higher reliability (Chang, para [0022] and para [0024]).
Regarding Claim 3, the combination of Chen and Chang teaches the semiconductor device of claim 1, further comprising:
a capacitor dielectric (Chen, 107, Fig. 14, page 11 of the PE2E machine translation describes a capacitor dielectric layer); and
a second capacitor electrode spaced apart from the first capacitor electrode by the capacitor dielectric (Chen, 108, Fig. 14, page 11 of the PE2E machine translation describes as an upper electrode 108 of the capacitor device, which is spaced apart from the first electrode 106 by the capacitor dielectric 107),
wherein the second capacitor electrode is spaced apart from the vertical supporting structure (Chen, Fig. 14, the capacitor dielectric 107 and upper horizontal supporting layer 104 separate the vertical supporting structure 105 from the second capacitor electrode 108).
Regarding Claim 4, the combination of Chen and Chang teaches the semiconductor device of claim 3, wherein the capacitor dielectric is in contact with the vertical supporting structure (Chen, 107 and 105, Fig. 14 wherein capacitor dielectric 107 can be seen contacting the vertical supporting structure in Fig. 14).
Regarding Claim 5, the combination of Chen and Chang teaches the semiconductor device of claim 3, wherein the first capacitor electrode is spaced apart from the vertical supporting structure by the capacitor dielectric and the second capacitor electrode (Chen, annotated Fig. 14 II, wherein the first capacitor electrode can be seen spaced apart from the vertical supporting structure by the capacitor dielectric and second capacitor electrode in annotated Fig. 14 II below).
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Regarding Claim 6, the combination of Chen and Chang teaches the semiconductor device of claim 5, further comprising a first sacrificial layer (please see “product by process” paragraph below with respect to a first sacrificial layer) formed between the lower horizontal supporting layer (Chen, 102, Fig. 14, page 9 of the PE2E machine translation) and the middle horizontal supporting layer (Chen, 201, Fig. 14, page 9 of the PE2E machine translation);
wherein the first sacrificial layer has a first opening extended therethrough (please see reference to “product by process” above with respect to the first sacrificial layer);
wherein the first pillar (Chen, 105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation) is disposed in the first opening of first sacrificial layer (please see reference to “product by process” above with respect to the first sacrificial layer) and between the lower horizontal supporting layer and the middle horizontal supporting layer (Chen, 201, Fig. 14, page 9 of the PE2E machine translation).
Regarding the process limitations recited in claim 6 ("a first sacrificial layer formed…" wherein a first sacrificial layer is not a part of the semiconductor device final product as disclosed in claims 1-6 and final product Fig. 1A – Fig. 3B, therefore the first sacrificial layer does not import structural limitations to the semiconductor device), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding Claim 7, the combination of Chen and Chang teaches the semiconductor device of claim 6, further comprising a second sacrificial layer formed (please see “product by process” paragraph below with respect to a second sacrificial layer) between the upper horizontal supporting layer (Chen, 104, Fig. 14, page 9 of the PE2E machine translation) and the middle horizontal supporting layer (Chen, 201, Fig. 14, page 9 of the PE2E machine translation);
wherein the second sacrificial layer has a second opening extended therethrough (please see reference to “product by process” above with respect to the second sacrificial layer);
wherein the second pillar is disposed in the second opening of second sacrificial layer (please see reference to “product by process” above with respect to the first sacrificial layer) and between the upper horizontal supporting layer (Chen, 104, Fig. 14, page 9 of the PE2E machine translation) and the middle horizontal supporting layer (201, Fig. 14, page 9 of the PE2E machine translation).
Regarding the process limitations recited in claim 7 ("a second sacrificial layer formed…" wherein a second sacrificial layer is not a part of the semiconductor device final product as disclosed in claims 1-7 and final product Fig. 1A – Fig. 3B and 17A-17B, therefore the second sacrificial layer does not import structural limitations to the semiconductor device), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding Claim 10, Chen discloses a semiconductor device, comprising:
a substrate (100, Fig. 14, page 6 of the PE2E machine translation, describes as a substrate made of a silicon material);
a lower horizontal supporting layer disposed on and contacted with a top surface of the substrate (102, Fig. 14, page 9 of the PE2E machine translation describes an isolation layer that is part of the wrapping support structure and is comprised of the same material as the support structure);
an upper horizontal supporting layer disposed on the lower horizontal supporting layer (104, Fig. 14, page 9 of the PE2E machine translation describes a transverse support layer);
a first vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer (105 from Fig. 13, Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer);
a plurality of capacitor structures (106, Fig. 14, page 10 of the PE2E machine translation describes a lower electrode of the capacitor device, wherein a plurality of capacitor devices can be seen pictured in Fig. 14); and
a middle horizontal supporting layer disposed between the lower horizontal supporting layer and the upper horizontal supporting layer (201, Fig. 14, page 9 of the PE2E machine translation describes a lower support layer 201 that is between lower horizontal supporting layer 102 and upper horizontal supporting layer 104);
wherein the plurality of capacitor structures comprises a first capacitor (FC, annotated Fig. 14 IV below wherein component FC comprises a first capacitor) comprising a first capacitor electrode (106, Fig. 14, page 10 of the PE2E machine translation describes a lower electrode of the capacitor device as shown in Fig. 14 above) in contact with the lower horizontal supporting layer (106, annotated Fig. 14, the first capacitor electrode 106 can be seen in contact with the lower horizontal support layer 102 in annotated Fig. 14 above).
wherein the first vertical supporting structure comprises a first pillar disposed between and in contact with the lower horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer and annotated Fig. 14 depicts wherein a lower portion of vertical supporting structure 105 comprising a first pillar is disposed between and in contact with lower horizontal supporting layer 102 and middle horizontal supporting layer 201), and a second pillar disposed between and in contact with the upper horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer and annotated Fig. 14 depicts wherein an upper portion of vertical supporting structure 105 comprising a second pillar is disposed between and in contact with upper horizontal supporting layer 104 and middle horizontal supporting layer 201).
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Chen fails to disclose a second vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer; wherein the plurality of capacitor structures are disposed between the first vertical supporting structure and the second vertical supporting structure; wherein a material of the first pillar is different from a material of the second pillar.
However, Chang teaches a similar semiconductor device, comprising a second vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer (310 and 316, Fig. 10, para [0012] describes as a first filling layer 310 and third filling layer 316 which provides vertical support between the horizontal supporting layers 308 and 318 and is part of the supporting structure 306, wherein the first and second vertical supporting structures can be seen pictured in annotated Fig. 10 from Chang below);
wherein the plurality of capacitor structures are disposed between the first vertical supporting structure and the second vertical supporting structure (322, Fig. 10, para [0015] describes bottom electrode layers wherein there exists two capacitor electrodes in Fig. 10, representing a plurality of capacitor structures),
wherein a material of the first pillar (310, Fig. 10, para [012] describes a first filling layer 310 comprising a first pillar of a support structure 306 comprised of a boro-phospho-silicate glass material) is different from a material of the second pillar (316, Fig. 10, para [0012] describes a third filling layer 316 comprising a first second of a support structure 306 comprised of a silicon oxide material).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang to further disclose a semiconductor device that comprises a second vertical supporting structure to provide the further advantage of structural integrity when forming the capacitor device and preventing the electrode from collapsing during the manufacturing process of multiple capacitor structures in between vertical supports (Chang, para [0018]) and to further disclose a semiconductor device wherein a material of a first pillar is different than a material of a second pillar in order to provide the advantage of enabling different etch selectivity’s of multiple layers so that a first support pillar and a second support pillar can be removed in different etching steps, improving accuracy when forming a bottom electrode layer thus providing a device with higher reliability (Chang, para [0022] and para [0024]).
Regarding Claim 15, the combination of Chen and Chang teaches the semiconductor device of claim 10, further comprising a first sacrificial layer (please see “product by process” paragraph below with respect to a first sacrificial layer) formed between the lower horizontal supporting layer (Chen, 102, Fig. 14, page 9 of the PE2E machine translation) and the middle horizontal supporting layer (Chen, 201, Fig. 14, page 9 of the PE2E machine translation);
wherein the first sacrificial layer has a first opening extended therethrough (please see reference to “product by process” above with respect to the first sacrificial layer);
wherein the first pillar (Chen, 105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation) is disposed in the first opening of first sacrificial layer (please see reference to “product by process” above with respect to the first sacrificial layer) and between the lower horizontal supporting layer and the middle horizontal supporting layer (Chen, 201, Fig. 14, page 9 of the PE2E machine translation).
Regarding the process limitations recited in claim 15 ("a first sacrificial layer formed…" wherein a first sacrificial layer is not a part of the semiconductor device final product as disclosed in claims 10 and 16 and final product Fig. 1A – Fig. 3B, therefore the first sacrificial layer does not import structural limitations to the semiconductor device), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Regarding Claim 16, the combination of Chen and Chang teaches the semiconductor device of claim 15, further comprising a second sacrificial layer formed (please see “product by process” paragraph below with respect to a second sacrificial layer) between the upper horizontal supporting layer (Chen, 104, Fig. 14, page 9 of the PE2E machine translation) and the middle horizontal supporting layer (Chen, 201, Fig. 14, page 9 of the PE2E machine translation);
wherein the second sacrificial layer has a second opening extended therethrough (please see reference to “product by process” above with respect to the second sacrificial layer);
wherein the second pillar is disposed in the second opening of second sacrificial layer (please see reference to “product by process” above with respect to the first sacrificial layer) and between the upper horizontal supporting layer (Chen, 104, Fig. 14, page 9 of the PE2E machine translation) and the middle horizontal supporting layer (201, Fig. 14, page 9 of the PE2E machine translation).
Regarding the process limitations recited in claim 16 ("a second sacrificial layer formed…" wherein a second sacrificial layer is not a part of the semiconductor device final product as disclosed in claims 10 and 15-16 and final product Fig. 1A – Fig. 3B and 17A-17B, therefore the second sacrificial layer does not import structural limitations to the semiconductor device), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
Claims 2, 11-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using PE2E machine translation for English translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) and in further view of Seongmin Choo et al. (US 2020/0006345 A1; hereinafter “Choo”).
Regarding Claim 2, the combination of Chen and Chang discloses all the limitations of claim 1.
The combination of Chen and Chang teaches the semiconductor device of claim 1, wherein the first capacitor electrode is spaced apart from the vertical supporting structure (Chen, annotated Fig. 14, wherein the first capacitor electrode 106 can be seen spaced apart from the vertical supporting structure 105 in annotated Fig. 14)
The combination of Chen and Chang fails to explicitly disclose the semiconductor device of claim 1, wherein the first capacitor has a top tapered portion spaced apart from the upper horizontal layer.
However, Choo teaches a similar semiconductor device, wherein the first capacitor (120, Fig. 15, para [0015] describes a lower electrode 120 of a capacitor structure wherein a first capacitor FC can be seen below in annotated Fig. 15) has a top tapered portion (TT, annotated Fig. 15, para [0060] describes forming openings 217 wherein upon forming openings 217, portions of the lower electrodes 120 may be etched to form separation spaces SS further forming top tapered portions TT as shown in annotated Fig. 15) spaced apart from the upper horizontal layer (TT and USP, annotated Fig. 15, para [0060] describes wherein top tapered portions of lower electrode 120 of first capacitor structure FC may be spaced apart from upper horizontal support layers USP1 and USP2).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Choo to further disclose a semiconductor device that comprises atop tapered section of a first capacitor structure which is spaced apart form an upper horizontal support structure in order to provide the advantage of providing an upper support layer sufficient for providing reliable support while also increasing the usable area of the lower electrode of the first capacitor thus increasing the capacitance of the capacitor structures (Choo, para [0066] – para [0068]).
Regarding Claim 11, the combination of Chen and Chang discloses all the limitations of claim 10.
The combination of Chen and Chang teaches the semiconductor device of claim 10, wherein the first capacitor electrode is spaced apart from the vertical supporting structure (Chen, annotated Fig. 14, wherein the first capacitor electrode 106 can be seen spaced apart from the vertical supporting structure 105 in annotated Fig. 14 below)
The combination of Chen and Chang fails to explicitly disclose the semiconductor device of claim 1, wherein the first capacitor has a top tapered portion spaced apart from the upper horizontal layer.
However, Choo teaches a similar semiconductor device, wherein the first capacitor (120, Fig. 15, para [0015] describes a lower electrode 120 of a capacitor structure wherein a first capacitor FC can be seen in annotated Fig. 15) has a top tapered portion (TT, annotated Fig. 15, para [0060] describes forming openings 217 wherein upon forming openings 217, portions of the lower electrodes 120 may be etched to form separation spaces SS further forming top tapered portions TT as shown in annotated Fig. 15) spaced apart from the upper horizontal layer (TT and USP, annotated Fig. 15, para [0060] describes wherein top tapered portions of lower electrode 120 of first capacitor structure FC may be spaced apart from upper horizontal support layers USP1 and USP2).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Choo to further disclose a semiconductor device that comprises a top tapered section of a first capacitor structure which is spaced apart form an upper horizontal support structure in order to provide the advantage of providing an upper support layer sufficient for providing reliable support while also increasing the usable area of the lower electrode of the first capacitor thus increasing the capacitance of the capacitor structures (Choo, para [0066] – para [0068]).
Regarding Claim 12, the combination of Chen, Chang and Choo teaches the semiconductor device of claim 11, wherein the first capacitor further comprises:
a capacitor dielectric (Chen, 107, Fig. 14, page 11 of the PE2E machine translation describes a capacitor dielectric layer) and a second capacitor electrode spaced apart from the first capacitor electrode by the capacitor dielectric (Chen, 108, Fig. 14, page 11 of the PE2E machine translation describes as an upper electrode 108 of the capacitor device, which is spaced apart from the first electrode 106 by the capacitor dielectric 107),
wherein the second capacitor electrode is spaced apart from the first vertical supporting structure (Chen, Fig. 14, the capacitor dielectric 107 and upper horizontal supporting layer 104 separate the first vertical supporting structure 105 from the second capacitor electrode 108).
Regarding Claim 13, the combination of Chen, Chang and Choo teaches the semiconductor device of claim 12, wherein the capacitor dielectric of the first capacitor is in contact with the first vertical supporting structure (Chen, 107 and 105, Fig. 14 wherein capacitor dielectric 107 can be seen contacting the first vertical supporting structure 105 in Fig. 14).
Regarding Claim 14, the combination of Chen, Chang and Choo teaches the semiconductor device of claim 12, wherein the first capacitor electrode is spaced apart from the first vertical supporting structure by the capacitor dielectric and the second capacitor electrode (Chen, annotated Fig. 14 II, wherein the first capacitor electrode can be seen spaced apart from the vertical supporting structure by the capacitor dielectric and second capacitor electrode in annotated Fig. 14 II).
Regarding Claim 18, the combination of Chen, Chang and Choo discloses the semiconductor device of claim 11, wherein the first capacitor electrode is in contact with the lower horizontal supporting layer (Fig. 14, the first capacitor electrode 106 can be seen in contact with the lower horizontal support layer 102 in Fig. 14).
Claims 8-9, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using PE2E machine translation for English translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) and in further view of Dongkyun Park et al. (US 2012/00193761 A1; hereinafter “Park”).
Regarding Claim 8, the combination of Chen and Chang discloses all the limitations of claim 7.
The combination of Chen and Chang teaches the semiconductor device of claim 7, wherein a material of the first sacrificial layer (please see “product by process” paragraph below with respect to the first sacrificial layer) is different from the lower horizontal supporting layer (102, Fig. 14, page 9 of the PE2E machine translation describes an isolation layer that is part of the wrapping support structure and is comprised of the same material as the support structure), wherein a material of the second sacrificial layer (please see “product by process” paragraph below with respect to the second sacrificial layer) is different from the middle horizontal supporting layer (201, Fig. 14, page 9 of the PE2E machine translation describes a lower support layer 201 that may be comprised of silicon nitride that is between lower horizontal supporting layer 102 and upper horizontal supporting layer 104).
Regarding the process limitations recited in claim 8 ("a material of the first sacrificial layer" and “a material of the second sacrificial layer” wherein the first sacrificial layer and the second sacrificial layer is not a part of the semiconductor device final product as disclosed in claims 1-8 and final product Fig. 1A – Fig. 3B and 17A-17B, therefore the second sacrificial layer does not import structural limitations to the semiconductor device), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
The combination of Chen and Chang fails to explicitly disclose the semiconductor device of claim 7, wherein a width of the first pillar is different from a width of the second pillar.
However, Park teaches a similar semiconductor device, wherein a width of the first pillar (142, Fig. 10G, para [0051] describes a core support pattern 142 comprising a first pillar wherein para [0043] describes an opening 129 from which the core support pattern 142 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a lowest portion would comprise a first width) is different from a width of the second pillar (234, Fig. 10G, para [0051] describes a second core support pattern 234 comprising a second pillar wherein para [0082] describes an opening 217 from which the second core support pattern 234 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a width of the narrowing portion would comprise a width different from that of the width of the first pillar).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Park to further disclose a semiconductor device that comprises a width of a first pillar that is different from a width of a second pillar in order to provide the well-known advantage of simplifying the manufacturing process of a capacitor device by providing for an anisotropic etching process which does not require 90 degree angles when forming openings for capacitor components reducing the time and precision needed during the anisotropic etching process further reducing manufacturing cost.
Regarding Claim 9, the combination of Chen, Chang and Park teaches the semiconductor device of claim 8, wherein the first pillar (Chang, FP, annotated Fig. 10 II depicts a first pillar FP between a lower horizontal support layer 308 and a middle horizontal support layer 312) is free from vertically overlapping the second pillar (Chang, SP, annotated Fig. 10 II depicts a second pillar SP between a middle horizontal support layer 312 and an upper horizontal support layer 318).
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Regarding Claim 17, the combination of Chen and Chang discloses all the limitations of claim 16.
The combination of Chen and Chang teaches the semiconductor device of claim 16, wherein a material of the first sacrificial layer (please see “product by process” paragraph below with respect to the first sacrificial layer) is different from the lower horizontal supporting layer (102, Fig. 14, page 9 of the PE2E machine translation describes an isolation layer that is part of the wrapping support structure and is comprised of the same material as the support structure), wherein a material of the second sacrificial layer (please see “product by process” paragraph below with respect to the second sacrificial layer) is different from the middle horizontal supporting layer (201, Fig. 14, page 9 of the PE2E machine translation describes a lower support layer 201 that may be comprised of silicon nitride that is between lower horizontal supporting layer 102 and upper horizontal supporting layer 104).
Regarding the process limitations recited in claim 17 ("a material of the first sacrificial layer" and “a material of the second sacrificial layer” wherein the first sacrificial layer and the second sacrificial layer is not a part of the semiconductor device final product as disclosed in claim 11 and final product Fig. 1A – Fig. 3B and 17A-17B, therefore the second sacrificial layer does not import structural limitations to the semiconductor device), these would not carry patentable weight in this claim drawn to a structure, because distinct structure is not necessarily produced.
Note that a “product by process” claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); and In re Marosi et al., 218 USPQ 289, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Note that the applicant has the burden of proof in such cases, as the above case law makes clear.
The combination of Chen and Chang fails to explicitly disclose the semiconductor device of claim 16, wherein a width of the first pillar is different from a width of the second pillar.
However, Park teaches a similar semiconductor device, wherein a width of the first pillar (142, Fig. 10G, para [0051] describes a core support pattern 142 comprising a first pillar wherein para [0043] describes an opening 129 from which the core support pattern 142 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a lowest portion would comprise a first width) is different from a width of the second pillar (234, Fig. 10G, para [0051] describes a second core support pattern 234 comprising a second pillar wherein para [0082] describes an opening 217 from which the second core support pattern 234 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a width of the narrowing portion would comprise a width different from that of the width of the first pillar).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Park to further disclose a semiconductor device that comprises a width of a first pillar that is different from a width of a second pillar in order to provide the well-known advantage of simplifying the manufacturing process of a capacitor device by providing for an anisotropic etching process which does not require 90 degree angles when forming openings for capacitor components reducing the time and precision needed during the anisotropic etching process further reducing manufacturing cost.
Regarding Claim 19, the combination of Chen and Chang discloses all the limitations of claim 11.
The combination of Chen and Chang teaches the semiconductor device of claim 11, wherein a material of the first vertical supporting structure is the same as that of the lower horizontal supporting layer (Chen, page 15 of the PE2E machine translation describes wherein the vertical supporting structure 105 and the lower horizontal supporting structure 102 comprise the subject support structure which is comprised of a silicon nitride).
The combination of Chen and Chang fail to explicitly disclose the semiconductor device of claim 11, wherein the material of the first vertical supporting structure is different from that of the upper horizontal supporting layer.
However, Park teaches a similar semiconductor device, wherein the material of the first vertical supporting structure is different from that of the upper horizontal supporting layer (USP1 and USP2, Fig. 15, para [0031] and para [0033] describes wherein an upper horizontal supporting layer USP1 and USP2 may be comprised of a SiOC material and page 15 of the PE2E machine translation of Chen describes the first vertical supporting structure 105 may comprised of a silicon nitride, wherein upon combining the upper horizontal layer USP1 and USP2 of Park with the first vertical supporting structure 105 of Chen, a resulting material of the upper horizontal layer USP1 and USP2 of Park may be comprised of a different material than the first vertical supporting structure 105 of Chen).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Park to further disclose a semiconductor device that comprises an upper horizontal supporting structure comprised of a different material than a first vertical supporting structure in order to provide the well-known advantage of providing support structures which may have different etch selectivity’s so that upon etching sacrificial material to form a vertical support structure, an upper horizontal support structure may remain to provide adequate support for capacitor devices.
Response to Arguments
Applicant's arguments filed on 17 December 2925 have been fully considered but they are not persuasive.
Applicant submits that at least the combined structure of Chen and Chang fails to teach that “a first pillar in contact with the lower horizontal supporting layer and the middle horizontal supporting layer”, a second pillar in contact with the upper horizontal supporting layer and the middle horizontal supporting layer” and “a material of the first pillar is different form a material of the second pillar” as claimed in the present applicant. The Examiner respectfully disagrees. As outlined in the rejection above, the combination of Chen and Chang teaches a first pillar disposed between and in contact with the lower horizontal supporting layer and the middle horizontal supporting layer (Chen, 105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer and annotated Fig. 14 depicts wherein a lower portion of vertical supporting structure 105 comprising a first pillar is disposed between and in contact with lower horizontal supporting layer 102 and middle horizontal supporting layer 201), and a second pillar disposed between and in contact with the upper horizontal supporting layer and the middle horizontal supporting layer (Chen, 105, Fig. 13 and annotated Fig. 14, page 9 of the PE2E machine translation describes a longitudinal support layer and annotated Fig. 14 depicts wherein an upper portion of vertical supporting structure 105 comprising a second pillar is disposed between and in contact with upper horizontal supporting layer 104 and middle horizontal supporting layer 201) and wherein a material of the first pillar (Chang, 310, Fig. 10, para [012] describes a first filling layer 310 comprising a first pillar of a support structure 306 comprised of a boro-phospho-silicate glass material) is different from a material of the second pillar (Chang, 316, Fig. 10, para [0012] describes a third filling layer 316 comprising a first second of a support structure 306 comprised of a silicon oxide material). Furthermore, the Examiner has rejected claim 1 in view of the combination of Chen and Chang as outlined above.
Applicant’s arguments with respect to claims 1-9 and 11-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new grounds of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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