DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2 April 2026 has been entered.
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1-4 and 10-13 in the Applicant’s response dated 2 April 2026. The claim amendments have been addressed below.
The Examiner acknowledges the amendments to claims 8 and 17 and the cancellation of claims 6-7 and 15-16 in the Applicant’s response dated 2 April 2026 in lieu of the 35 U.S.C. 112(b) rejections presented in the previous office action. The 35 U.S.C. 112(b) rejections are therefore withdrawn.
The Examiner acknowledges the amendments to the drawings in the Applicant’s response dated 2 April 2026 in lieu of the drawing objections presented in the previous office action. The drawing objections are therefore withdrawn.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 appears to contain a grammatical error wherein claim 4 recites “… conformally forms on the first capacitor electrode” wherein the Examiner believes claim 4 is intended to recite “… conformally formed on the first capacitor electrode”.
Claim 13 appears to contain a grammatical error wherein claim 4 recites “… conformally forms on the first capacitor electrode” wherein the Examiner believes claim 4 is intended to recite “… conformally formed on the first capacitor electrode”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3-5 are rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using Espacenet machine translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) in further view of Janbo Zhang et al. (US 2022/0059647 A1; hereinafter “Zhang”).
Regarding Claim 1, Chen teaches a semiconductor device, comprising:
a substrate (100, Fig. 14, para [0087] describes as a substrate 100 made of a silicon material);
a lower horizontal supporting layer disposed on the substrate (102, Fig. 14, para [0090] describes an isolation layer 102 that is part of the wrapping support structure and is comprised of the same material as the support structure);
an upper horizontal supporting layer disposed on the lower horizontal supporting layer (104, Fig. 14, para [0090] describes a transverse support layer 104);
a vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer (105 from Fig. 13, Fig. 14, para [0089] describes a longitudinal support layer 105);
a first capacitor electrode disposed on the substrate and extending from the lower horizontal supporting layer to the upper horizontal supporting layer (106, Fig. 14, para [0093] describes a lower electrode 106 of the capacitor device); and
a middle horizontal supporting layer disposed between the lower horizontal supporting layer and the upper horizontal supporting layer (201, Fig. 14, para [0112] describes a lower support layer 201 that is between lower horizontal supporting layer 102 and upper horizontal supporting layer 104);
a capacitor dielectric (107, Fig. 14, para [0098] describes a capacitor dielectric layer 107) conformally formed on the lower horizontal supporting layer (107 and 102, Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the lower horizontal supporting layer 102), the middle horizontal supporting layer (107 and 201, Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the middle horizontal supporting layer 201), the upper horizontal supporting layer (107 and 104, Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the upper horizontal supporting layer 104), and the vertical supporting structure (105 and 105, Fig. 13 and Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the vertical supporting layer 105);
wherein the first capacitor electrode is in contact with the lower horizontal supporting layer (106, Fig. 14 depicts the first capacitor electrode 106 can be seen in contact with the lower horizontal support layer 102 in Fig. 14);
wherein the vertical supporting structure comprises a first pillar disposed between and in contact with the lower horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14 depicts wherein a lower portion of vertical supporting structure 105 comprising a first pillar is disposed between and in contact with lower horizontal supporting layer 102 and middle horizontal supporting layer 201), and a second pillar disposed between and in contact with the upper horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14 depicts wherein an upper portion of vertical supporting structure 105 comprising a second pillar is disposed between and in contact with upper horizontal supporting layer 104 and middle horizontal supporting layer 201).
wherein the capacitor dielectric is disposed on and in contact with a top surface of the lower horizontal supporting layer (107 and 102, Fig. 14 depicts wherein capacitor dielectric 107 is disposed on and in contact with a top surface of the lower horizontal supporting layer 102), disposed on and in contact with top and bottom surfaces of the middle horizontal supporting layer (107 and 201, Fig. 14 depicts wherein capacitor dielectric 107 is disposed on and in contact with a top surface and bottom surface of the middle horizontal supporting layer 201), disposed on and in contact with a bottom surface of the upper horizontal supporting layer (107 and 104, Fig. 14 depicts wherein capacitor dielectric 107 is disposed on and in contact with a bottom surface of the upper horizontal supporting layer 104).
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Chen fails to explicitly teach wherein a material of the first pillar is different from a material of the second pillar.
However, Chang teaches a similar semiconductor device, wherein a material of the first pillar (310, Fig. 10, para [012] describes a first filling layer 310 comprising a first pillar of a support structure 306 comprised of a boro-phospho-silicate glass material) is different from a material of the second pillar (316, Fig. 10, para [0012] describes a third filling layer 316 comprising a first second of a support structure 306 comprised of a silicon oxide material).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen with Chang to further disclose a semiconductor device wherein a material of a first pillar is different than a material of a second pillar in order to provide the advantage of enabling different etch selectivity’s of multiple layers so that a first support pillar and a second support pillar can be removed in different etching steps, improving accuracy when forming a bottom electrode layer thus providing a device with higher reliability (Chang, para [0022] and para [0024]).
The combination of Chen and Chang fails to explicitly disclose wherein the capacitor dielectric is disposed on and in contact with two lateral surfaces of the first pillar, and two lateral surfaces of the second pillar.
However, Zhang teaches a similar semiconductor device wherein a capacitor dielectric (21, annotated Fig. 10B, para [0059] describes a conformal capacitor dielectric layer 21) is disposed on and in contact with two lateral surfaces of a first pillar (FP2, annotated Fig. 10A, para [0066] describes wherein the capacitor dielectric 21 can be disposed on and in contact with two lateral surfaces of a guard ring structure 17 comprising a vertical support material including a first pillar FP2 between and in contact with a lower horizontal supporting layer 17 disposed on substrate 10 and a middle horizontal supporting layer 12), and two lateral surfaces of a second pillar (SP2, annotated Fig. 10A, para [0066] describes wherein the capacitor dielectric 21 can be disposed on and in contact with two lateral surfaces of a guard ring structure 17 comprising a vertical support material including a first pillar SP2 between and in contact with a middle horizontal supporting layer 12 and an upper horizontal supporting layer 18).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen and Chang with Zhang to further disclose a semiconductor device wherein a capacitor dielectric is disposed on and in contact with two lateral surfaces of a first pillar, and two lateral surfaces of a second pillar in order to provide the advantage of providing additional dielectric layers which may protect the guard ring structure and peripheral circuit region from etching in subsequent manufacturing steps which would negatively affect the device performance in the guard ring structure region and peripheral circuit region (Zhang, para [0051]) and to further provide the well-known advantage of extending the capacitor dielectric layer over surrounding device components therefore decreasing the possibility of parasitic capacitance to the peripheral circuit region.
Regarding Claim 3, the combination of Chen, Chang and Zhang teaches the semiconductor device of claim 1, further comprising:
a second capacitor electrode spaced apart from the first capacitor electrode by the capacitor dielectric (Chen, 108, Fig. 14, para [0098] describes an upper electrode 108 of the capacitor device, which is spaced apart from the first electrode 106 by the capacitor dielectric 107),
wherein the second capacitor electrode is spaced apart from the first pillar and the second pillar of the vertical supporting structure by the capacitor dielectric (Chen, Fig. 14 depicts the capacitor dielectric 107 and upper horizontal supporting layer 104 separate the first pillar and the second pillar of the vertical supporting structure 105 from the second capacitor electrode 108).
Regarding Claim 4, the combination of Chen, Chang and Zhang teaches the semiconductor device of claim 3, wherein the capacitor dielectric is in contact with and conformally formed on the first capacitor electrode (Chen, 107 and 106, Fig. 14 depicts wherein capacitor dielectric 107 can be seen contacting and conformally formed on the first capacitor electrode 106).
Regarding Claim 5, the combination of Chen, Chang and Zhang teaches the semiconductor device of claim 3, wherein the first capacitor electrode is spaced apart from the vertical supporting structure by the capacitor dielectric and the second capacitor electrode (Chen, 106, 107, 108 and 105, annotated Fig. 14 II depicts wherein the first capacitor electrode 106 is apart from the vertical supporting structure 105 by the capacitor dielectric 107 and second capacitor electrode 108).
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Claims 2 is rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using Espacenet machine translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) in further view of Janbo Zhang et al. (US 2022/0059647 A1; hereinafter “Zhang”) and in further view of Seongmin Choo et al. (US 2020/0006345 A1; hereinafter “Choo”).
Regarding Claim 2, the combination of Chen, Chang and Zhang discloses all the limitations of claim 1.
The combination of Chen, Chang and Zhang teaches the semiconductor device of claim 1, wherein the first capacitor electrode is spaced apart from the vertical supporting structure (Chen, annotated Fig. 14 depicts wherein the first capacitor electrode 106 can be seen spaced apart from the vertical supporting structure 105 in annotated Fig. 14)
The combination of Chen, Chang and Zhang fails to explicitly disclose the semiconductor device of claim 1, wherein the first capacitor electrode has a top tapered portion spaced apart from the upper horizontal layer, wherein the capacitor dielectric conformally forms on the top tapered portion of the first capacitor electrode.
However, Choo teaches a similar semiconductor device, wherein the first capacitor (120, Fig. 15, para [0015] describes a lower electrode 120 of a capacitor structure wherein a first capacitor FC can be seen below in annotated Fig. 15) has a top tapered portion (TT, annotated Fig. 15, para [0060] describes forming openings 217 wherein upon forming openings 217, portions of the lower electrodes 120 may be etched to form separation spaces SS further forming top tapered portions TT as shown in annotated Fig. 15) spaced apart from the upper horizontal layer (TT and USP, annotated Fig. 15, para [0060] describes wherein top tapered portions of lower electrode 120 of first capacitor structure FC may be spaced apart from upper horizontal support layers USP1 and USP2), wherein the capacitor dielectric conformally forms on the top tapered portion of the first capacitor electrode (140 and TT, annotated Fig. 15, para [0029] describes a dielectric layer 140 which may be conformally disposed on the top tapered portion TT of the lower electrode 120).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen, Chang and Zhang with Choo to further disclose a semiconductor device that comprises a top tapered portion of a first capacitor structure which is spaced apart form an upper horizontal support structure and further wherein a capacitor dielectric layer is conformally disposed on the top tapered portion in order to provide the advantage of providing an upper support layer sufficient for providing reliable support while also increasing the usable area of the lower electrode of the first capacitor thus increasing the capacitance of the capacitor structures (Choo, para [0066] – para [0068]).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using Espacenet machine translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) in further view of Janbo Zhang et al. (US 2022/0059647 A1; hereinafter “Zhang”) and in further view of and in further view of Dongkyun Park et al. (US 2012/0193761 A1; hereinafter “Park”).
Regarding Claim 8, the combination of Chen, Chang and Zhang discloses all the limitations of claim 1.
The combination of Chen, Chang and Zhang fails to explicitly disclose the semiconductor device of claim 1, wherein a width of the first pillar is different from a width of the second pillar.
However, Park teaches a similar semiconductor device, wherein a width of the first pillar (142, Fig. 10G, para [0051] describes a core support pattern 142 comprising a first pillar wherein para [0043] describes an opening 129 from which the core support pattern 142 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a lowest portion would comprise a first width) is different from a width of the second pillar (234, Fig. 10G, para [0051] describes a second core support pattern 234 comprising a second pillar wherein para [0082] describes an opening 217 from which the second core support pattern 234 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a width of the narrowing portion would comprise a width different from that of the width of the first pillar).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen, Chang and Zhang with Park to further disclose a semiconductor device that comprises a width of a first pillar that is different from a width of a second pillar in order to provide the well-known advantage of simplifying the manufacturing process of a capacitor device by providing for an anisotropic etching process which does not require 90 degree angles when forming openings for capacitor components reducing the time and precision needed during the anisotropic etching process further reducing manufacturing cost.
Regarding Claim 9, the combination of Chen, Chang, Zhang and Park teaches the semiconductor device of claim 8, wherein the first pillar (Chang, FP, annotated Fig. 10 II depicts a first pillar FP between a lower horizontal support layer 308 and a middle horizontal support layer 312) is free from vertically overlapping the second pillar (Chang, SP, annotated Fig. 10 II depicts a second pillar SP between a middle horizontal support layer 312 and an upper horizontal support layer 318).
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Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using Espacenet machine translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) in further view of Seongmin Choo et al. (US 2020/0006345 A1; hereinafter “Choo”).
Regarding Claim 10, Chen discloses a semiconductor device, comprising:
a substrate (100, Fig. 14, para [0087] describes as a substrate 100 made of a silicon material);
a lower horizontal supporting layer disposed on and contacted with a top surface of the substrate (102, Fig. 14, para [0090] describes an isolation layer 102 that is part of the wrapping support structure and is comprised of the same material as the support structure);
an upper horizontal supporting layer disposed on the lower horizontal supporting layer (104, Fig. 14, para [0090] describes a transverse support layer 104);
a first vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer (105 from Fig. 13, Fig. 14, para [0089] describes a longitudinal support layer 105);
a plurality of capacitor structures (106, Fig. 14, para [0093] describes a lower electrode 106 of the capacitor device wherein a plurality of capacitor devices can be seen pictured in Fig. 14); and
a middle horizontal supporting layer disposed between the lower horizontal supporting layer and the upper horizontal supporting layer (201, Fig. 14, para [0112] describes a lower support layer 201 that is between lower horizontal supporting layer 102 and upper horizontal supporting layer 104);
wherein the plurality of capacitor structures comprises a first capacitor (FC, annotated Fig. 14 IV depicts wherein component FC comprises a first capacitor) comprising a first capacitor electrode (106, Fig. 14, para [0093] describes a lower electrode 106 of the capacitor device as shown in Fig. 14 above) in contact with the lower horizontal supporting layer (106, annotated Fig. 14 depicts wherein the first capacitor electrode 106 can be seen in contact with the lower horizontal support layer 102) and a capacitor dielectric (107, Fig. 14, para [0098] describes a capacitor dielectric layer 107) conformally formed on the lower horizontal supporting layer (107 and 102, Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the lower horizontal supporting layer 102), the middle horizontal supporting layer (107 and 201, Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the middle horizontal supporting layer 201), the upper horizontal supporting layer (107 and 104, Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the upper horizontal supporting layer 104), and the vertical supporting structure (105 and 105, Fig. 13 and Fig. 14 depicts wherein capacitor dielectric 107 is conformally formed on the first vertical supporting layer 105);
wherein the first vertical supporting structure comprises a first pillar disposed between and in contact with the lower horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14 depicts wherein a lower portion of vertical supporting structure 105 comprising a first pillar is disposed between and in contact with lower horizontal supporting layer 102 and middle horizontal supporting layer 201), and a second pillar disposed between and in contact with the upper horizontal supporting layer and the middle horizontal supporting layer (105, Fig. 13 and annotated Fig. 14 depicts wherein an upper portion of vertical supporting structure 105 comprising a second pillar is disposed between and in contact with upper horizontal supporting layer 104 and middle horizontal supporting layer 201);
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Chen fails to disclose a second vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer; wherein the plurality of capacitor structures are disposed between the first vertical supporting structure and the second vertical supporting structure; wherein a material of the first pillar is different from a material of the second pillar.
However, Chang teaches a similar semiconductor device, comprising a second vertical supporting structure extending between the lower horizontal supporting layer and the upper horizontal supporting layer (310 and 316, Fig. 10, para [0012] describes as a first filling layer 310 and third filling layer 316 which provides vertical support between the horizontal supporting layers 308 and 318 and is part of the supporting structure 306, wherein the first and second vertical supporting structures can be seen pictured in annotated Fig. 10 from Chang below);
wherein the plurality of capacitor structures are disposed between the first vertical supporting structure and the second vertical supporting structure (322, Fig. 10, para [0015] describes bottom electrode layers wherein there exists two capacitor electrodes in Fig. 10, representing a plurality of capacitor structures),
wherein a material of the first pillar (310, Fig. 10, para [012] describes a first filling layer 310 comprising a first pillar of a support structure 306 comprised of a boro-phospho-silicate glass material) is different from a material of the second pillar (316, Fig. 10, para [0012] describes a third filling layer 316 comprising a first second of a support structure 306 comprised of a silicon oxide material).
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Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang to further disclose a semiconductor device that comprises a second vertical supporting structure to provide the further advantage of structural integrity when forming the capacitor device and preventing the electrode from collapsing during the manufacturing process of multiple capacitor structures in between vertical supports (Chang, para [0018]) and to further disclose a semiconductor device wherein a material of a first pillar is different than a material of a second pillar in order to provide the advantage of enabling different etch selectivity’s of multiple layers so that a first support pillar and a second support pillar can be removed in different etching steps, improving accuracy when forming a bottom electrode layer thus providing a device with higher reliability (Chang, para [0022] and para [0024]).
The combination of Chen and Chang fail to explicitly disclose wherein the first capacitor has a top tapered portion spaced apart from the upper horizontal layer; wherein the capacitor dielectric conformally forms on the top tapered portion of the first capacitor.
However, Choo teaches a similar semiconductor device, wherein the first capacitor (120, Fig. 15, para [0015] describes a lower electrode 120 of a capacitor structure wherein a first capacitor FC can be seen below in annotated Fig. 15) has a top tapered portion (TT, annotated Fig. 15, para [0060] describes forming openings 217 wherein upon forming openings 217, portions of the lower electrodes 120 may be etched to form separation spaces SS further forming top tapered portions TT as shown in annotated Fig. 15) spaced apart from the upper horizontal layer (TT and USP, annotated Fig. 15, para [0060] describes wherein top tapered portions of lower electrode 120 of first capacitor structure FC may be spaced apart from upper horizontal support layers USP1 and USP2), wherein the capacitor dielectric conformally forms on the top tapered portion of the first capacitor (140 and TT, annotated Fig. 15, para [0029] describes a dielectric layer 140 which may be conformally disposed on the top tapered portion TT of the lower electrode 120).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Choo to further disclose a semiconductor device that comprises a top tapered portion of a first capacitor structure which is spaced apart form an upper horizontal support structure and further wherein a capacitor dielectric layer is conformally disposed on the top tapered portion in order to provide the advantage of providing an upper support layer sufficient for providing reliable support while also increasing the usable area of the lower electrode of the first capacitor thus increasing the capacitance of the capacitor structures (Choo, para [0066] – para [0068]).
Claims 11-14 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using Espacenet machine translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) in further view of Seongmin Choo et al. (US 2020/0006345 A1; hereinafter “Choo”) and in further view of Janbo Zhang et al. (US 2022/0059647 A1; hereinafter “Zhang”).
Regarding Claim 11, the combination of Chen, Chang and Choo discloses all the limitations of claim 10.
The combination of Chen, Chang and Choo teaches the semiconductor device of claim 10, wherein the first capacitor electrode is spaced apart from the vertical supporting structure (Chen, annotated Fig. 14 depicts wherein the first capacitor electrode 106 can be seen spaced apart from the vertical supporting structure 105), wherein the capacitor dielectric is disposed on and in contact with a top surface of the lower horizontal supporting layer (Chen, 107 and 102, Fig. 14 depicts wherein capacitor dielectric 107 is disposed on and in contact with a top surface of the lower horizontal supporting layer 102), disposed on and in contact with top and bottom surfaces of the middle horizontal supporting layer (Chen, 107 and 201, Fig. 14 depicts wherein capacitor dielectric 107 is disposed on and in contact with a top surface and bottom surface of the middle horizontal supporting layer 201), disposed on and in contact with a bottom surface of the upper horizontal supporting layer (Chen, 107 and 104, Fig. 14 depicts wherein capacitor dielectric 107 is disposed on and in contact with a bottom surface of the upper horizontal supporting layer 104).
The combination of Chen, Chang and Choo fails to explicitly disclose wherein the capacitor dielectric is disposed on and in contact with two lateral surfaces of the first pillar, and two lateral surfaces of the second pillar.
However, Zhang teaches a similar semiconductor device wherein a capacitor dielectric (21, annotated Fig. 10B, para [0059] describes a conformal capacitor dielectric layer 21) is disposed on and in contact with two lateral surfaces of a first pillar (FP2, annotated Fig. 10A, para [0066] describes wherein the capacitor dielectric 21 can be disposed on and in contact with two lateral surfaces of a guard ring structure 17 comprising a vertical support material including a first pillar FP2 between and in contact with a lower horizontal supporting layer 17 disposed on substrate 10 and a middle horizontal supporting layer 12), and two lateral surfaces of a second pillar (SP2, annotated Fig. 10A, para [0066] describes wherein the capacitor dielectric 21 can be disposed on and in contact with two lateral surfaces of a guard ring structure 17 comprising a vertical support material including a first pillar SP2 between and in contact with a middle horizontal supporting layer 12 and an upper horizontal supporting layer 18).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chen and Chang with Zhang to further disclose a semiconductor device wherein a capacitor dielectric is disposed on and in contact with two lateral surfaces of a first pillar, and two lateral surfaces of a second pillar in order to provide the advantage of providing additional dielectric layers which may protect the guard ring structure and peripheral circuit region from etching in subsequent manufacturing steps which would negatively affect the device performance in the guard ring structure region and peripheral circuit region (Zhang, para [0051]) and to further provide the well-known advantage of extending the capacitor dielectric layer over surrounding device components therefore decreasing the possibility of parasitic capacitance to the peripheral circuit region.
Regarding Claim 12, the combination of Chen, Chang, Choo and Zhang teaches the semiconductor device of claim 11, wherein the first capacitor further comprises a second capacitor electrode spaced apart from the first capacitor electrode by the capacitor dielectric (Chen, 108, Fig. 14, para [0098] describes as an upper electrode 108 of the capacitor device which is spaced apart from the first electrode 106 by the capacitor dielectric 107),
wherein the second capacitor electrode is spaced apart from the first vertical supporting structure (Chen, Fig. 14 depicts wherein the capacitor dielectric 107 and upper horizontal supporting layer 104 separate the first vertical supporting structure 105 from the second capacitor electrode 108).
Regarding Claim 13, the combination of Chen, Chang, Choo and Zhang teaches the semiconductor device of claim 12, wherein the capacitor dielectric of the first capacitor is in contact with and conformally formed on the first capacitor electrode (Chen, 107 and 106, Fig. 14 depicts wherein capacitor dielectric 107 can be seen contacting conformally and formed on the first capacitor electrode 106).
Regarding Claim 14, the combination of Chen, Chang, Choo and Zhang teaches the semiconductor device of claim 12, wherein the first capacitor electrode is spaced apart from the first vertical supporting structure by the capacitor dielectric and the second capacitor electrode (Chen, annotated Fig. 14 II depicts wherein the first capacitor electrode can be seen spaced apart from the vertical supporting structure by the capacitor dielectric and second capacitor electrode).
Regarding Claim 18, the combination of Chen, Chang, Choo and Zhang discloses the semiconductor device of claim 11, wherein the first capacitor electrode is in contact with the lower horizontal supporting layer (Chen, 106 and 102, Fig. 14 depicts wherein the first capacitor electrode 106 can be seen in contact with the lower horizontal support layer 102 in Fig. 14).
Regarding Claim 19, the combination of Chen, Chang, Choo and Zhang discloses the semiconductor device of claim 11, wherein a material of the first vertical supporting structure is the same as that of the lower horizontal supporting layer (Chen, para [0116] describes wherein the vertical supporting structure 105 and the lower horizontal supporting structure 102 comprise the subject support structure which is comprised of a silicon nitride).
Chen fails to explicitly disclose wherein the material of the first vertical supporting structure is different from that of the upper horizontal supporting layer.
However, Choo teaches a similar semiconductor device, wherein the material of the first vertical supporting structure is different from that of the upper horizontal supporting layer (USP1 and USP2, Fig. 15, para [0031] and para [0033] describes wherein an upper horizontal supporting layer USP1 and USP2 may be comprised of a SiOC material and para [0116] of Chen describes the first vertical supporting structure 105 may comprised of a silicon nitride, wherein upon combining the upper horizontal layer USP1 and USP2 of Park with the first vertical supporting structure 105 of Chen, a resulting material of the upper horizontal layer USP1 and USP2 of Park may be comprised of a different material than the first vertical supporting structure 105 of Chen).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen, Chang, Zhang and Choo to further disclose a semiconductor device that comprises an upper horizontal supporting structure comprised of a different material than a first vertical supporting structure in order to provide the well-known advantage of providing support structures which may have different etch selectivity’s so that upon etching sacrificial material to form a vertical support structure, an upper horizontal support structure may remain to provide adequate support for capacitor devices.
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Wen-Li Chen et. al (CN 110970403 A using Espacenet machine translation; hereinafter “Chen”) in view of Feng-Yi Chang et. al (US 2019/0081134 A1; hereinafter “Chang”) in further view of Seongmin Choo et al. (US 2020/0006345 A1; hereinafter “Choo”) and in further view of Dongkyun Park et al. (US 2012/00193761 A1; hereinafter “Park”).
Regarding Claim 17, the combination of Chen, Chang and Choo discloses all the limitations of claim 10.
The combination of Chen, Chang and Choo fails to explicitly disclose the semiconductor device of claim 10, wherein a width of the first pillar is different from a width of the second pillar.
However, Park teaches a similar semiconductor device, wherein a width of the first pillar (142, Fig. 10G, para [0051] describes a core support pattern 142 comprising a first pillar wherein para [0043] describes an opening 129 from which the core support pattern 142 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a lowest portion would comprise a first width) is different from a width of the second pillar (234, Fig. 10G, para [0051] describes a second core support pattern 234 comprising a second pillar wherein para [0082] describes an opening 217 from which the second core support pattern 234 is disposed may have a gradually narrowing width as it approaches a lower portion, wherein a width of the narrowing portion would comprise a width different from that of the width of the first pillar).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teachings of Chen and Chang with Park to further disclose a semiconductor device that comprises a width of a first pillar that is different from a width of a second pillar in order to provide the well-known advantage of simplifying the manufacturing process of a capacitor device by providing for an anisotropic etching process which does not require 90 degree angles when forming openings for capacitor components reducing the time and precision needed during the anisotropic etching process further reducing manufacturing cost.
Response to Arguments
Applicant’s arguments with respect to claims 1-5, 8-14 and 17-19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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