DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim and Specification Status
The Examiner acknowledges the amendments to claims 1, 3, 14 and 16 in the Applicant’s response dated 22 July 2026. The claim amendments have been addressed below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Po-Yu Huang et al. (US 2022/0352326 A1; hereinafter “Huang”).
Regarding Claim 1, Huang teaches a semiconductor device comprising:
an active region (205, Fig. 30 and Fig. 31, para [0021] describes fin-shaped structures comprising active regions 205C and 205S/D);
a gate (210’, 213’ and 212’, Fig. 30 and Fig. 31, para [0044] and para [0032] describe a gate electrode layer 213’ and gate dielectric layer 212’ forming a gate structure 210’);
a gate electrode spacer formed on the sidewalls of the gate (216’, Fig. 30 and Fig. 31, para [0053] describes a gate electrode spacer 216’ comprising gate spacers 216a and 216b formed on sidewalls of the gate structure 210’);
a gate contact formed on the gate (254b, Fig. 30 and Fig. 31, para [0052] describes a gate contact via 254b formed on the gate 213’), the gate contact overlapping in plan view with at least a portion of the active region (254b, Fig. 31, para [0052] describes a plan view comprising gate contact 254b which can be seen overlapping active region 205 including 205C and 205 S/D in Fig. 30); and
a source/drain contact formed on the active region and adjacent to the gate contact (248, Fig. 30 and Fig. 31, para [0036] describes a drain contact formed on the active region comprising drain feature 232D and adjacent to gate contact 254b),
wherein the gate contact is offset from a centerline of the gate in a direction away from the source/drain contact (annotated Fig. 30 depicts wherein gate contact 254b is offset from a centerline C of the gate structure 213’ in a direction away from the source/drain contact 248), and
wherein a bottom surface of the gate contact is at a same level as a top surface of the gate electrode spacer (S, 254b and 216a, annotated Fig. 30, para [0052] describes wherein the gate contact 254b is formed directly on the gate spacer 216a therefore having a bottom surface of the gate contact at a same level as a top surface of the gate electrode spacer 216a as shown by surface S in annotated Fig. 30).
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Regarding Claim 2, Huang teaches the semiconductor device of claim 1, wherein the active region includes at least one source/drain epitaxial layer (232S and 232D, Fig. 30, para [0028] describes forming source epitaxial layer 232S and drain epitaxial layer 232D in the active region 205).
Regarding Claim 3, Huang teaches the semiconductor device of claim 2, wherein the source/drain contact is formed on the at least one source/drain epitaxial layer (248, Fig. 30, para [0036] describes forming drain contact 248 on drain epitaxial layer 232D).
Regarding Claim 4, Huang teaches the semiconductor device of claim 1, further comprising a substrate and a backside contact formed in the substrate (202, Fig. 30, para [0041] and para [0042] describes a substrate 202 selectively removed to form backside contact 268 wherein substrate 202 is replaced with dielectric layer 260 functioning as a backside replacement substrate as shown in Fig. 30), the backside contact formed on a side of the gate opposite to where the source/drain contact is located (268, Fig. 30 depicts backside contact 268 on a side of the gate 213’ opposite to where the source/drain contact 248 is located).
Regarding Claim 5, Huang teaches the semiconductor device of claim 1, wherein the gate contact extends beyond an edge of the gate on a side of the gate opposite to where the source/drain contact is located (254b, Fig 31 depicts wherein the gate contact 254b extends beyond an edge of the gate 213’ on a side of the gate opposite to where the source/drain contact 252 is located).
Regarding Claim 6, Huang teaches the semiconductor device of claim 5, further comprising a gate contact via formed on an extension portion of the gate contact (256, Fig. 30, para [0039] describes an interconnect structure 256 including contact vias formed on the gate contact 254b).
Regarding Claim 7, Huang teaches the semiconductor device of claim 1, wherein the gate contact partially covers the gate (254b and 213’, Fig. 30 and Fig. 31 depicts wherein gate contact 254b partially covers gate 213’).
Regarding Claim 8, Huang teaches the semiconductor device of claim 7, wherein a portion of the gate that is not covered by the gate contact is on a side of the gate nearer to the source/drain contact (213’ and 254b, Fig. 30 and Fig. 31 depicts wherein the portion of the gate 213’ not covered by gate contact 254b is on a side of the gate 213’ nearer to the source/drain contact 248).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Po-Yu Huang et al. (US 2022/0352326 A1; hereinafter “Huang”) in view of Ming-Hsiang Song et al. (US 2015/0129971 A1; hereinafter “Song”).
Regarding Claim 9, Huang discloses all the limitations of claim 1.
Huang fails to explicitly disclose the semiconductor device of claim 1, wherein the gate contact extends across a source/drain epitaxial layer and contacts a second gate.
However, Song teaches a similar semiconductor device, wherein the gate contact (1000, Fig. 8, para [0057] describes a multi-gate contact 1000) extends across a source/drain epitaxial layer (106, Fig. 8, para [0023] describes a second region 106 comprising a drain or source region) and contacts a second gate (130 and 140, Fig. 8, para [0027] and para [0028] describe a second gate 130, herein the first gate, and a third gate 140, herein the second gate, wherein gate contact 1000 contacts both the first gate 130 and second gate 140).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Huang with Song to further disclose a semiconductor device comprising a gate contact that extends across a source/drain epitaxial layer and contacts a second gate in order to provide the advantage of providing a contact which can dissipate heat across multiple gates resulting in a device with improved thermal conductivity in multi-gate devices increasing device performance (Song, para [0066]).
Regarding Claim 10, the combination of Huang and Song teaches the semiconductor device of claim 9, wherein the gate contact only partially covers the gate and only partially covers the second gate (Song, 1000, 130 and 140, Fig. 8 depicts wherein multi-gate contact 1000 partially covers gate 130 and second gate 140 wherein remaining portions not covered by gate contact 1000 are covered by dielectric surface 910 and 912).
Regarding Claim 11, the combination of Huang and Song teaches the semiconductor device of claim 9, further comprising a second source/drain contact in the active region adjacent to the second gate (Song, 254, Fig. 8, para [0035] describes a second source/drain contact 254 adjacent to the second gate 140 wherein second source/drain contact 254 contacts source/drain region 108).
Regarding Claim 12, the combination of Huang and Song teaches the semiconductor device of claim 11, wherein the gate contact is offset from a centerline of the second gate in a direction away from the second source/drain contact (Song, C2, annotated Fig. 8 depicts wherein gate contact 1000 is offset from a centerline of the second gate C2 in a direction away from the second source/drain contact 254 by at least a width of the second dielectric surface 912 overlapping the second gate 140).
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Regarding Claim 13, the combination of Huang and Song teaches the semiconductor device of claim 9, further comprising a substrate and a backside contact formed in the substrate (Huang, 202, Fig. 30, para [0041] and para [0042] describes a substrate 202 selectively removed to form backside contact 268 wherein substrate 202 is replaced with dielectric layer 260 functioning as a backside replacement substrate as shown in Fig. 30), the backside contact formed underneath the gate contact (Huang, 268, Fig. 30 depicts backside contact 268 formed underneath gate contact 254b).
Claims 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kyo-Suk Chae et al. (US 2012/0001271 A1; hereinafter “Chae”) in view of Po-Yu Huang et al. (US 2022/0352326 A1; hereinafter “Huang”).
Regarding Claim 14, Chae teaches a semiconductor device comprising:
an active region (ACT, Fig. 8A, para [0141] describes a device active region ACT);
a first gate (310a, Fig. 8a, para [0155] describes a first gate electrode 310a) and a second gate (310c, Fig. 8a, para [0155] describes a third gate electrode 310c herein referred to as the second gate electrode);
a first gate electrode spacer formed on the sidewalls of the first gate, and a second gate electrode spacer formed on sidewalls of the second gate (319, 310a and 310c, Fig. 8A and Fig. 8B, para [0155] describes wherein a gate spacer 319 may be formed on sidewalls of the first gate 310a and a second gate spacer 319 may be formed on sidewalls of the second gate 310c);
a first gate contact formed on the first gate (336a, Fig. 8a, para [0157] describes a first gate electrode 336a), and a second gate contact formed on the second gate (336c, Fig. 8a, para [0158] describes a second gate electrode 336c), the first gate contact and second gate contact overlapping in plan view with at least a portion of the active region (336a and 336c, Fig. 8a, para [0157] and para [0158] describes wherein first gate contact 336a and second gate contact 336c may overlap with the active region ACT); and
a first source/drain contact on the active region and adjacent to the first gate contact (340a, Fig. 8a, para [0160] describes a first drain contact 340a adjacent to the first gate contact 336a), and a second source/drain contact on the active region and adjacent to the second gate contact (340c, Fig. 8a, para [0160] describes a third drain contact 340c herein referred to as the second drain contact, adjacent to the first gate contact 336a),
wherein the first gate contact is offset from a centerline of the first gate in a first offset direction away from the first source/drain contact (FC and FD, annotated Fig. 8a depicts wherein the first gate contact 336a is offset from a centerline FC of the first gate 310a in a first offset direction FD away from the first source/drain contact 340a),
wherein the second gate contact is offset from a centerline of the second gate in a second offset direction away from the second source/drain contact (SC and SD, annotated Fig. 8a depicts wherein the second gate contact 336c is offset from a centerline SC of the second gate 310c in a second offset direction SD away from the second source/drain contact 340c),
wherein the first offset direction is different from the second offset direction (FD and SD, annotated Fig. 8a depicts wherein the first offset direction FD is different from the second offset direction SD wherein the first offset direction FD is opposite to the second offset direction SD).
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Chae fails to explicitly disclose wherein a bottom surface of the first gate contact is at a same level as a top surface of the first gate electrode spacer.
However, Huang teaches a similar semiconductor device wherein a bottom surface of the first gate contact (254b, Fig. 30 and Fig. 31, para [0052] describes a gate contact via 254b formed on a gate 213’) is at a same level as a top surface of the first gate electrode spacer (S, 254b and 216a, annotated Fig. 30, para [0052] describes wherein the first gate contact 254b is formed directly on a first gate spacer 216a therefore having a bottom surface of the first gate contact at a same level as a top surface of the first gate electrode spacer 216a as shown by surface S in annotated Fig. 30).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chae with Huang to further disclose a semiconductor device wherein a bottom surface of the first gate contact is at a same level as a top surface of the first gate electrode spacer in order to provide the advantage of disposing the a gate contact on a surface of a gate spacer therefore further increasing a distance between a gate contact and a drain contact decreasing parasitic capacitance in the semiconductor device (Huang, para [0052]).
Regarding Claim 15, the combination of Chae and Huang discloses all the limitations of claim 14.
Chae fails to explicitly disclose the semiconductor device of claim 14, wherein the active region includes at least one source/drain epitaxial layer.
However, Huang teaches a similar semiconductor device, wherein the active region includes at least one source/drain epitaxial layer (232S and 232D, Fig. 30, para [0028] describes forming source epitaxial layer 232S and drain epitaxial layer 232D in the active region 205).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chae with Huang to further disclose a semiconductor device wherein an active layer includes at least one source/drain epitaxial layer in order to provide the advantage of providing a source/drain feature in an active region through a suitable process to yield expected results wherein such a process includes epitaxial growth (Huang, para [0028]).
Regarding Claim 16, the combination of Chae and Huang teaches the semiconductor device of claim 15, wherein the first source/drain contact and second source/drain contact are formed on the at least one source/drain epitaxial layer (Chen, 340a and 340c, Fig. 8a, para [0160] describes wherein first source/drain contact 340a and second source/drain contact 340c may penetrate an interlayer dielectric layer to contact and underlying source/drain region 332a and 332c wherein said source/drain regions would be a result of an epitaxial process after combining Chen with Huang).
Regarding Claim 17, the combination of Chae and Huang discloses all the limitations of claim 14.
Chae fails to explicitly disclose the semiconductor device of claim 14, further comprising a substrate and a backside contact formed in the substrate, the backside contact formed on a side of the first gate opposite to where the first source/drain contact is located.
However, Huang teaches a similar semiconductor device, further comprising a substrate and a backside contact formed in the substrate (202, Fig. 30, para [0041] and para [0042] describes a substrate 202 selectively removed to form a backside contact 268 wherein substrate 202 is replaced with dielectric layer 260 functioning as a backside replacement substrate as shown in Fig. 30), the backside contact formed on a side of the first gate opposite to where the first source/drain contact is located (268, Fig. 30 depicts backside contact 268 on a side of a gate 213’ opposite to where a source/drain contact 248 is located).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chae with Huang to further disclose a semiconductor device comprising a backside contact located in a substrate on an opposite side of a first source/drain contact in order to provide the advantage of increasing the tolerance of processing errors during the formation of a gate contact via and eliminating the potential of a parasitic capacitance between a front side contact and a gate contact in a front side region of the source/drain opposite the backside contact structure (Huang, para [0044]).
Regarding Claim 18, the combination of Chae and Huang discloses all the limitations of claim 14.
Chae fails to explicitly disclose the semiconductor device of claim 14, wherein the first gate contact extends beyond an edge of the first gate on a side of the first gate opposite to where the first source/drain contact is located.
However, Huang teaches a similar semiconductor device, wherein the first gate contact extends beyond an edge of the first gate on a side of the first gate opposite to where the first source/drain contact is located (254b, Fig 31 depicts wherein a gate contact 254b extends beyond an edge of a gate 213’ on a side of the gate opposite to where a source/drain contact 252 is located).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filling date of the claimed invention to combine the teachings of Chae with Huang to further disclose a semiconductor device wherein the first gate contact extends beyond an edge of the first gate on a side of the first gate opposite to where the first source/drain contact is located in order to provide the advantage of enlarging a leakage window and reducing a parasitic capacitance between a gate contact and an adjacent source/drain contact (Huang, para [0052]).
Regarding Claim 19, the combination of Chae and Huang teaches the semiconductor device of claim 14, wherein the first gate contact partially covers the first gate (Huang, 254b and 213’, Fig. 30 and Fig. 31 depicts wherein gate contact 254b partially covers gate 213’).
Regarding Claim 20, the combination of Chae and Huang teaches the semiconductor device of claim 19, wherein a portion of the first gate that is not covered by the first gate contact is on a side of the first gate nearer to the first source/drain contact (213’ and 254b, Fig. 30 and Fig. 31 depicts wherein the portion of the gate 213’ not covered by gate contact 254b is on a side of the gate 213’ nearer to the source/drain contact 248).
Response to Arguments
Applicant's arguments filed 22 July 2026 have been fully considered but they are not persuasive. The Applicant argues on page 7, lines 4-12 and page 8, lines 1-6 of the Applicant’s remarks that the prior art of record, Huang, fails to disclose claim 1 as amended which recites the features “wherein a bottom surface of the gate contact is at a same level as a top surface of the gate electrode spacer”. The Examiner respectfully disagrees. As indicated in the 35 U.S.C. 102(a)(1) rejection above, the prior art of record, Huang, discloses wherein a bottom surface of the gate contact is at a same level as a top surface of the gate electrode spacer (S, 254b and 216a, annotated Fig. 30, para [0052] describes wherein the gate contact 254b is formed directly on the gate spacer 216a therefore having a bottom surface of the gate contact at a same level as a top surface of the gate electrode spacer 216a as shown by surface S in annotated Fig. 30). Therefore, a first bottom surface (S) of the gate electrode (254b) of Huang, is disposed on an upper surface (S) of the gate electrode spacer (216a) of Huang, as a result the bottom surface of the gate electrode (254b) and top surface of the gate electrode spacer (216a) are at a same level.
Applicant’s arguments, see page 8, lines 8-23 and page 9, lines 1-14, filed 22 July 202, with respect to the rejection of claims 14 under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of rejection is made in view of the prior art of record, Huang. As indicated above, the prior art of record, Huang, discloses wherein a bottom surface of the first gate contact (254b, Fig. 30 and Fig. 31, para [0052] describes a gate contact via 254b formed on a gate 213’) is at a same level as a top surface of the first gate electrode spacer (S, 254b and 216a, annotated Fig. 30, para [0052] describes wherein the first gate contact 254b is formed directly on a first gate spacer 216a therefore having a bottom surface of the first gate contact at a same level as a top surface of the first gate electrode spacer 216a as shown by surface S in annotated Fig. 30). Therefore, a first bottom surface (S) of the first gate electrode (254b) of Huang, is disposed on an upper surface (S) of the first gate electrode spacer (216a) of Huang, as a result the bottom surface of the first gate electrode (254b) and top surface of the first gate electrode spacer (216a) are at a same level.
The Applicant indicated in the Applicant’s remarks, see page 9, lines 15-20, filed 22 July 2026, that during the Applicant-initiated telephone interview with the Examiner on July 13, 2026, that the Examiner indicated the proposed amendments appear to overcome the current rejections. The Examiner respectfully disagrees. As indicated in the Examiner’s Interview Summary Record (EXIN), filed 17 July 2026, the Examiner and the Examiner’s Supervisor made the observation that the proposed amendments to claim 1 may appear to be disclosed by the prior art of record. The observations made by the Examiner and the Examiner’s Supervisor can be found in the rejection of claim 1 in view of the prior art of record, Huang, above as well as the response to arguments with respect to claim 1 above, wherein Huang teaches the proposed amendments outlined in the Email Correspondence attached to the Interview Summary filed 17 July 2026.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER M MILLER whose telephone number is (571)272-6051. The examiner can normally be reached Monday - Friday 8:00 am - 4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571(272)-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER MICHAEL MILLER/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
